MOTOROLA SN74LS251DR2, SN74LS251MEL, SN74LS251ML1, SN74LS251MR1, SN74LS251N Datasheet

 Semiconductor Components Industries, LLC, 1999

December, 1999 – Rev. 6

1 Publication Order Number:

SN74LS251/D

SN74LS251

8-Input Multiplexer
with 3-State Outputs

The TTL/MSI SN74LS251 is a high speed 8-Input Digital
Multiplexer. It provides, in one package, the ability to select one bit of
data from up to eight sources. The LS251 can be used as a universal
function generator to generate any logic function of four variables.
Both assertion and negation outputs are provided.

• Schottky Process for High Speed

• Multifunction Capability

• On-Chip Select Logic Decoding

• Inverting and Non-Inverting 3-State Outputs

• Input Clamp Diodes Limit High Speed Termination Effects

GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit

V

CC

Supply Voltage 4.75 5.0 5.25 V

T

A

Operating Ambient

T emperature Range

0 25 70 °C

I

OH

Output Current – High –2.6 mA

I

OL

Output Current – Low 24 mA

LOW

POWER

SCHOTTKY

Device Package Shipping

ORDERING INFORMATION

SN74LS251N 16 Pin DIP 2000 Units/Box
SN74LS251D 16 Pin

SOIC

D SUFFIX

CASE 751B

http://onsemi.com

2500/Tape & Reel

PLASTIC
N SUFFIX
CASE 648

16

1

16

1

SN74LS251

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2

CONNECTION DIAGRAM DIP (TOP VIEW)

Select Inputs
Output Enable (Active LOW) Inputs
Multiplexer Inputs
Multiplexer Output
Complementary Multiplexer Output

S

0

– S

2

E

0

I0 – I

7

Z
Z

0.5 U.L.

0.5 U.L.

0.5 U.L.
65 U.L.
65 U.L.

0.25 U.L.

0.25 U.L.

0.25 U.L.
15 U.L.
15 U.L.

NOTES:

a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.

HIGH LOW

(Note a)LOADING

PIN NAMES

LOGIC DIAGRAM

1412

6

7

34

5

9

11

12

10

1315

VCC = PIN 16
GND = PIN 8

= PIN NUMBERS

S

2

S

1

S

0

E

1

ZZ

I

0

I

1

I

2

I

3

I

4

I

5

I

6

I

7

14 13 12 11 10 9

123456

7

16 15

8

V

CC

I

3

I4I5I6I

7

S

1

S

0

S

2

I2I

1I0

ZZE0GND

SN74LS251

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3

FUNCTIONAL DESCRIPTION

The LS251 is a logical implementation of a single pole,
8-position switch with the switch position controlled by the
state of three Select inputs, S

0

, S1, S2. Both assertion and
negation outputs are provided. The Output Enable input
(EO) is active LOW . When it is activated, the logic function
provided at the output is:

Z = E

O

⋅ (I

0

⋅ S

0

⋅ S

1

⋅ S2+ I

1

⋅ S

0

⋅ S

1

⋅ S

2

+ I

2

⋅ S

0

⋅ S

1

⋅

Z = E

O

⋅ S

2

+ I

3

⋅ S

0

⋅ S1⋅ S

2

+ I

4

⋅ S

0

⋅ S

1

⋅ S

2

+ I

5

⋅ S

0

⋅

Z = E

O

⋅ S

1

⋅ S

2

+ I

6

⋅ S

0

⋅ S

1

⋅ S

2

+ I

7

⋅ S

0

⋅ S

1

⋅ S2).

When the Output Enable is HIGH, both outputs are in the
high impedance (high Z) state. This feature allows
multiplexer expansion by tying the outputs of up to 128
devices together. When the outputs of the 3-state devices are
tied together, all but one device must be in the high
impedance state to avoid high currents that would exceed the
maximum ratings. The Output Enable signals should be
designed to ensure there is no overlap in the active LOW
portion of the enable voltage.

TRUTH TABLE

E0S2S1S0I0I

1I2I3I4I5I6

I

7

Z Z

H X X X X X X X X X X X (Z) (Z)
L L LLLXXXXXX XHL
L L LLHXXXXXX XLH
L L LHXLXXXXX XHL
L L LHXHXXXXX XLH
L L HLXXLXXXX XHL
L L HLXXHXXXX XLH
L L HHXXXLXXX XHL
L L HHXXXHXXX XLH
L H LLXXXXLXX XHL
L H LLXXXXHXX XLH
L H LHXXXXXLX XHL
L H LHXXXXXHX XLH
L H HLXXXXXXL XHL
L H HLXXXXXXH XLH
L H HHXXXXXXX LHL
L H H H X X X X X X X H L H

H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
(Z) = High impedance (Off)

SN74LS251

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4

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits

Symbol Parameter

Min Typ Max

Unit Test Conditions

V

IH

Input HIGH Voltage 2.0 V

Guaranteed Input HIGH Voltage for
All Inputs

V

IL

Input LOW Voltage

0.8
V

Guaranteed Input LOW Voltage for
All Inputs

V

IK

Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA

V

OH

Output HIGH Voltage 2.4 3.1 V

VCC = MIN, IOH = MAX, VIN = V

IH

or VIL per Truth Table

p

0.25 0.4 V IOL = 12 mA

VCC = VCC MIN,

VOLOutput LOW Voltage

0.35 0.5 V IOL = 24 mA

V

IN

=

V

IL

or

V

IH

per Truth Table

I

OZH

Output Off Current HIGH 20 µA VCC = MAX, V

OUT

= 2.7 V

I

OZL

Output Off Current LOW –20 µA VCC = MAX, V

OUT

= 0.4 V

p

20 µA VCC = MAX, VIN = 2.7 V

IIHInput HIGH Current

0.1 mA VCC = MAX, VIN = 7.0 V

I

IL

Input LOW Current –0.4 mA VCC = MAX, VIN = 0.4 V

I

OS

Short Circuit Current (Note 1) –30 –130 mA VCC = MAX

pp

10 mA VCC = MAX, VE = 0 V

ICCPower Supply Current

12 mA VCC = MAX, VE = 4.5 V

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (T

A

= 25°C, VCC = 5.0 V)

Limits

Symbol Parameter

Min Typ Max

Unit Test Conditions

t

PLH

t

PHL

Propagation Delay,
Select to Z

Output

20
21

33
33

ns Figure 1

t

PLH

t

PHL

Propagation Delay,
Select to Z Output

29
28

45
45

ns Figure 2

t

PLH

t

PHL

Propagation Delay,
Data to Z

Output

10

9.0

15
15

ns Figure 1

CL = 15 pF,

t

PLH

t

PHL

Propagation Delay,
Data to Z Output

17
18

28
28

ns Figures 2

L

RL = 2.0 kΩ

t

PZH

t

PZL

Output Enable Time
to Z

Output

17
24

27
40

ns Figures 4, 5

t

PZH

t

PZL

Output Enable Time
to Z Output

30
26

45
40

ns Figures 3, 5

t

PHZ

t

PLZ

Output Disable Time
to Z

Output

37
15

55
25

ns Figures 3, 5

CL = 5.0 pF,

t

PHZ

t

PLZ

Output Disable Time
to Z Output

30
15

45
25

ns Figures 4, 5

L

RL = 667 kΩ

SN74LS251

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5

3-STATE AC WAVEFORMS

1.3 V

1.3 V 1.3 V

1.3 V

V

IN

V

OUT

t

PLH

t

PHL

1.3 V

1.3 V

V

IN

V

OUT

SW2CL*

5 kΩ

SW1

V

CC

R

L

TO OUTPUT

UNDER TEST

1.3 V

t

PHL

t

PLH

1.3 V

Figure 1. Figure 2.

Figure 3. Figure 4.

Figure 5.

1.3 V

1.3 V 1.3 V

V

E

V

OUT

V

E

V

OUT

t

PHZ

1.3 V 1.3 V

t

PZL

t

PLZ

V

OL

1.3 V

≥ V

OH

0.5 V

t

PZH

* Includes Jig and Probe Capacitance.

AC LOAD CIRCUIT

≈ 1.3 V

0.5 V

≈ 1.3 V

0.5 V

SWITCH POSITIONS

Closed

Open
Closed
Closed

Open
Closed
Closed
Closed

t

PZH

t

PZL

t

PLZ

t

PHZ

SW2SW1SYMBOL

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6

P ACKAGE DIMENSIONS

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

ISSUE R

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

–A–

B

F

C

S

H

G

D

J

L

M

16 PL

SEATING

18

916

K

PLANE

–T–

M

A

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01

____

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7

P ACKAGE DIMENSIONS

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

18

16 9

SEATING

PLANE

F

J

M

R

X 45

_

G

8 PLP

–B–

–A–

M

0.25 (0.010) B

S

–T–

D

K

C

16 PL

S

B

M

0.25 (0.010) A

S

T

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019

F 0.40 1.25 0.016 0.049

G 1.27 BSC 0.050 BSC

J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7

P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019

____

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8

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