MOTOROLA SN74LS156N, SN74LS156D, SN74LS156DR2, SN74LS156ML1 Datasheet

5-1
FAST AND LS TTL DAT A
DUAL 1-OF-4 DECODER/ DEMULTIPLEXER
The SN54/74LS155 and SN54/74LS156 are high speed Dual 1-of-4 Decoder/Demultiplexers. These devices have two decoders with common 2-bit Address inputs and separate gated Enable inputs. Decoder “a” has an Enable gate with one active HIGH and one active LOW input. Decoder “b” has two active LOW Enable inputs. If the Enable functions are satisfied, one output of each decoder will be LOW as selected by the address inputs. The LS156 has open collector outputs for wired-OR (DOT-AND) decoding and function generator applications.
The LS155 and LS156 are fabricated with the Schottky barrier diode process for high speed and are completely compatible with all Motorola TTL families.
Schottky Process for High Speed
Multifunction Capability
Common Address Inputs
True or Complement Data Demultiplexing
Input Clamp Diodes Limit High Speed Termination Effects
ESD > 3500 Volts
CONNECTION DIAGRAM DIP (TOP VIEW)
NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.
14 13 12 11 10 9
123456
7
16 15
8
V
CC
E
a
EbEbA0O
3b
O
1b
O
2b
O
0b
EaA1O3aO2aO1aO0aGND
PIN NAMES LOADING (Note a)
HIGH
LOW
A0, A
1
E
a
, E
b
E
a
O
0–O3
Address Inputs Enable (Active LOW) Inputs Enable (Active HIGH) Input Active LOW Outputs (Note b)
0.5 U.L.
0.5 U.L.
0.5 U.L. 10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
NOTES: a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
Temperature Ranges. The HIGH level drive for the LS156 must be established by an external resistor.
SN54 /74LS155 SN54 /74LS156
DUAL 1-OF-4 DECODER/
DEMULTIPLEXER
LS156-OPEN-COLLECTOR
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
16
1
16
1
ORDERING INFORMATION
SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXD SOIC
16
1
D SUFFIX
SOIC
CASE 751B-03
LOGIC SYMBOL
VCC = PIN 16 GND = PIN 8
1 2 13 3 1415
EE
A
0
A
0
A
1
A
1
0123 0123
DECODER a DECODER b
7 6 5 4 9 10 11 12
5-2
FAST AND LS TTL DATA
SN54/74LS155 SN54/74LS156
LOGIC DIAGRAM
EaE
a
A0A
1
EbE
b
O0aO1aO2aO3aO0bO
1bO2bO3b
1412
67
3
45 9 11 1210
13 15
VCC = PIN 16 GND = PIN 8
= PIN NUMBERS
FUNCTIONAL DESCRIPTION
The LS155 and LS156 are Dual 1-of-4 Decoder/Demulti­plexers with common Address inputs and separate gated Enable inputs. When enabled, each decoder section accepts the binary weighted Address inputs (A0, A1) and provides four mutually exclusive active LOW outputs (O
0–O3
). If the Enable requirements of each decoder are not met, all outputs of that decoder are HIGH.
Each decoder section has a 2-input enable gate. The enable gate for Decoder “a” requires one active HIGH input and one active LOW input (Ea•E
a
). In demultiplexing applica­tions, Decoder “a” can accept either true or complemented data by using the E
a
or Ea inputs respectively. The enable gate
for Decoder “b” requires two active LOW inputs (E
b•Eb
). The LS155 or LS156 can be used as a 1-of-8 Decoder/Demulti­plexer by tying Ea to E
b
and relabeling the common connection
as (A2). The other E
b
and Ea are connected together to form
the common enable.
The LS155 and LS156 can be used to generate all four minterms of two variables. These four minterms are useful in some applications replacing multiple gate functions as shown in Fig. a. The LS156 has the further advantage of being able to
AND the minterm functions by tying outputs together. Any number of terms can be wired-AND as shown below.
f = (E + A0 + A1) (E + A
0
+ A1) (E + A0 + A1)
(E + A
0
+ A1)
where E = Ea + E
a
; E = Eb + E
b
Figure a
E
A
0
A
1
E
A
0
A
1
E
A
0
A
1
E
A
0
A
1
O
0
O
1
O
2
O
3
E
A
0
A
1
E
A
0
A
1
E
A
0
A
1
E
A
0
A
1
O
0
O
1
O
2
O
3
TRUTH TABLE
ADDRESS ENABLE “a” OUTPUT “a” ENABLE “b” OUTPUT “b”
A
0
A
1
E
a
E
a
O
0
O
1
O
2
O
3
E
b
E
b
O
0
O
1
O
2
O
3
X X L X H H H H H X H H H H X XXHHHHHXHHHHH LLHLLHHHL LLHHH HLHLHLHHLLHLHH LHHLHHLHLLHHLH HHHLHHHLLLHHHL
H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care
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