5-2
FAST AND LS TTL DATA
SN54/74LS155 • SN54/74LS156
LOGIC DIAGRAM
EaE
a
A0A
1
EbE
b
O0aO1aO2aO3aO0bO
1bO2bO3b
1412
67
3
45 9 11 1210
13 15
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
FUNCTIONAL DESCRIPTION
The LS155 and LS156 are Dual 1-of-4 Decoder/Demultiplexers with common Address inputs and separate gated
Enable inputs. When enabled, each decoder section accepts
the binary weighted Address inputs (A0, A1) and provides four
mutually exclusive active LOW outputs (O
0–O3
). If the Enable
requirements of each decoder are not met, all outputs of that
decoder are HIGH.
Each decoder section has a 2-input enable gate. The
enable gate for Decoder “a” requires one active HIGH input
and one active LOW input (Ea•E
a
). In demultiplexing applications, Decoder “a” can accept either true or complemented
data by using the E
a
or Ea inputs respectively. The enable gate
for Decoder “b” requires two active LOW inputs (E
b•Eb
). The
LS155 or LS156 can be used as a 1-of-8 Decoder/Demultiplexer by tying Ea to E
b
and relabeling the common connection
as (A2). The other E
b
and Ea are connected together to form
the common enable.
The LS155 and LS156 can be used to generate all four
minterms of two variables. These four minterms are useful in
some applications replacing multiple gate functions as shown
in Fig. a. The LS156 has the further advantage of being able to
AND the minterm functions by tying outputs together. Any
number of terms can be wired-AND as shown below.
f = (E + A0 + A1) ⋅ (E + A
0
+ A1) ⋅ (E + A0 + A1) ⋅
(E + A
0
+ A1)
where E = Ea + E
a
; E = Eb + E
b
Figure a
E
A
0
A
1
E
A
0
A
1
E
A
0
A
1
E
A
0
A
1
O
0
O
1
O
2
O
3
E
A
0
A
1
E
A
0
A
1
E
A
0
A
1
E
A
0
A
1
O
0
O
1
O
2
O
3
TRUTH TABLE
ADDRESS ENABLE “a” OUTPUT “a” ENABLE “b” OUTPUT “b”
A
0
A
1
E
a
E
a
O
0
O
1
O
2
O
3
E
b
E
b
O
0
O
1
O
2
O
3
X X L X H H H H H X H H H H
X XXHHHHHXHHHHH
LLHLLHHHL LLHHH
HLHLHLHHLLHLHH
LHHLHHLHLLHHLH
HHHLHHHLLLHHHL
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care