MOTOROLA MPC7400 Technical data

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Order Number: MPC7400EC/D

Rev. 1.1, 11/2000

Semiconductor Products Sector

™

Advance Information

MPC7400 RISC Microprocessor
Hardware Specifications

The MPC7400 is an implementation of the PowerPC™ family of reduced instruction set computing (RISC)
microprocessors. This document describes pertinent electrical and physical characteristics of the MPC7400.
For functional characteristics of the processor, refer to the MPC7400 RISC Microprocessor User’s Manual.

This document contains the following topics:

Topic Page

Section 1.1, “Overview” 2
Section 1.2, “Features” 4
Section 1.3, “General Parameters” 7
Section 1.4, “Electrical and Thermal Characteristics” 7
Section 1.5, “Pin Assignments” 25
Section 1.6, “Pinout Listings” 26
Section 1.7, “Package Description” 29
Section 1.8, “System Design Information” 31
Section 1.9, “Document Revision History” 43
Section 1.10, “Ordering Information” 43

To locate updates for this document, refer to the website at http://www.motorola.com/sps. For the most
current part errata document, please contact your Motorola Sales Office.

This document contains information on a new product under development by Motorola.
Motorola reserves the right to change or discontinue this product without notice.

© Motorola, Inc., 2000. All rights reserved.

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Overview

1.1 Overview

The MPC7400 is the first implementation of the fourth generation (G4) of PowerPC microprocessors from
Motorola. The MPC7400 implements the full PowerPC 32-bit architecture and is targeted at both portable
and computing systems applications. Some comments on the MPC7400 (with respect to MPC750):

• The MPC7400 adds an implementation of the new AltiVec™ technology instruction set

• The MPC7400 includes significant improvements in memory subsystem (MSS) bandwidth and
offers an optional, high-bandwidth MPX bus interface

• The MPC7400 adds full hardware-based multiprocessing capability, including a 5-state cache
coherency protocol (4 MESI states plus a fifth state for shared intervention)

• The MPC7400 is implemented in a next generation process technology for core frequency
improvement

• The MPC7400 floating-point unit has been improved to make latency equal for double-precision
and single-precision operations involving multiplication

• The completion queue has been extended to 8 slots

• There are no other significant changes to scalar pipelines, decode/dispatch/completion mechanisms,
or the branch unit. The MPC750’s 4-stage pipeline model is unchanged (fetch, decode/dispatch,
execute, complete/writeback)

Figure 1 shows a block diagram of the MPC7400.

2

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Overview

128-Bit

(4 Instructions)

SRs

Instruction MMU

Branch Processing

Instruction Unit

i Cache

32-Kbyte

Tags

IBAT

Array

(Shadow)

128-Entry

BHT

Unit

BTIC

Data MMU

ITLB

CTRLR

(512 Entry)

(64 Entry)

32-Kbyte

SRs

(Original)

EA

D Cache

Tags

Array

DBAT

DTLB

128-Entry

PA

64-Bit (2 Instructions)

Dispatch Unit

Station

Station

Reservation

Reservation

Buffers

FPR File

6 Rename

Reservation

Station (2 Entry)

Load/Store Unit

Buffers

GPR File

6 Rename

Station

Reservation

Station

Reservation

FPSCR

+ x ÷

Floating-

Point Unit

+

Register UnitUnit 1 Unit 2

Integer

FPSCR

Finished Stores

(EA Calculation)

Completed Stores

32-Bit

+

64-Bit

64-Bit

32-Bit

L2CR

L2 Tags

L2 Controller

L2 MissL2 Data

L2 Bus Interface Unit

Queue

Load Fold

Instruction

Reload Queue

Bus Interface Unit

Queue

Data Reload

L2 Castout

Transaction

L1Operations

Instruction

Reload Table

Queue

64-/128-Bit L2 Data Bus

19-Bit L2 Address Bus

(6 Word)

Fetcher

Instruction Queue

Additional Features

• Time Base Counter/

Decrementer

2 Instructions

• Clock Multiplier

• JTAG/COP Interface

• Power Management

32-Bit

Station

Reservation

Buffers

VR File

6 Rename

Station

Reservation

Station

Reservation

+ x ÷

Integer System

128-Bit

128-Bit

VCIU

VSIU VFPU

Unit

Vector Vector ALU

Permute

VSCR

Figure 1. MPC7400 Block Diagram

Table

Data Reload

(8 Entry)

Reorder Buffer

Completion Unit

32-Bit 60x/MAX Address Bus

64-Bit 60x Data Bus/128-Bit MAX Data Bus

Ability to complete up

to two instructions per clock

MPC7400 RISC Microprocessor Hardware Specifications

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Features

1.2 Features

This section summarizes features of the MPC7400’s implementation of the PowerPC architecture. Major
features of the MPC7400 are as follows:

• Branch processing unit
— Four instructions fetched per clock

— One branch processed per cycle (plus resolving 2 speculations)
— Up to 1 speculative stream in execution, 1 additional speculative stream in fetch
— 512-entry branch history table (BHT) for dynamic prediction
— 64-entry , 4-way set associative Branch Target Instruction Cache (BTIC) for eliminating branch

delay slots

• Dispatch unit
— Full hardware detection of dependencies (resolved in the execution units)

— Dispatch two instructions to eight independent units (system, branch, load/store, fixed-point

unit 1, fixed-point unit 2, floating-point, AltiV ec permute, AltiV ec ALU)

— Serialization control (predispatch, postdispatch, execution serialization)

• Decode
— Register file access

— Forwarding control
— Partial instruction decode

• Completion
— 8 entry completion buffer

— Instruction tracking and peak completion of two instructions per cycle
— Completion of instructions in program order while supporting out-of-order instruction

execution, completion serialization and all instruction flow changes

• Fixed-point units (FXUs) that share 32 GPRs for integer operands
— Fixed-point unit 1 (FXU1)—multiply, divide, shift, rotate, arithmetic, logical

— Fixed-point unit 2 (FXU2)—shift, rotate, arithmetic, logical
— Single-cycle arithmetic, shifts, rotates, logical
— Multiply and divide support (multi-cycle)
— Early out multiply

• Three-stage floating-point unit and a 32-entry FPR file
— Support for IEEE-754 standard single and double-precision floating-point arithmetic

— 3 cycle latency, 1 cycle throughput (single or double precision)
— Hardware support for divide
— Hardware support for denormalized numbers
— Time deterministic non-IEEE mode

• System unit
— Executes CR logical instructions and miscellaneous system instructions

— Special register transfer instructions

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Features

• AltiVec Unit
— Full 128-bit data paths
— Two dispatchable units: vector permute unit and vector ALU unit.
— Contains its own 32-entry 128-bit vector register file (VRF) with 6 renames
— The vector ALU unit is further sub-divided into the vector simple integer unit (VSIU), the

vector complex integer unit (VCIU), and the vector floating-point unit (VFPU).

— Fully pipelined

• Load/store unit
— One cycle load or store cache access (byte, half word, word, double-word)

— 2 cycle load latency with 1 cycle throughput
— Effective address generation
— Hits under misses (multiple outstanding misses)
— Single-cycle unaligned access within double word boundary
— Alignment, zero padding, sign extend for integer register file
— Floating-point internal format conversion (alignment, normalization)
— Sequencing for load/store multiples and string operations
— Store gathering
— Executes the cache and TLB instructions
— Big- and little-endian byte addressing supported
— Misaligned little-endian supported
— Supports FXU, FPU, and AltiVec load/store traffic
— Complete support for all 4 architecture AltiVec DST streams

• Level 1 (L1) cache structure
— 32K, 32-byte line, 8-way set associative instruction cache (iL1)

— 32K, 32-byte line, 8-way set associative data cache (dL1)
— Single-cycle cache access
— Pseudo least-recently-used (LRU) replacement
— Data cache supports AltiVec LRU and transient instructions algorithm
— Copy-back or write-through data cache (on a page per page basis)
— Supports all PowerPC memory coherency modes
— Non-blocking instruction and data cache
— Separate copy of data cache tags for efficient snooping
— No snooping of instruction cache except for ICBI instruction

• Level 2 (L2) cache interface
— Internal L2 cache controller and tags; external data SRAMs

— 512K, 1M, and 2Mbyte 2-way set associative L2 cache support
— Copyback or write-through data cache (on a page basis, or for all L2)
— 32 byte (512K), 64 byte (1M), or 128 byte (2M) sectored line size
— Supports pipelined (register-register) synchronous burst SRAMs and pipelined (register-

register) late-write synchronous burst SRAMs
— Core-to-L2 frequency divisors of ÷1, ÷1.5, ÷2, ÷2.5, ÷3, ÷3.5, and ÷4 supported
— 64 bit data bus
— Selectable interface voltages of 1.8, 2.5, and 3.3V.

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5

• Memory management unit
— 128 entry, 2-way set associative instruction TLB

— 128 entry, 2-way set associative data TLB
— Hardware reload for TLBs
— 4 instruction BATs and 4 data BATs
— Virtual memory support for up to 4 exabytes (2
— Real memory support for up to 4 gigabytes (2

52

) of virtual memory

32

) of physical memory

— Snooped and invalidated for TLBI instructions

•Efficient data flow
— All data buses between VRF, load/store unit, dL1, iL1, L2, and the bus are 128-bits wide

— dL1 is fully pipelined to provide 128 bits/cycle to/from the VRF
— L2 is fully pipelined to provide 128 bits per L2 clock cycle to the L1s
— Up to 8 outstanding, out-of-order, cache misses between dL1 and L2/bus
— Up to 7 outstanding, out-of-order transactions on the bus
— Load folding to fold new dL1 misses into older, outstanding load and store misses to the same

line

— Store miss merging for multiple store misses to the same line. Only coherency action taken (i.e.,

address only) for store misses merged to all 32 bytes of a cache line (no data tenure needed).
— 2-entry finished store queue and 4-entry completed store queue between load/store unit and dL1
— Separate additional queues for efficient buffering of outbound data (castouts, write throughs,

etc.) from dL1 and L2

• Bus interface
— New MPX bus extension to 60X processor interface

— Mode-compatible with 60x processor interface
— 32-bit address bus
— 64 bit data bus
— Bus-to-core frequency multipliers of 2x, 2.5x, 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x,

8x supported

— Selectable interface voltages of 1.8 and 3.3V.

• Power management
— Low-power design with thermal requirements very similar to MPC740 and MPC750.

— 1.8 volt processor core
— Selectable interface voltages below 3.3V can reduce power in output buffers
— Three static power saving modes: doze, nap, and sleep
— Dynamic power management

• Testability
— LSSD scan design

— IEEE 1149.1 JTAG interface
— Array built-in self test (ABIST)—factory test only.
— Redundancy on L1 data arrays and L2 tag arrays

• Reliability and serviceability
— Parity checking on 60x and L2 cache buses

Features

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General Parameters

1.3 General Parameters

The following list provides a summary of the general parameters of the MPC7400:

Technology 0.20 µm CMOS, six-layer metal
Die size 7.86 mm x 10.58 mm (83 mm

2

)
Transistor count 10.5 million
Logic design Fully-static
Packages Surface mount 360 ceramic ball grid array (CBGA)
Core power supply: 1.8V ± 100 mV dc (nominal; see Table 3 for recommended operating

conditions)

I/O power supply 1.8V ± 100 mV dc or

2.5V ± 100 mV dc or

3.3V ± 5% (input thresholds are configuration pin selectable)

1.4 Electrical and Thermal Characteristics

This section provides the AC and DC electrical specifications and thermal characteristics for the MPC7400.

1.4.1 DC Electrical Characteristics

The tables in this section describe the MPC7400 DC electrical characteristics. T able 1 provides the absolute
maximum ratings.

Table 1. Absolute Maximum Ratings

Characteristic Symbol Maximum Value Unit Note

Core supply voltage Vdd –0.3 to 2.1 V 4
PLL supply voltage AVdd –0.3 to 2.1 V 4
L2 DLL supply voltage L2AVdd –0.3 to 2.1 V 4
Processor bus supply voltage OVdd –0.3 to 3.465 V 3
L2 bus supply voltage L2OVdd –0.3 to 3.465 V 3
Input voltage Processor bus V

L2 Bus V
JTAG Signals V

Storage temperature range T

Notes:

1. Functional and tested operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause
permanent damage to the device.

2. Caution: Vin must not exceed OVdd or L2OVdd by more than 0.3V at any time including during power-on reset.

3. Caution: L2OVdd/OVdd must not exceed Vdd/AVdd/L2AVdd by more than 2.0V at any time including during power-on
reset.

in

in

in

stg

1

–0.3 to OVdd + 0.3V V 2,5
–0.3 to L2OVdd + 0.3V V 2,5
–0.3 to 3.6 V

–55 to 150 °C

MPC7400 RISC Microprocessor Hardware Specifications

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7

Electrical and Thermal Characteristics

4. Caution: Vdd/AVdd/L2AVdd must not exceed L2OVdd/OVdd by more than 0.4V at any time including during power-on
reset. In addition, operation at nominal Vdd/AVdd/L2AVdd greater than nominal L2OVdd or OVdd in the 1.8V input
threshold select mode can cause erratic operation and AC timing values worse than described in this specification.

may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.

5. V

in

Figure 2 shows the undershoot and overshoot voltage on the MPC7400.

(L2)OVdd + 20%

(L2)OVdd + 5%

(L2)OVdd

V

IH

V

IL

Gnd

Gnd - .3V

Gnd - 0.7V

Not to exceed 10%
of t

SYSCLK

Figure 2. Overshoot/Undershoot Voltage

The MPC7400 provides several I/O voltages to support both compatibility with existing systems and
migration to future systems. The MPC7400 “core” voltage must always be provided at nominal 1.8V (see
Table 3 for actual recommended core voltage). Voltage to the L2 I/Os and processor interface I/Os are
provided through separate sets of supply pins and may be provided at the voltages shown in Table 2. The
input voltage threshold for each bus is selected by sampling the state of the voltage select pins at the
negation of the signal HRESET

. The output voltage will swing from GND to the maximum voltage applied

to the OVdd or L2OVdd power pins.

Table 2. Input Threshold Voltage Setting

BVSEL Signal

0 1.8V 0 1.8 1
HRESET
1 3.3V 1 3.3 1

Notes:

1. Caution: The input threshold selection must agree with the OVdd/L2OVdd voltages supplied.

2. To select the 2.5 volt threshold option, L2VSEL / BVSEL should be tied to HRESET
change state together.

Processor Bus Input

Threshold is Relative to:

2.5V HRESET 2.5 1,2

L2VSEL Signal

L2 Bus Input Threshold is

Relative to:

so that the two signals

Note

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MPC7400 RISC Microprocessor Hardware Specifications

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Electrical and Thermal Characteristics

Table 3 provides the recommended operating conditions for the MPC7400.

Table 3. Recommended Operating Conditions

Characteristic Symbol

Core supply voltage Vdd 1.8v ± 100mv V 1
PLL supply voltage AVdd 1.8v ± 100mv V 1
L2 DLL supply voltage L2AVdd 1.8v ± 100mv V 1
Processor bus supply

voltage

L2 bus supply voltage L2VSEL = 0 L2OVdd 1.8v ± 100mv V 1

Input voltage Processor bus V

Die-junction temperature T

Note:

1. These are the recommended and tested operating conditions. Proper device operation outside of these
conditions is not guaranteed.

2. The extended temperature parts have die-junction temperature of -40 to 105 ˚C.

BVSEL = 0 OVdd 1.8v ± 100mv V 1
BVSEL = HRESET
BVSEL = 1 OVdd 3.3v ± 165mv V 1

L2VSEL = HRESET
L2VSEL = 1 L2OVdd 3.3v ± 165mv V 1

L2 Bus V
JTAG Signals V

OVdd 2.5v ± 100mv V 1

L2OVdd 2.5v ± 100mv V 1

in

in

in

j

Recommended

Value

GND to OVdd V 1
GND to L2OVdd V 1
GND to OVdd V 1
0 to 105 °C 2

Unit Note

Table 4 provides the package thermal characteristics for the MPC7400.

Table 4. Package Thermal Characteristics

Characteristic Symbol Value Rating

CBGA package thermal resistance, junction-to-case thermal resistance (typical)
CBGA package thermal resistance, die junction-to-lead thermal resistance

(typical)

Note: Refer to Section 1.8, “System Design Information,” for more details about thermal management.

θ

JC

θ

JB

0.03 °C/W

3.8 °C/W

The MPC7400 incorporates a thermal management assist unit (T AU) composed of a thermal sensor , digital­to-analog converter, comparator, control logic, and dedicated special-purpose registers (SPRs). See the
MPC7400 RISC Microprocessor User’s Manual for more information on the use of this feature.
Specifications for the thermal sensor portion of the TAU are found in Table 5.

Table 5. Thermal Sensor Specifications

At recommended operating conditions (See Table 3)

Characteristic Min Max Unit Notes

Temperature range 0 127
Comparator settling time 20 — µs 2

°C

1

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Table 5. Thermal Sensor Specifications

At recommended operating conditions (See Table 3)

Characteristic Min Max Unit Notes

Electrical and Thermal Characteristics

Resolution 4 —
Accuracy -12 +12

°C
°C

3

Notes:

1. The temperature is the junction temperature of the die. The thermal assist unit’s raw output does not indicate an absolute
temperature, but it must be interpreted by software to derive the absolute junction temperature. For information about the
use and calibration of the TAU, see Motorola application note, “Programming the Thermal Assist Unit in the MPC750
Microprocessor,” (order #: AN1800/D).

2. The comparator settling time value must be converted into the number of CPU clocks that need to be written into the
THRM3 SPR.

3. Guaranteed by design and characterization.

Table 6 provides the DC electrical characteristics for the MPC7400.

Table 6. DC Electrical Specifications

At recommended operating conditions (See Table 3)

Nominal

Characteristic

Input high voltage (all inputs except
SYSCLK)

Input low voltage (all inputs except
SYSCLK)

SYSCLK input high voltage 1.8 CV

SYSCLK input low voltage 1.8 CV

Input leakage current, V

= L2OVdd/

in

OVdd

Bus

1

Voltage

1.8 V

2.5 V

3.3 V

1.8 V

2.5 V

3.3 V

3.3 CV

3.3 CV
I

in

Symbol Min Max Unit Notes

IH

0.65 *

(L2)OVdd + 0.3 V 2,3

(L2)OVdd

IH

IH

IL

IL

IL

IH

IH

IL

IL

1.7 (L2)OVdd + 0.3 V 2,3

2.0 (L2)OVdd + 0.3 V 2,3

-0.3 0.35 * OVdd V

-0.3 0.2 * (L2)OVdd V

-0.3 0.8 V

1.5 OVdd + 0.3 V 2

2.4 OVdd + 0.3 V 2

-0.3 0.2 V

-0.3 0.4 V
— 10 µA 2,3

Hi-Z (off-state) leakage current, V
L2OVdd/OVdd

Output high voltage, I

10

= -6 mA 1.8 V

OH

MPC7400 RISC Microprocessor Hardware Specifications

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=

in

2.5 V

3.3 V

I

TSI

OH

OH

OH

— 10 µA 2,3,5

(L2)OVdd–0.45 — V

1.7 — V

2.4 — V

Electrical and Thermal Characteristics

Table 6. DC Electrical Specifications (Continued)

At recommended operating conditions (See Table 3)

Nominal

Characteristic

Output low voltage, I

Capacitance, V

=

in

6 mA 1.8 V

=

OL

0 V, f = 1 MHz C

Notes:

1. Nominal voltages; See Table 3 for recommended operating conditions.

2. For processor bus signals, the reference is OVdd

3. Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK) and IEEE 1149.1 boundary scan (JTAG) signals.

Bus

Voltage

2.5 V

3.3 V

Symbol Min Max Unit Notes

1

OL —

OL —

OL —

in

— 7.5 pF 3,4

while L2OVdd is the reference for the L2 bus signals.

0.45 V

0.4 V

0.4 V

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Electrical and Thermal Characteristics

4. Capacitance is periodically sampled rather than 100% tested.

5. The leakage is measured for nominal OVdd and Vdd, or both OVdd and Vdd must vary in the same direction (for example,
both OVdd and Vdd vary by either +5% or -5%).

Table 7 provides the power consumption for the MPC7400.

Table 7. Power Consumption for MPC7400

Processor (CPU) Frequency

Unit Notes

350 MHz 400 MHz

Full-On Mode

Typical

Maximum

Doze Mode

Maximum 4.4 5.0 W 1, 2

Nap Mode

Maximum 1.75 2.0 W 1, 2

Sleep Mode

Maximum 1.75 2.0 W 1, 2

Sleep Mode—PLL and DLL Disabled

Typical 600 600 mW 1, 3
Maximum 1.0 1.0 W 1, 2

Notes:

1. These values apply for all valid processor bus and L2 bus ratios. The values do not include
I/O Supply Power (OVdd and L2OVdd) or PLL/DLL supply power (AVdd and
L2AVdd). OVdd and L2OVdd power is system dependent, but is typically <10% of Vdd
power. Worst case power consumption for AVdd = 15 mw and L2AVdd = 15 mW.

2. Maximum power is measured at Vdd = 1.9V while running an entirely cache-resident,
contrived sequence of instructions which keep the execution units, including AltiVec,
maximally busy.

3. Typical power is an average value measured at Vdd = AVdd = L2AVdd = 1.8V, OVdd =
L2OVdd = 3.3V in a system while running a codec application that is AltiVec intensive.

4. These values include the use of AltiVec. Without AltiVec operation, estimate a 25%
decrease.

4.6 5.3 W 1, 3

9.9 11.3 W 1, 2, 4

1.4.2 AC Electrical Characteristics

This section provides the AC electrical characteristics for the MPC7400. After fabrication, functional parts
are sorted by maximum processor core frequency as shown in Section 1.4.2.1, “Clock AC Specifications,”
and tested for conformance to the AC specifications for that frequency. The processor core frequency is
determined by the bus (SYSCLK) frequency and the settings of the PLL_CFG[0–3] signals. Parts are sold
by maximum processor core frequency; see Section 1.10, “Ordering Information.”

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Electrical and Thermal Characteristics

1.4.2.1 Clock AC Specifications

Table 8 provides the clock AC timing specifications as defined in Figure 3.

Table 8. Clock AC Timing Specifications

At recommended operating conditions (See Table 3)

Maximum Processor Core

Frequency

Characteristic Symbol

350 MHz 400 MHz

Min Max Min Max

Processor frequency f
VCO frequency f
SYSCLK frequency f
SYSCLK cycle time t
SYSCLK rise and fall time t

SYSCLK duty cycle

core

VCO

SYSCLK

SYSCLK

&

KR

&

t

KR

t

KHKL

t

KF

t

KF

/t

SYSCLK

measured at OVdd/2
SYSCLK jitter — ±150 — ±150 ps 5

300 350 300 400 MHz 1
600 700 600 800 MHz 1
25 100 25 100 MHz 1
10 40 7.5 40 ns

— 1.0 — 1.0 ns 2
— 0.5 — 0.5 ns 3

40 60 40 60 % 4

Unit Notes

Internal PLL relock time — 100 — 100

µ

s6

Notes:

1. Caution: The SYSCLK frequency and PLL_CFG[0–3] settings must be chosen such that the
resulting SYSCLK (bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not
exceed their respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0–
3] signal description in Section 1.8.1, “PLL Configuration,” for valid PLL_CFG[0–3] settings

2. Rise and fall times for the SYSCLK input measured from 0.4V to 2.4V when OVdd = 3.3V
nominal.

3. Rise and fall times for the SYSCLK input measured from 0.4V to 1.4V when OVdd = 1.8V
nominal.

4. Timing is guaranteed by design and characterization.

5. This represents total input jitter—short term and long term combined—and is guaranteed by
design.

6. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum
amount of time required for PLL lock after a stable Vdd and SYSCLK are reached during the
power-on reset sequence. This specification also applies when the PLL has been disabled and
subsequently re-enabled during sleep mode. Also note that HRESET

must be held asserted for a

minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.

MPC7400 RISC Microprocessor Hardware Specifications

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Electrical and Thermal Characteristics

Figure 3 provides the SYSCLK input timing diagram.

CV

SYSCLK VMVMVM

t

KHKL

t

SYSCLK

CV

IL

IH

t

KR

t

KF

VM = Midpoint Voltage (OVDD/2)

Figure 3. SYSCLK Input Timing Diagram

1.4.2.2 Processor Bus AC Specifications

Table 9 provides the processor bus AC timing specifications for the MPC7400 as defined in Figure 4 and
Figure 5. Timing specifications for the L2 bus are provided in Section 1.4.2.3, “L2 Clock AC
Specifications.”y

Table 9. Processor Bus AC Timing Specifications

1

At Vdd=AVdd=1.8V±100mV; 0 ≤ Tj ≤ 105°C, OVdd = 3.3V±165mV or OVdd = 2.5V±100mV or OVdd=1.8V±100mV

350, 400 MHz

Unit Notes

Parameter Symbol

2

Min Max
Mode select input setup to HRESET
HRESET

to mode select input hold t

Setup Times:

Input Hold Times:

Valid Times:

Address/Transfer Attribute

Transfer Start (TS

Data/Data Parity

TRY/SHD0/SHD1

AR

All Other Inputs

Address/Transfer Attribute

Transfer Start (TS

Data/Data Parity

TRY/SHD0/SHD1

AR

All Other Inputs

Address/Transfer Attribute

, ABB, DBB

TS

Data

Data Parity

TRY/SHD0/SHD1

AR

All Other Outputs

t

MVRH

MXRH

t

AVKH

t

)

)

TSVKH

t

DVKH

t

ARVKH

t

IVKH

t

AXKH

t

TSXKH

t

DXKH

t

ARXKH

t

IXKH

t

KHAV

t

KHTSV

t

KHDV

t

KHDPV

t

KHARV

t

KHOV

8—t

sysclk

3,4,5,6

0 — ns 2,3,5

ns

1.6

1.6

1.6

1.6

1.6

—
—
—
—
—

7
—
8
—
9

ns
0
0
0
0
0

—
—
—
—
—

7
—
8
—
9

ns
—
—
—
—
—
—

3.2

3.4

3.5

3.5

2.5

3.2

7
—
8
8
—
10

14

MPC7400 RISC Microprocessor Hardware Specifications

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE