MOTOROLA MPC5200, MPC5200D Technical data

查询MPC5200BV400供应商

MPC5200/D Rev. 2, 5/2004

MPC5200 Hardware Specifications

Freescale Semiconductor, Inc.

Top ic Pa ge

1 Overview ......................................1

2 Features .......................................1

3 Electrical and Thermal

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Characteristics..............................5

4 Package Description ..................60

5 System Design Information ........69

6 Ordering Information ..................74

7 Document Revision History ........75

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NOTE:

The information in this document is subject to change. For the latest data on the MPC5200, visit www.mobilegt.com and proceed to the MPC5200 Product Summary Page.

1 Overview

The MPC5200 integrates a high performance MPC603e series G2_LE core with a rich set of peripheral functions focused on communications and systems integration. The G2_LE core design is based on the PowerPC MPC5200 incorporates an innovative BestComm I/O subsystem, which isolates routine maintenance of peripheral functions from the embedded G2_LE core. The MPC5200 contains a SDRAM/ DDR Memory Controller, a flexible External Bus Interface, PCI Controller, USB, ATA, Ethernet, six Programmable Serial Controllers (PSC), I

C, SPI, CAN, J1850, Timers, and GPIOs.

core architecture.

2Features

Key features are shown below.

• MPC603e series G2_LE core

— Superscalar architecture

— 760 MIPS at 400 MHz (-40 to +85 — 16 k Instruction cache, 16 k Data cache — Double precision FPU — Instruction and Data MMU — Standard and Critical interrupt capability

• SDRAM / DDR Memory Interface

— up to 132-MHz operation — SDRAM and DDR SDRAM support — 256-MByte addressing range per CS, two CS available — 32-bit data bus — Built-in initialization and refresh

• Flexible multi-function External Bus Interface

— Supports interfacing to ROM/Flash/SRAM memories or other memory

mapped devices

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Features

— 8 programmable Chip Selects — Non multiplexed data access using 8/16/32 bit databus with up to 26-bit address — Short or Long Burst capable — Multiplexed data access using 8/16/32 bit databus with up to 25-bit address

• Peripheral Component Interconnect (PCI) Controller

— Version 2.2 PCI compatibility — PCI initiator and target operation — 32-bit PCI Address/Data bus — 33- and 66-MHz operation — PCI arbitration function

• ATA Controller

— Version 4 ATA compatible external interface—IDE Disk Drive connectivity

• BestComm DMA subsystem

— Intelligent virtual DMA Controller — Dedicated DMA channels to control peripheral reception and transmission — Local memory (SRAM 16 kBytes)

• 6 Programmable Serial Controllers (PSC), configurable for the following:

— UART or RS232 interface — CODEC interface for Soft Modem, Master/Slave CODEC Mode, I — Full duplex SPI mode — IrDA mode from 2400 bps to 4 Mbps

• Fast Ethernet Controller (FEC)

— Supports 100Mbps IEEE 802.3 MII, 10 Mbps IEEE 802.3 MII, 10 Mbps 7-wire interface

• Universal Serial Bus Controller (USB)

— USB Revision 1.1 Host

— Open Host Controller Interface (OHCI)

— Integrated USB Hub, with two ports.

• Two Inter-Integrated Circuit Interfaces (I

• Serial Peripheral Interface (SPI)

• Dual CAN 2.0 A /B Controller (MSCAN)

— Motorola Scalable Controller Area Network (MSCAN) architecture — Implementation of version 2.0A/ B CAN protocol — Standard and extended data frames

• J1850 Byte Data Link Controller (BDLC)

— J1850 Class B data communication network interface compatible and ISO compatible for low

speed (<125 kbps) serial data communications in automotive applications. — Supports 4X mode, 41.6 kbps — In-frame response (IFR) types 0, 1, 2, and 3 supported

S and AC97

2 MPC5200 Hardware Specifications M O T O R O L A

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• Systems level features

— Interrupt Controller supports four external interrupt request lines and 47 internal interrupt

sources

— GPIO/Timer functions

– Up to 56 total GPIO pins (depending on functional multiplexing selections ) that support a

variety of interrupt /WakeUp capabilities.

– Eight GPIO pins with timer capability supporting input capture, output compare, and pulse

width modulation (PWM) functions

— Real-time Clock with one-second resolution — Systems Protection ( watch dog timer, bus monitor ) — Individual control of functional block clock sources — Power management: Nap, Doze, Sleep, Deep Sleep modes — Support of WakeUp from low power modes by different sources (GPIO, RTC, CAN)

• Test/ Debug features

— JTAG (IEEE 1149.1 test access port )

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— Common On-chip Processor (COP ) debug port

• On-board PLL and clock generation

Features

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Figure 1 shows a simplified MPC5200 block diagram.

MOTOROLA MPC5200 Hardware Specifications 3

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Features

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Bus

Local

MSCAN

J1850

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SDRAM / DDR

Systems Interface Unit (SIU )

Real-Time Clock

SDRAM / DDR

Memory Controller

USB

SPI

System Functions

Interrupt Controller

GPIO/Timers

Local Plus Controller

PCI Bus Controller

BestComm DMA

SRAM 16K

ATA Host Controller

I2C

Ethernet

PSC

CommBus

603

G2_LE Core

Figure 1 Simplified Block Diagram—MPC5200

4 MPC5200 Hardware Specifications M O T O R O L A

Interface

JTAG / COP

Generation

Reset / Clock

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Electrical and Thermal Characteristics

3 Electrical and Thermal Characteristics

3.1 DC Electrical Characteristics

3.1.1 Absolute Maximum Ratings

The tables in this section describe the MPC5200 DC Electrical characteristics. Table 1 gives the absolute maximum ratings.

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Table 1 Absolute Maximum Ratings

Characteristic Symbol Min Max Unit SpecID

Supply voltage - G2_LE core and peripheral logic VDD_CORE –0.3 1.8 V D1.1

Supply voltage - I/O buffers VDD_IO,

VDD_MEM_IO

Supply voltage - System APLL SYS_PLL_AVDD –0.3 2.1 V D1.3

Supply voltage - G2_LE APLL CORE_PLL_AVDD –0.3 2.1 V D1.4

Input voltage (VDD_IO) Vin –0.3 VDD_IO + 0.3 V D1.5

Input voltage (VDD_MEM_IO) Vin –0.3 VDD_MEM_IO

Input voltage overshoot Vinos – 1.0 V D1.7

Input voltage undershoot Vinus – 1.0 V D1.8

Storage temperature range Tstg –55 150

1 Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses

beyond those listed may affect device reliability or cause permanent damage.

–0.3 3.6 V D1.2

V D1.6

+ 0.3

D1.9

3.1.2 Recommended Operating Conditions

Table 2 gives the recommended operating conditions.

Table 2 Recommended Operating Conditions

Characteristic Symbol

Supply voltage - G2_LE core and peripheral logic

Supply voltage - standard I/O buffers VDD_IO 3.0 3.6 V D2.2

Supply voltage - memory I/ O buffers (SDR)

Supply voltage - memory I/O buffers (DDR)

VDD_CORE 1.42 1.58 V D2.1

VDD_MEM_IO

SDR

DDR

Min

3.0 3.6 V D2.3

2.42 2.63 V D2.4

Max

Unit SpecID

Supply voltage - System APLL SYS_PLL_AVDD 1.42 1.58 V D2.5

Supply voltage - G2_LE APLL CORE_PLL_AVDD 1.42 1.58 V D2.6

Input voltage - standard I/O buffers Vin 0 VDD_IO V D2.7

Input voltage - memory I/O buffers (SDR) Vin

Input voltage - memory I/O buffers (DDR) Vin

MOTOROLA MPC5200 Hardware Specifications 5

SDR

DDR

0 VDD_MEM_IO

SDR

DDR

VD2.8

VD2.9

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Electrical and Thermal Characteristics

Table 2 Recommended Operating Conditions (continued)

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Characteristic Symbol

Ambient operating temperature range

Extended ambient operating temperature

range

Die junction operating temperature range Tj -40 +115

Extended die junction operating temperature range

1 These are recommended and tested operating conditions. Proper device operation outside these conditions is not guar-

anteed. 2 Maximum G2_LE core operating frequency is 400 MHz 3 Maximum G2_LE core operating frequency is 264 MHz

Aext

Tjext -40 +125

Min

-40 +85

-40 +105

Max

Unit SpecID

D2.10

D2.11

D2.12

D2.13

3.1.3 DC Electrical Specifications

Table 3 gives the DC Electrical characteristics for the MPC5200 at recommended operating conditions

(see Table 2).

Table 3 DC Electrical Specifications

Characteristic Condition Symbol Min Max Unit SpecID

Input high voltage Input type = TTL

VDD_IO/VDD_MEM_IO

Input high voltage Input type = TTL

VDD_MEM_IO

Input high voltage Input type = PCI

VDD_IO

Input high voltage Input type = SCHMITT

VDD_IO

Input high voltage SYS_XTAL_IN CV

Input high voltage RTC_XTAL_IN CV

Input low voltage Input type = TTL

VDD_IO/VDD_MEM_IO

Input low voltage Input type = TTL

VDD_MEM_IO

Input low voltage Input type = PCI

VDD_IO

SDR

DDR

SDR

DDR

2.0 — V D3.1

1.7 — V D3.2

2.0 — V D3.3

2.0 — V D3.4

2.0 — V D3.5

2.0 — V D3.6

—0.8VD3.7

—0.7VD3.8

—0.8VD3.9

Input low voltage Input type = SCHMITT

VDD_IO

Input low voltage SYS_XTAL_IN CV

Input low voltage RTC_XTAL_IN CV

Input leakage current Vin = 0 or

VDD_IO/VDD_IO_MEM

(depending on input type 1)

SDR

—0.8VD3.10

—0.8VD3.11

—0.8VD3.12

—+10 µAD3.13

6 MPC5200 Hardware Specifications M O T O R O L A

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Electrical and Thermal Characteristics

Table 3 DC Electrical Specifications (continued)

Characteristic Condition Symbol Min Max Unit SpecID

Input leakage current SYS_XTAL_IN

Vin = 0 or VDD_IO

Input leakage current RTC_XTAL_IN

Vin = 0 or VDD_IO

Input current, pullup resistor

Input current, pullup resistor - memory I/O buffers

Input current, pulldown resistor

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Output high voltage

Output low voltage

DC Injection Current Per

Capacitance Vin = 0V, f = 1 MHz C

1 Leakage current is measured with output drivers disabled and pull-up/pull-downs inactive. 2 See Table 4 for the typical drive capability of a specific signal pin based on the type of output driver associated with that

pin as listed in Table 51.

3 All injection current is transferred to VDD_IO/VDD_IO_MEM. An external load is required to dissipate this current to main-

tain the power supply within the specified voltage range. Total injection current for all digital input-only and all digital input/output pins must not exceed 10 mA. Exceeding this limit can cause disruption of normal operation.

IOH is driver dependent

VDD_IO, VDD_IO_MEM

IOH is driver dependent

IOL is driver dependent

VDD_IO, VDD_IO_MEM

IOL is driver dependent

PULLUP VDD_IO

Vin = 0

PULLUP_MEM

VDD_IO_MEM

Vin = 0

PULLDOWN

VDD_IO

Vin = VDD_IO

VDD_IO_MEM

SDR

DDR

SDR

DDR

INpu

INpd

OHDDR

OLDDR

—+10 µAD3.14

—+10 µAD3.15

40 109 µAD3.16

41 111 µAD3.17

36 106 µAD3.18

2.4 — V D3.19

1.7 — V D3.20

—0.4VD3.21

—0.4VD3.22

-1.0 1.0 mA D3.23

—15pFD3.24

Frees

Table 4 Drive Capability of MPC5200 Output Pins

Driver Type Supply Voltage

DRV4 VDD_IO = 3.3V 4 4 mA D3.25

DRV8 VDD_IO = 3.3V 8 8 mA D3.26

DRV8_OD VDD_IO = 3.3V - 8 mA D3.27

DRV16_MEM VDD_IO_MEM = 3.3V 16 16 mA D3.28

DRV16_MEM VDD_IO_MEM = 2.5V 16 16 mA D3.29

PCI VDD_IO = 3.3V 16 16 mA D3.30

MOTOROLA MPC5200 Hardware Specifications 7

Unit SpecID

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Electrical and Thermal Characteristics

3.1.4 Electrostatic Discharge

— CAUTION —

This device contains circuitry that protects against damage due to high-static voltage or electrical fields. However, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages. Operational reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (i.e., either GND or V

Sym Rating Min Max Unit SpecID

). Table 7 gives package thermal characteristics for this device.

Table 5 ESD and Latch-Up Protection Characteristics

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3.1.5 Power Dissipation

Power dissipation of the MPC5200 is caused by 3 different components: the dissipation of the internal or core digital logic (supplied by VDD_CORE), the dissipation of the analog circuitry (supplied by SYS_PLL_AVDD and CORE_PLL_AVDD) and the dissipation of the IO logic (supplied by VDD_IO_MEM and VDD_IO). Table 6 details typical measured core and analog power dissipation figures for a range of operating modes. However, the dissipation due to the switching of the IO pins can not be given in general, but must be calculated by the user for each application case using the following formula

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Human Body Model (HBM)—JEDEC JESD22-A114-B 2000 — V D4.1

HBM

Machine Model (MM) —JEDEC JESD22-A115 200 — V D4.2

Charge Device Model (CDM)— JEDEC JESD22-C101 500 — V D4.3

CDM

Latch-up Current at TA=85oC

LAT

positive negative

Latch-up Current at TA=27oC

LAT

positive negative

IOint

∑

+ C VDD_IO

+100

-100

+200

-200

f×××=

—mA

D4.4

D4.5

Frees

where N is the number of output pins switching in a group M, C is the capacitance per pin, VDD_IO is the IO voltage swing, f is the switching frequency and PIOint is the power consumed by the unloaded IO stage. The total power consumption of the MPC5200 processor

total

must not exceed the value, which would cause the maximum junction temperature to be exceeded.

8 MPC5200 Hardware Specifications M O T O R O L A

++=

corePanalogPIO

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Electrical and Thermal Characteristics

Table 6 Power Dissipation

Core Power Supply (VDD_CORE)

SYS_XTAL/XLB/PCI/IPG/CORE (MHz)

Typ Typ

SpecID

Unit Notes33/66/33/33/264 33/132/66/132/396

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Operational 727.5 1080 mW

Doze — 600 mW

Nap — 225 mW

Sleep — 225 mW

Deep-Sleep 52.5 52.5 mW

PLL Power Supplies (SYS_PLL_AVDD, CORE_PLL_AVDD)

Mode Typ Unit Notes

Typical 2 mW

Unloaded I/O Power Supplies (VDD_IO, VDD_MEM_IO

Mode Typ Unit Notes

Typical 33 mW

1 Typical core power is measured at VDD_CORE = 1.5 V, Tj = 25 C 2 Operational power is measured while running an entirely cache-resident program with floating-point multiplication

instructions in parallel with a continuous PCI transaction via BestComm.

3 Doze power is measured with the G2_LE core in Doze mode, the system oscillator, System PLL and Core PLL are

active, all other system modules are inactive

4 Nap power is measured with the G2_LE core in Nap mode, the stem oscillator, System PLL and Core PLL are ac-

tive, all other system modules are inactive

5 Sleep power is measured with the G2_LE core in Sleep mode, the stem oscillator, System PLL and Core PLL are

active, all other system modules are inactive

6 Deep-Sleep power is measured with the G2_LE core in Sleep mode, the stem oscillator, System PLL, Core PLL

and all other system modules are inactive 7 Typical PLL power is measured at SYS_PLL_AVDD = CORE_PLL_AVDD = 1.5 V, Tj = 25 C 8 IO power figures given in the table represent the worst case scenario. For the mem_io rail connected to 2.5V the

IO power is expected to be lower and bounded by the worst case with VDD_MEM_IO connected to 3.3V. 9 Unloaded typical I/O power is measured in Deep-Sleep mode at VDD_IO = VDD_MEM_IO

)

1, 2

1, 3

1, 4

1, 5

1, 6

= 3.3 V, Tj = 25 C

SDR

D5.1

D5.2

D5.3

D5.4

D5.5

D5.6

D5.7

MOTOROLA MPC5200 Hardware Specifications 9

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Electrical and Thermal Characteristics

3.1.6 Thermal Characteristics

Table 7 Thermal Resistance Data

Rating Value Unit Notes SpecID

Junction to Ambient Natural Convection

Junction to Ambient (@200 ft/min)

Junction to Board R

Junction to Case R

Junction to Package Top Natural Convection Ψ

1 Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site

(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board

thermal resistance. 2 Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. 3 Per JEDEC JESD51-6 with the board horizontal. 4 Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is mea-

sured on the top surface of the board near the package. 5 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1). 6 Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is

written as Psi-JT.

Single layer board (1s)

Four layer board (2s2p) R

Single layer board (1s)

Four layer board (2s2p)

θJA

θJMA

θJB θJC

30 °C/W 1,

22 °C/W1,

24 °C/W1,

19 °C/W1,

14 °C/W

8°C/W

2°C/W

3.1.6.1 Heat Dissipation

An estimation of the chip-junction temperature, TJ, can be obtained from the following equation:

where:

TJ=TA+(R

= ambient temperature for the package ( ºC)

= junction to ambient thermal resistance (º C/W )

θJA

= power dissipation in package (W)

θJA

× P

) Eqn. 1

D6.1

D6.2

D6.3

D6.4

D6.5

D6.6

D6.7

The junction to ambient thermal resistance is an industry standard value, which provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single layer board, and the value obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which value is correct depends on the power dissipated by other components on the board. The value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated.

Historically, the thermal resistance has frequently been expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance:

10 MPC5200 Hardware Specifications M O T O R O L A

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Electrical and Thermal Characteristics

where:

= junction to ambient thermal resistance ( ºC/ W)

θJA

= junction to case thermal resistance (ºC/ W)

θJC

= case to ambient thermal resistance (ºC/ W)

θCA

is device related and cannot be influenced by the user. The user controls the thermal environment to

θJC

change the case to ambient thermal resistance, R around the device, add a heat sink, change the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This description is most useful for ceramic packages with heat sinks where some 90% of the heat flow is through the case to the heat sink to ambient. For most packages, a better model is required.

A more accurate thermal model can be constructed from the junction to board thermal resistance and the junction to case thermal resistance

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used or where a substantial amount of heat is dissipated from the top of the package. The junction to board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. This model can be used for either hand estimations or for a computational fluid dynamics (CFD) thermal model.

To determine the junction temperature of the device in the application after prototypes are available, the

Thermal Characterization Parameter (Ψ

measurement of the temperature at the top center of the package case using the following equation:

1-3

. The junction to case covers the situation where a heat sink will be

θJA

) can be used to determine the junction temperature with a

θJC+RθCA

. For instance, the user can change the air flow

θCA

Eqn. 2

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TJ=T

where:

= thermocouple temperature on top of package (ºC)

= thermal characterization parameter ( ºC/ W)

= power dissipation in package ( W)

The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned, so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over approximately one mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire.

+(ΨJT × P

) Eqn. 3

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Electrical and Thermal Characteristics

3.2 Oscillator and PLL Electrical Characteristics

The MPC5200 System requires a system-level clock input SYS_XTAL. This clock input may be driven directly from an external oscillator or with a crystal using the internal oscillator.

There is a separate oscillator for the independent Real-Time Clock (RTC) system.

The MPC5200 clock generation uses two phase locked loop (PLL) blocks.

• The system PLL (SYS_PLL) takes an external reference frequency and generates the internal system clock. The system clock frequency is determined by the external reference frequency and the settings of the SYS_PLL configuration.

• The G2_LE core PLL (CORE_PLL) generates a master clock for all of the CPU circuitry. The G2_LE core clock frequency is determined by the system clock frequency and the settings of the CORE_PLL configuration.

3.2.1 System Oscillator Electrical Characteristics

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Table 8 System Oscillator Electrical Characteristics

Characteristic Symbol Notes Min Typical Max Unit SpecID

SYS_XTAL frequency f

Oscillator start-up time t

sys_xtal

up_osc

15.6 33.3 35.0 MHz O1.1

3.2.2 RTC Oscillator Electrical Characteristics

Table 9 RTC Oscillator Electrical Characteristics

Characteristic Symbol Notes Min Typical Max Unit SpecID

RTC_XTAL frequency f

rtc_xtal

— — 100 µsO1.2

— 32.768 — kHz O2.1

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3.2.3 System PLL Electrical Characteristics

Table 10 System PLL Specifications

Characteristic Symbol Notes Min Typical Max Unit SpecID

Electrical and Thermal Characteristics

SYS_XTAL frequency f

SYS_XTAL cycle time T

SYS_XTAL clock input jitter t

System VCO frequency f

System PLL relock time t

1 The SYS_XTAL frequency and PLL Configuration bits must be chosen such that the resulting system frequency, CPU

(core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequen-

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cies.

2 This represents total input jitter - short term and long term combined - and is guaranteed by design. Two different types

of jitter can exist on the input to core_sysclk, systemic and true random jitter. True random jitter is rejected, but the PLL. Systemic jitter will be passed into and through the PLL to the internal clock circuitry, directly reducing the operating frequency.

3 Relock time is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for

the PLL lock after a stable Vdd and core_sysclk are reached during the power-on reset sequence. This specification also applies when the PLL has been disabled and subsequently re-enabled during sleep modes.

sys_xtal

jitter

VCOsys

lock

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15.6 33.3 35.0 MHz O3.1

66.6 30.0 28.5 ns O3.2

— — 150 ps O3.3

250 533 800 MHz O3.4

——100µsO3.5

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Electrical and Thermal Characteristics

3.2.4 G2_LE Core PLL Electrical Characteristics

The internal clocking of the G2_LE core is generated from and synchronized to the system clock by means of a voltage-controlled core PLL.

Table 11 G2_LE PLL Specifications

Characteristic Symbol Notes Min Typical Max Unit SpecID

G2_LE frequency f

G2_LE cycle time t

G2_LE VCO frequency f

G2_LE input clock frequency f

G2_LE input clock cycle time t

G2_LE input clock jitter t

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G2_LE PLL relock time t

1 The SYSCLK frequency and G2_LE PLL Configuration bits must be chosen such that the resulting system frequencies,

CPU (core) frequency, and G2_LE PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies.

2 This represents total input jitter - short term and long term combined - and is guaranteed by design. Two different types

3 Relock time is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for

core

VCOcore

SYSCLK

jitter

lock

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50 — 550 MHz O4.1

2.85 — 40.0 ns O4.2

400 — 1200 MHz O4.3

25 — 367 MHz O4.4

2.73 — 50.0 ns O4.5

— — 150 ps O4.6

— — 100 µsO4.7

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14 MPC5200 Hardware Specifications M O T O R O L A

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Electrical and Thermal Characteristics

3.3 AC Electrical Characteristics

Hyperlinks to the indicated timing specification sections are provided below.

• AC Operating Frequency Data • USB

• Clock AC Specifications • SPI

• Resets • MSCAN

• External Interrupts

• SDRAM • J1850

•PCI •PSC

• Local Plus Bus • GPIOs and Timers

• ATA • IEEE 1149.1 (JTAG) AC Specifications

• Ethernet

•I

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AC Test Timing Conditions:

Unless otherwise noted, all test conditions are as follows:

• TA = -40 to 85

• Tj = -40 to 115

• VDD_CORE = 1.42 to 1.58 V VDD_IO = 3.0 to 3.6 V

• Input conditions: All Inputs: tr, tf <= TBD

• Output Loading: All Outputs: 50 pF

3.3.1 AC Operating Frequency Data

Table 12 provides the operating frequency information for the MPC5200.

Table 12 Clock Frequencies

Min Max Units SpecID

1 G2_LE Processor Core — 400 MHz A1.1

2 SDRAM Clock — 133 MHz A1.2

3 XL Bus Clock — 133 MHz A1.3

4 IP Bus Clock — 133 MHz A1.4

5 PCI / Local Plus Bus Clock — 66 MHz A1.5

6 PLL Input Range 15.6 35 MHz A1.6

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Electrical and Thermal Characteristics

3.3.2 Clock AC Specifications

CYCLE

FAL L

SYSCLK

DUTY

RISE

Figure 2 Timing Diagram—SYS_XTAL_IN

Table 13 SYS_XTAL_IN Timing

Sym Description Min Max Units SpecID

CYCLE

SYS_XTAL_IN cycle time.

28.6 64.1 ns A2.1

nc...

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Frees

RISE

FALL

DUTY

1 CAUTION—The SYS_XTAL_IN frequency and system PLL_CFG[0-6] settings must be chosen such that the resulting

2 SYS_XTAL_IN duty cycle is measured at VM.

SYS_XTAL_IN rise time. — 5.0 ns A2.2

SYS_XTAL_IN fall time. — 5.0 ns A2.3

SYS_XTAL_IN duty cycle (measured at VM). 2

SYS_XTAL_IN input voltage high 2.0 — V A2.5

SYS_XTAL_IN input voltage low — 0.8 V A2.6

system frequencies do not exceed their respective maximum or minimum operating frequencies. See the MPC5200 User Manual [1].

40.0 60.0 % A2.4

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3.3.3 Resets

The MPC5200 has three reset pins:

Electrical and Thermal Characteristics

• PORESET

• HRESET

• SRESET

These signals are asynchronous I /O signals and can be asserted at any time. The input side uses a Schmitt trigger and requires the same input characteristics as other MPC5200 inputs, as specified in the DC Electrical Specifications section. Table 14 specifies the pulse widths of the Reset inputs.

- Power on Reset

- Hard Reset

- Software Reset

Table 14 Reset Pulse Width

Name Description Min Pulse Width

PORESET

nc...

HRESET

SRESET

Notes:

1. For PORESET wards its minimum pulse width equals the minimum given for HRESET

2. The t

3. For t

4. For t

5. Following the deassertion of PORESET

6. The deassertion of HRESET 4096 clock cycles.

Power On Reset t

Hardware Reset 4 clock cycles — SYS_XTAL_IN A3.2

Software Reset 4 clock cycles — SYS_XTAL_IN A3.3

the value of the minimum pulse width reflects the power on sequence. If PORESET is asserted after-

VDD_stable

lock,

up_osc,

describes the time which is needed to get all power supplies stable.

refer to the Oscillator/PLL section of this specification for further details.

VDD_stable+tup_osc+tlock

, HRESET and SRESET remain low for 4096 reference clock cycles.

for at least the minimum pulse width forces the internal resets to be active for an additional

NOTE:

As long as VDD is not stable the HRESET

Table 15 Reset Rise / Fall Timing

Description Min Max Unit SpecID

cale Semiconductor,

PORESET

HRESET

fall time — 1 ms A3.4

rise time — 1 ms A3.5

fall time — TBD ns A3.6

Max Pulse

Width

— SYS_XTAL_IN A3.1

related to the same reference clock.

Reference Clock SpecID

output is not stable.

Frees

HRESET

SRESET

For additional information, see the MPC5200 User Manual [1].

MOTOROLA MPC5200 Hardware Specifications 1 7

rise time — TBD ns A3.7

fall time — TBD ns A3.8

rise time — TBD ns A3.9

NOTE:

Make sure that the PORESET has no filter to prevent them from getting into the chip.

does not carry any glitches. The MPC5200

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Electrical and Thermal Characteristics

3.3.3.1 Reset Configuration Word

During reset (HRESET and PORESET) the Reset Configuration Word is cached in the related Reset Configuration Word Register with each rising edge of the SYS_XTAL signal. If both resets (HRESET PORESET (see Figure 3).

) are inactive (high), the contents of this register get locked after two further SYS_XTAL cycles

SYS_XTAL

PORESET

HRESET

RST_CFG_WRD

4096 clocks 2 clocks

and

nc...

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Frees

sample

Beware of changing the values on the pins of the reset configuration word after the deassertion of PORESET may change the internal clock ratios and so extend the PLL locking process.

sample

Figure 3 Reset Configuration Word Locking

sample sample

sample

sample sample

NOTE:

. This may cause problems because it

sample

LOCK

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Electrical and Thermal Characteristics

3.3.4 External Interrupts

The MPC5200 provides three different kinds of external interrupts:

• Four IRQ interrupts

• Eight GPIO interrupts with simple interrupt capability (not available in power-down mode)

• Eight WakeUp interrupts (special GPIO pins)

The propagation of these three kinds of interrupts to the core is shown in the following graphic:

nc...

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Frees

IRQ0

8 GPIOs

8 GPIOs GPIO WakeUp

IRQ1

IRQ2

IRQ3

Due to synchronization, prioritization, and mapping of external interrupt sources, the propagation of external interrupts to the core processor is delayed by several IP_CLK clock cycles. The following table specifies the interrupt latencies in IP_CLK cycles. The IP_CLK frequency is programmable in the Clock Distribution Module (see Note Table 16).

Interrupt Type Pin Name Clock Cycles Reference Clock Core Interrupt SpecID

Interrupt Requests IRQ0 10 IP_CLK critical (cint) A4.1

GPIO Std

Notes:

1. PIs = Programmable Inputs

2. Grouper and Encoder functions imply programmability in software

Figure 4 External interrupt scheme

Table 16 External interrupt latencies

IRQ0 10 IP_CLK normal (int) A4.2

IRQ1 10 IP_CLK normal (int) A4.3

cint

int

PIs

Main Interrupt

Controller

Encoder

Grouper Encoder

core_cint

core_int

G2_LE Core

IRQ2 10 IP_CLK normal (int) A4.5

IRQ3 10 IP_CLK normal (int) A4.6

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Electrical and Thermal Characteristics

Table 16 External interrupt latencies (continued)

Interrupt Type Pin Name Clock Cycles Reference Clock Core Interrupt SpecID

Standard GPIO Interrupts GPIO_PSC3_4 12 IP_CLK normal (int) A4.7

GPIO_PSC3_5 12 IP_CLK normal (int) A4.8

GPIO_PSC3_8 12 IP_CLK normal (int) A4.9

GPIO_USB_9 12 IP_CLK normal (int) A4.10

GPIO_ETHI_4 12 IP_CLK normal (int) A4.11

GPIO_ETHI_5 12 IP_CLK normal (int) A4.12

GPIO_ETHI_6 12 IP_CLK normal (int) A4.13

GPIO_ETHI_7 12 IP_CLK normal (int) A4.14

GPIO WakeUp Interrupts GPIO_PSC1_4 12 IP_CLK normal (int) A4.15

nc...

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Frees

GPIO_PSC2_4 12 IP_CLK normal (int) A4.16

GPIO_PSC3_9 12 IP_CLK normal (int) A4.17

GPIO_ETHI_8 12 IP_CLK normal (int) A4.18

GPIO_IRDA_0 12 IP_CLK normal (int) A4.19

DGP_IN0 12 IP_CLK normal (int) A4.20

DGP_IN1 12 IP_CLK normal (int) A4.21

Notes:

1) The frequency of IP_CLK depends on register settings in Clock Distribution Module. See the MPC5200 User Manual [1].

2) The interrupt latency descriptions in the table above are related to non competitive, non masked but enabled external interrupt sources. Take care of interrupt prioritization which may increase the latencies.

Since all external interrupt signals are synchronized into the internal processor bus clock domain, each of these signals has to exceed a minimum pulse width of more than one IP_CLK cycle.

Table 17 Minimum pulse width for external interrupts to be recognized

Name Min Pulse Width Max Pulse Width Reference Clock SpecID

All external interrupts (IRQs, GPIOs) > 1 clock cycle — IP_CLK A4.22

Notes:

1) The frequency of the IP_CLK depends on the register settings in Clock Distribution Module. See the MPC5200 User Manual [1] for further information.

2) If the same interrupt occurs a second time while its interrupt service routine has not cleared the former one, the second interrupt will not be recognized at all.

Besides synchronization, prioritization, and mapping the latency of an external interrupt to the start of its associated interrupt service routine also depends on the following conditions: To get a minimum interrupt service response time, it is recommended to enable the instruction cache and set up the maximum core clock, XL bus, and IP bus frequencies (depending on board design and programming). In addition, it is advisable to execute an interrupt handler, which has been implemented in assembly code.

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Electrical and Thermal Characteristics

3.3.5 SDRAM

3.3.5.4 Memory Interface Timing-Standard SDRAM Read Command

Table 18 Standard SDRAM Memory Read Timing

Sym Description Min Max Units SpecID

nc...

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Frees

mem_clk

valid

hold

data

MBA (Bank Selects)

MEM_CLK period 7.5 — ns A5.1

Control Signals, Address and MBA Valid after rising edge of MEM_CLK

Control Signals, Address and MBA Hold after rising edge of MEM_CLK

DQM valid after rising edge of

valid

MEM_CLK

DQM hold after rising edge of MEM_CLK t

hold

MDQ setup to rising edge of MEM_CLK — 0.3 ns A5.6

setup

MDQ hold after rising edge of MEM_CLK 0.2 — ns A5.7

hold

MEM_CLK

Control Signals

DQM (Data Mask)

MDQ (Data)

MA (Address)

—t

mem_clk

valid

hold

Active NOP READ NOPNOPNOP NOP

valid

hold

Row Column

hold

*0.5 — ns A5.3

—t

*0.25-0.7 — ns A5.5

hold

data

setup

mem_clk

NOP

*0.5+0.4 ns A5.2

*0.25+0.4 ns A5.4

data

hold

NOTE: Control Signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN

Figure 5 Timing Diagram—Standard SDRAM Memory Read Timing

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Electrical and Thermal Characteristics

3.3.5.5 Memory Interface Timing-Standard SDRAM Write Command

In Standard SDRAM, all signals are activated on the Mem_clk from the Memory Controller and captured on the Mem_clk clock at the memory device.

Table 19 Standard SDRAM Write Timing

Sym Description Min Max Units SpecID

nc...

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Frees

mem_clk

valid

hold

valid

hold

data

DQM (Data Mask)

MBA (Bank Selects)

MEM_CLK period 7.5 — ns A5.8

Control Signals, Address and MBA Valid after rising edge of MEM_CLK

Control Signals, Address and MBA Hold after rising edge of MEM_CLK

DQM valid after rising edge of MEM_CLK

DQM hold after rising edge of Mem_clk t

MDQ valid after rising edge of

valid

MEM_CLK

MDQ hold after rising edge of

hold

MEM_CLK

Control Signals

MDQ (Data)

MA (Address)

—t

mem_clk

valid

hold

Active NOP WRITE NOPNOPNOPNOP NOP

valid

data

valid

hold

Row Column

hold

*0.5 — ns A5.10

—t

*0.25-0.7 — ns A5.12

—t

*0.75-0.7 — ns A5.14

hold

data

hold

mem_clk

*0.5+0.4 ns A5.9

*0.25+0.4 ns A5.11

*0.75+0.4 ns A5.13

NOTE: Control Signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN

Figure 6 Timing Diagram—Standard SDRAM Memory Write Timing

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Electrical and Thermal Characteristics

3.3.5.6 Memory Interface Timing-DDR SDRAM Read Command

The SDRAM Memory Controller uses an internally skewed clock for reading DDR memory. The programmable bits in the Reset Configuration Register used to account for unknown board delays are in the CDM module. The internal read clock can be delayed up to 3 ns under worst operating conditions in 32 increments of 95 ps, (1.4 ns in 45 ps increments under best case operating conditions) by programming the CDM Reset Configuration Register tap delay bits. Note: These bits in the CDM Reset Configuration register are not ‘reset configured’ but have a hard coded reset value and are writable during operation.

Table 20 DDR SDRAM Memory Read Timing

Sym Description Min Max Units SpecID

mem_clk

valid

hold

nc...

data

cale Semiconductor,

MDQS (Data Strobe)

MEM_CLK period 7.5 — ns A5.15

Control Signals, Address and MBA valid after rising edge of MEM_CLK

Control Signals, Address and MBA hold after rising edge of MEM_CLK

Setup time skewed by CDM Reset

setup

Config Reg [3:7] = 0b00010

Hold time skewed by CDM Reset Con-

hold

fig Reg [3:7] = 0b00010

MEM_CLK

valid

Control Signals

Active NOP READ NOPNOPNOPNOP NOP

hold

—t

mem_clk

*0.5 — ns A5.17

— 0.4 ns A5.18

2.34 — ns A5.19

mem_clk

*0.5+0.4 ns A5.16

Frees

data

MDQ (Data)

valid

MA (Address)

valid

MBA (Bank Selects)

NOTE: Control Signals signals are composed of RAS, CAS, MEM_WE

Row Column

hold

setup

, MEM_CS, MEM_CS1 and CLK_EN

data

hold

Figure 7 Timing Diagram—DDR SDRAM Memory Read Timing

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