MOTOROLA MPC5200, MPC5200D Technical data

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MPC5200/D Rev. 2, 5/2004

MPC5200 Hardware Specifications

Freescale Semiconductor, Inc.

Top ic Pa ge

1 Overview ......................................1

2 Features .......................................1

3 Electrical and Thermal

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Characteristics..............................5

4 Package Description ..................60

5 System Design Information ........69

6 Ordering Information ..................74

7 Document Revision History ........75

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NOTE:

The information in this document is subject to change. For the latest data on the MPC5200, visit www.mobilegt.com and proceed to the MPC5200 Product Summary Page.

1 Overview

The MPC5200 integrates a high performance MPC603e series G2_LE core with a rich set of peripheral functions focused on communications and systems integration. The G2_LE core design is based on the PowerPC MPC5200 incorporates an innovative BestComm I/O subsystem, which isolates routine maintenance of peripheral functions from the embedded G2_LE core. The MPC5200 contains a SDRAM/ DDR Memory Controller, a flexible External Bus Interface, PCI Controller, USB, ATA, Ethernet, six Programmable Serial Controllers (PSC), I

C, SPI, CAN, J1850, Timers, and GPIOs.

core architecture.

2Features

Key features are shown below.

• MPC603e series G2_LE core

— Superscalar architecture

— 760 MIPS at 400 MHz (-40 to +85 — 16 k Instruction cache, 16 k Data cache — Double precision FPU — Instruction and Data MMU — Standard and Critical interrupt capability

• SDRAM / DDR Memory Interface

— up to 132-MHz operation — SDRAM and DDR SDRAM support — 256-MByte addressing range per CS, two CS available — 32-bit data bus — Built-in initialization and refresh

• Flexible multi-function External Bus Interface

— Supports interfacing to ROM/Flash/SRAM memories or other memory

mapped devices

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Features

— 8 programmable Chip Selects — Non multiplexed data access using 8/16/32 bit databus with up to 26-bit address — Short or Long Burst capable — Multiplexed data access using 8/16/32 bit databus with up to 25-bit address

• Peripheral Component Interconnect (PCI) Controller

— Version 2.2 PCI compatibility — PCI initiator and target operation — 32-bit PCI Address/Data bus — 33- and 66-MHz operation — PCI arbitration function

• ATA Controller

— Version 4 ATA compatible external interface—IDE Disk Drive connectivity

• BestComm DMA subsystem

— Intelligent virtual DMA Controller — Dedicated DMA channels to control peripheral reception and transmission — Local memory (SRAM 16 kBytes)

• 6 Programmable Serial Controllers (PSC), configurable for the following:

— UART or RS232 interface — CODEC interface for Soft Modem, Master/Slave CODEC Mode, I — Full duplex SPI mode — IrDA mode from 2400 bps to 4 Mbps

• Fast Ethernet Controller (FEC)

— Supports 100Mbps IEEE 802.3 MII, 10 Mbps IEEE 802.3 MII, 10 Mbps 7-wire interface

• Universal Serial Bus Controller (USB)

— USB Revision 1.1 Host

— Open Host Controller Interface (OHCI)

— Integrated USB Hub, with two ports.

• Two Inter-Integrated Circuit Interfaces (I

• Serial Peripheral Interface (SPI)

• Dual CAN 2.0 A /B Controller (MSCAN)

— Motorola Scalable Controller Area Network (MSCAN) architecture — Implementation of version 2.0A/ B CAN protocol — Standard and extended data frames

• J1850 Byte Data Link Controller (BDLC)

— J1850 Class B data communication network interface compatible and ISO compatible for low

speed (<125 kbps) serial data communications in automotive applications. — Supports 4X mode, 41.6 kbps — In-frame response (IFR) types 0, 1, 2, and 3 supported

S and AC97

2 MPC5200 Hardware Specifications M O T O R O L A

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• Systems level features

— Interrupt Controller supports four external interrupt request lines and 47 internal interrupt

sources

— GPIO/Timer functions

– Up to 56 total GPIO pins (depending on functional multiplexing selections ) that support a

variety of interrupt /WakeUp capabilities.

– Eight GPIO pins with timer capability supporting input capture, output compare, and pulse

width modulation (PWM) functions

— Real-time Clock with one-second resolution — Systems Protection ( watch dog timer, bus monitor ) — Individual control of functional block clock sources — Power management: Nap, Doze, Sleep, Deep Sleep modes — Support of WakeUp from low power modes by different sources (GPIO, RTC, CAN)

• Test/ Debug features

— JTAG (IEEE 1149.1 test access port )

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— Common On-chip Processor (COP ) debug port

• On-board PLL and clock generation

Features

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Figure 1 shows a simplified MPC5200 block diagram.

MOTOROLA MPC5200 Hardware Specifications 3

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Features

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Bus

Local

MSCAN

J1850

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SDRAM / DDR

Systems Interface Unit (SIU )

Real-Time Clock

SDRAM / DDR

Memory Controller

USB

SPI

System Functions

Interrupt Controller

GPIO/Timers

Local Plus Controller

PCI Bus Controller

BestComm DMA

SRAM 16K

ATA Host Controller

I2C

Ethernet

PSC

CommBus

603

G2_LE Core

Figure 1 Simplified Block Diagram—MPC5200

4 MPC5200 Hardware Specifications M O T O R O L A

Interface

JTAG / COP

Generation

Reset / Clock

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Electrical and Thermal Characteristics

3 Electrical and Thermal Characteristics

3.1 DC Electrical Characteristics

3.1.1 Absolute Maximum Ratings

The tables in this section describe the MPC5200 DC Electrical characteristics. Table 1 gives the absolute maximum ratings.

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Table 1 Absolute Maximum Ratings

Characteristic Symbol Min Max Unit SpecID

Supply voltage - G2_LE core and peripheral logic VDD_CORE –0.3 1.8 V D1.1

Supply voltage - I/O buffers VDD_IO,

VDD_MEM_IO

Supply voltage - System APLL SYS_PLL_AVDD –0.3 2.1 V D1.3

Supply voltage - G2_LE APLL CORE_PLL_AVDD –0.3 2.1 V D1.4

Input voltage (VDD_IO) Vin –0.3 VDD_IO + 0.3 V D1.5

Input voltage (VDD_MEM_IO) Vin –0.3 VDD_MEM_IO

Input voltage overshoot Vinos – 1.0 V D1.7

Input voltage undershoot Vinus – 1.0 V D1.8

Storage temperature range Tstg –55 150

1 Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses

beyond those listed may affect device reliability or cause permanent damage.

–0.3 3.6 V D1.2

V D1.6

+ 0.3

D1.9

3.1.2 Recommended Operating Conditions

Table 2 gives the recommended operating conditions.

Table 2 Recommended Operating Conditions

Characteristic Symbol

Supply voltage - G2_LE core and peripheral logic

Supply voltage - standard I/O buffers VDD_IO 3.0 3.6 V D2.2

Supply voltage - memory I/ O buffers (SDR)

Supply voltage - memory I/O buffers (DDR)

VDD_CORE 1.42 1.58 V D2.1

VDD_MEM_IO

SDR

DDR

Min

3.0 3.6 V D2.3

2.42 2.63 V D2.4

Max

Unit SpecID

Supply voltage - System APLL SYS_PLL_AVDD 1.42 1.58 V D2.5

Supply voltage - G2_LE APLL CORE_PLL_AVDD 1.42 1.58 V D2.6

Input voltage - standard I/O buffers Vin 0 VDD_IO V D2.7

Input voltage - memory I/O buffers (SDR) Vin

Input voltage - memory I/O buffers (DDR) Vin

MOTOROLA MPC5200 Hardware Specifications 5

SDR

DDR

0 VDD_MEM_IO

SDR

DDR

VD2.8

VD2.9

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Electrical and Thermal Characteristics

Table 2 Recommended Operating Conditions (continued)

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Characteristic Symbol

Ambient operating temperature range

Extended ambient operating temperature

range

Die junction operating temperature range Tj -40 +115

Extended die junction operating temperature range

1 These are recommended and tested operating conditions. Proper device operation outside these conditions is not guar-

anteed. 2 Maximum G2_LE core operating frequency is 400 MHz 3 Maximum G2_LE core operating frequency is 264 MHz

Aext

Tjext -40 +125

Min

-40 +85

-40 +105

Max

Unit SpecID

D2.10

D2.11

D2.12

D2.13

3.1.3 DC Electrical Specifications

Table 3 gives the DC Electrical characteristics for the MPC5200 at recommended operating conditions

(see Table 2).

Table 3 DC Electrical Specifications

Characteristic Condition Symbol Min Max Unit SpecID

Input high voltage Input type = TTL

VDD_IO/VDD_MEM_IO

Input high voltage Input type = TTL

VDD_MEM_IO

Input high voltage Input type = PCI

VDD_IO

Input high voltage Input type = SCHMITT

VDD_IO

Input high voltage SYS_XTAL_IN CV

Input high voltage RTC_XTAL_IN CV

Input low voltage Input type = TTL

VDD_IO/VDD_MEM_IO

Input low voltage Input type = TTL

VDD_MEM_IO

Input low voltage Input type = PCI

VDD_IO

SDR

DDR

SDR

DDR

2.0 — V D3.1

1.7 — V D3.2

2.0 — V D3.3

2.0 — V D3.4

2.0 — V D3.5

2.0 — V D3.6

—0.8VD3.7

—0.7VD3.8

—0.8VD3.9

Input low voltage Input type = SCHMITT

VDD_IO

Input low voltage SYS_XTAL_IN CV

Input low voltage RTC_XTAL_IN CV

Input leakage current Vin = 0 or

VDD_IO/VDD_IO_MEM

(depending on input type 1)

SDR

—0.8VD3.10

—0.8VD3.11

—0.8VD3.12

—+10 µAD3.13

6 MPC5200 Hardware Specifications M O T O R O L A

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Electrical and Thermal Characteristics

Table 3 DC Electrical Specifications (continued)

Characteristic Condition Symbol Min Max Unit SpecID

Input leakage current SYS_XTAL_IN

Vin = 0 or VDD_IO

Input leakage current RTC_XTAL_IN

Vin = 0 or VDD_IO

Input current, pullup resistor

Input current, pullup resistor - memory I/O buffers

Input current, pulldown resistor

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Output high voltage

Output low voltage

DC Injection Current Per

Capacitance Vin = 0V, f = 1 MHz C

1 Leakage current is measured with output drivers disabled and pull-up/pull-downs inactive. 2 See Table 4 for the typical drive capability of a specific signal pin based on the type of output driver associated with that

pin as listed in Table 51.

3 All injection current is transferred to VDD_IO/VDD_IO_MEM. An external load is required to dissipate this current to main-

tain the power supply within the specified voltage range. Total injection current for all digital input-only and all digital input/output pins must not exceed 10 mA. Exceeding this limit can cause disruption of normal operation.

IOH is driver dependent

VDD_IO, VDD_IO_MEM

IOH is driver dependent

IOL is driver dependent

VDD_IO, VDD_IO_MEM

IOL is driver dependent

PULLUP VDD_IO

Vin = 0

PULLUP_MEM

VDD_IO_MEM

Vin = 0

PULLDOWN

VDD_IO

Vin = VDD_IO

VDD_IO_MEM

SDR

DDR

SDR

DDR

INpu

INpd

OHDDR

OLDDR

—+10 µAD3.14

—+10 µAD3.15

40 109 µAD3.16

41 111 µAD3.17

36 106 µAD3.18

2.4 — V D3.19

1.7 — V D3.20

—0.4VD3.21

—0.4VD3.22

-1.0 1.0 mA D3.23

—15pFD3.24

Frees

Table 4 Drive Capability of MPC5200 Output Pins

Driver Type Supply Voltage

DRV4 VDD_IO = 3.3V 4 4 mA D3.25

DRV8 VDD_IO = 3.3V 8 8 mA D3.26

DRV8_OD VDD_IO = 3.3V - 8 mA D3.27

DRV16_MEM VDD_IO_MEM = 3.3V 16 16 mA D3.28

DRV16_MEM VDD_IO_MEM = 2.5V 16 16 mA D3.29

PCI VDD_IO = 3.3V 16 16 mA D3.30

MOTOROLA MPC5200 Hardware Specifications 7

Unit SpecID

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Electrical and Thermal Characteristics

3.1.4 Electrostatic Discharge

— CAUTION —

This device contains circuitry that protects against damage due to high-static voltage or electrical fields. However, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages. Operational reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (i.e., either GND or V

Sym Rating Min Max Unit SpecID

). Table 7 gives package thermal characteristics for this device.

Table 5 ESD and Latch-Up Protection Characteristics

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3.1.5 Power Dissipation

Power dissipation of the MPC5200 is caused by 3 different components: the dissipation of the internal or core digital logic (supplied by VDD_CORE), the dissipation of the analog circuitry (supplied by SYS_PLL_AVDD and CORE_PLL_AVDD) and the dissipation of the IO logic (supplied by VDD_IO_MEM and VDD_IO). Table 6 details typical measured core and analog power dissipation figures for a range of operating modes. However, the dissipation due to the switching of the IO pins can not be given in general, but must be calculated by the user for each application case using the following formula

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Human Body Model (HBM)—JEDEC JESD22-A114-B 2000 — V D4.1

HBM

Machine Model (MM) —JEDEC JESD22-A115 200 — V D4.2

Charge Device Model (CDM)— JEDEC JESD22-C101 500 — V D4.3

CDM

Latch-up Current at TA=85oC

LAT

positive negative

Latch-up Current at TA=27oC

LAT

positive negative

IOint

∑

+ C VDD_IO

+100

-100

+200

-200

f×××=

—mA

D4.4

D4.5

Frees

where N is the number of output pins switching in a group M, C is the capacitance per pin, VDD_IO is the IO voltage swing, f is the switching frequency and PIOint is the power consumed by the unloaded IO stage. The total power consumption of the MPC5200 processor

total

must not exceed the value, which would cause the maximum junction temperature to be exceeded.

8 MPC5200 Hardware Specifications M O T O R O L A

++=

corePanalogPIO

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Electrical and Thermal Characteristics

Table 6 Power Dissipation

Core Power Supply (VDD_CORE)

SYS_XTAL/XLB/PCI/IPG/CORE (MHz)

Typ Typ

SpecID

Unit Notes33/66/33/33/264 33/132/66/132/396

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Operational 727.5 1080 mW

Doze — 600 mW

Nap — 225 mW

Sleep — 225 mW

Deep-Sleep 52.5 52.5 mW

PLL Power Supplies (SYS_PLL_AVDD, CORE_PLL_AVDD)

Mode Typ Unit Notes

Typical 2 mW

Unloaded I/O Power Supplies (VDD_IO, VDD_MEM_IO

Mode Typ Unit Notes

Typical 33 mW

1 Typical core power is measured at VDD_CORE = 1.5 V, Tj = 25 C 2 Operational power is measured while running an entirely cache-resident program with floating-point multiplication

instructions in parallel with a continuous PCI transaction via BestComm.

3 Doze power is measured with the G2_LE core in Doze mode, the system oscillator, System PLL and Core PLL are

active, all other system modules are inactive

4 Nap power is measured with the G2_LE core in Nap mode, the stem oscillator, System PLL and Core PLL are ac-

tive, all other system modules are inactive

5 Sleep power is measured with the G2_LE core in Sleep mode, the stem oscillator, System PLL and Core PLL are

active, all other system modules are inactive

6 Deep-Sleep power is measured with the G2_LE core in Sleep mode, the stem oscillator, System PLL, Core PLL

and all other system modules are inactive 7 Typical PLL power is measured at SYS_PLL_AVDD = CORE_PLL_AVDD = 1.5 V, Tj = 25 C 8 IO power figures given in the table represent the worst case scenario. For the mem_io rail connected to 2.5V the

IO power is expected to be lower and bounded by the worst case with VDD_MEM_IO connected to 3.3V. 9 Unloaded typical I/O power is measured in Deep-Sleep mode at VDD_IO = VDD_MEM_IO

)

1, 2

1, 3

1, 4

1, 5

1, 6

= 3.3 V, Tj = 25 C

SDR

D5.1

D5.2

D5.3

D5.4

D5.5

D5.6

D5.7

MOTOROLA MPC5200 Hardware Specifications 9

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Electrical and Thermal Characteristics

3.1.6 Thermal Characteristics

Table 7 Thermal Resistance Data

Rating Value Unit Notes SpecID

Junction to Ambient Natural Convection

Junction to Ambient (@200 ft/min)

Junction to Board R

Junction to Case R

Junction to Package Top Natural Convection Ψ

1 Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site

(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board

thermal resistance. 2 Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. 3 Per JEDEC JESD51-6 with the board horizontal. 4 Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is mea-

sured on the top surface of the board near the package. 5 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1). 6 Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is

written as Psi-JT.

Single layer board (1s)

Four layer board (2s2p) R

Single layer board (1s)

Four layer board (2s2p)

θJA

θJMA

θJB θJC

30 °C/W 1,

22 °C/W1,

24 °C/W1,

19 °C/W1,

14 °C/W

8°C/W

2°C/W

3.1.6.1 Heat Dissipation

An estimation of the chip-junction temperature, TJ, can be obtained from the following equation:

where:

TJ=TA+(R

= ambient temperature for the package ( ºC)

= junction to ambient thermal resistance (º C/W )

θJA

= power dissipation in package (W)

θJA

× P

) Eqn. 1

D6.1

D6.2

D6.3

D6.4

D6.5

D6.6

D6.7

The junction to ambient thermal resistance is an industry standard value, which provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single layer board, and the value obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which value is correct depends on the power dissipated by other components on the board. The value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated.

Historically, the thermal resistance has frequently been expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance:

10 MPC5200 Hardware Specifications M O T O R O L A

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Electrical and Thermal Characteristics

where:

= junction to ambient thermal resistance ( ºC/ W)

θJA

= junction to case thermal resistance (ºC/ W)

θJC

= case to ambient thermal resistance (ºC/ W)

θCA

is device related and cannot be influenced by the user. The user controls the thermal environment to

θJC

change the case to ambient thermal resistance, R around the device, add a heat sink, change the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This description is most useful for ceramic packages with heat sinks where some 90% of the heat flow is through the case to the heat sink to ambient. For most packages, a better model is required.

A more accurate thermal model can be constructed from the junction to board thermal resistance and the junction to case thermal resistance

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used or where a substantial amount of heat is dissipated from the top of the package. The junction to board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. This model can be used for either hand estimations or for a computational fluid dynamics (CFD) thermal model.

To determine the junction temperature of the device in the application after prototypes are available, the

Thermal Characterization Parameter (Ψ

measurement of the temperature at the top center of the package case using the following equation:

1-3

. The junction to case covers the situation where a heat sink will be

θJA

) can be used to determine the junction temperature with a

θJC+RθCA

. For instance, the user can change the air flow

θCA

Eqn. 2

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TJ=T

where:

= thermocouple temperature on top of package (ºC)

= thermal characterization parameter ( ºC/ W)

= power dissipation in package ( W)

The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned, so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over approximately one mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire.

+(ΨJT × P

) Eqn. 3

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Electrical and Thermal Characteristics

3.2 Oscillator and PLL Electrical Characteristics

The MPC5200 System requires a system-level clock input SYS_XTAL. This clock input may be driven directly from an external oscillator or with a crystal using the internal oscillator.

There is a separate oscillator for the independent Real-Time Clock (RTC) system.

The MPC5200 clock generation uses two phase locked loop (PLL) blocks.

• The system PLL (SYS_PLL) takes an external reference frequency and generates the internal system clock. The system clock frequency is determined by the external reference frequency and the settings of the SYS_PLL configuration.

• The G2_LE core PLL (CORE_PLL) generates a master clock for all of the CPU circuitry. The G2_LE core clock frequency is determined by the system clock frequency and the settings of the CORE_PLL configuration.

3.2.1 System Oscillator Electrical Characteristics

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Table 8 System Oscillator Electrical Characteristics

Characteristic Symbol Notes Min Typical Max Unit SpecID

SYS_XTAL frequency f

Oscillator start-up time t

sys_xtal

up_osc

15.6 33.3 35.0 MHz O1.1

3.2.2 RTC Oscillator Electrical Characteristics

Table 9 RTC Oscillator Electrical Characteristics

Characteristic Symbol Notes Min Typical Max Unit SpecID

RTC_XTAL frequency f

rtc_xtal

— — 100 µsO1.2

— 32.768 — kHz O2.1

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3.2.3 System PLL Electrical Characteristics

Table 10 System PLL Specifications

Characteristic Symbol Notes Min Typical Max Unit SpecID

Electrical and Thermal Characteristics

SYS_XTAL frequency f

SYS_XTAL cycle time T

SYS_XTAL clock input jitter t

System VCO frequency f

System PLL relock time t

1 The SYS_XTAL frequency and PLL Configuration bits must be chosen such that the resulting system frequency, CPU

(core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequen-

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cies.

2 This represents total input jitter - short term and long term combined - and is guaranteed by design. Two different types

of jitter can exist on the input to core_sysclk, systemic and true random jitter. True random jitter is rejected, but the PLL. Systemic jitter will be passed into and through the PLL to the internal clock circuitry, directly reducing the operating frequency.

3 Relock time is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for

the PLL lock after a stable Vdd and core_sysclk are reached during the power-on reset sequence. This specification also applies when the PLL has been disabled and subsequently re-enabled during sleep modes.

sys_xtal

jitter

VCOsys

lock

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15.6 33.3 35.0 MHz O3.1

66.6 30.0 28.5 ns O3.2

— — 150 ps O3.3

250 533 800 MHz O3.4

——100µsO3.5

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Electrical and Thermal Characteristics

3.2.4 G2_LE Core PLL Electrical Characteristics

The internal clocking of the G2_LE core is generated from and synchronized to the system clock by means of a voltage-controlled core PLL.

Table 11 G2_LE PLL Specifications

Characteristic Symbol Notes Min Typical Max Unit SpecID

G2_LE frequency f

G2_LE cycle time t

G2_LE VCO frequency f

G2_LE input clock frequency f

G2_LE input clock cycle time t

G2_LE input clock jitter t

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G2_LE PLL relock time t

1 The SYSCLK frequency and G2_LE PLL Configuration bits must be chosen such that the resulting system frequencies,

CPU (core) frequency, and G2_LE PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies.

2 This represents total input jitter - short term and long term combined - and is guaranteed by design. Two different types

3 Relock time is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for

core

VCOcore

SYSCLK

jitter

lock

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50 — 550 MHz O4.1

2.85 — 40.0 ns O4.2

400 — 1200 MHz O4.3

25 — 367 MHz O4.4

2.73 — 50.0 ns O4.5

— — 150 ps O4.6

— — 100 µsO4.7

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14 MPC5200 Hardware Specifications M O T O R O L A

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Electrical and Thermal Characteristics

3.3 AC Electrical Characteristics

Hyperlinks to the indicated timing specification sections are provided below.

• AC Operating Frequency Data • USB

• Clock AC Specifications • SPI

• Resets • MSCAN

• External Interrupts

• SDRAM • J1850

•PCI •PSC

• Local Plus Bus • GPIOs and Timers

• ATA • IEEE 1149.1 (JTAG) AC Specifications

• Ethernet

•I

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AC Test Timing Conditions:

Unless otherwise noted, all test conditions are as follows:

• TA = -40 to 85

• Tj = -40 to 115

• VDD_CORE = 1.42 to 1.58 V VDD_IO = 3.0 to 3.6 V

• Input conditions: All Inputs: tr, tf <= TBD

• Output Loading: All Outputs: 50 pF

3.3.1 AC Operating Frequency Data

Table 12 provides the operating frequency information for the MPC5200.

Table 12 Clock Frequencies

Min Max Units SpecID

1 G2_LE Processor Core — 400 MHz A1.1

2 SDRAM Clock — 133 MHz A1.2

3 XL Bus Clock — 133 MHz A1.3

4 IP Bus Clock — 133 MHz A1.4

5 PCI / Local Plus Bus Clock — 66 MHz A1.5

6 PLL Input Range 15.6 35 MHz A1.6

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Electrical and Thermal Characteristics

3.3.2 Clock AC Specifications

CYCLE

FAL L

SYSCLK

DUTY

RISE

Figure 2 Timing Diagram—SYS_XTAL_IN

Table 13 SYS_XTAL_IN Timing

Sym Description Min Max Units SpecID

CYCLE

SYS_XTAL_IN cycle time.

28.6 64.1 ns A2.1

nc...

cale Semiconductor,

Frees

RISE

FALL

DUTY

1 CAUTION—The SYS_XTAL_IN frequency and system PLL_CFG[0-6] settings must be chosen such that the resulting

2 SYS_XTAL_IN duty cycle is measured at VM.

SYS_XTAL_IN rise time. — 5.0 ns A2.2

SYS_XTAL_IN fall time. — 5.0 ns A2.3

SYS_XTAL_IN duty cycle (measured at VM). 2

SYS_XTAL_IN input voltage high 2.0 — V A2.5

SYS_XTAL_IN input voltage low — 0.8 V A2.6

system frequencies do not exceed their respective maximum or minimum operating frequencies. See the MPC5200 User Manual [1].

40.0 60.0 % A2.4

16 MPC5200 Hardware Specifications M O T O R O L A

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3.3.3 Resets

The MPC5200 has three reset pins:

Electrical and Thermal Characteristics

• PORESET

• HRESET

• SRESET

These signals are asynchronous I /O signals and can be asserted at any time. The input side uses a Schmitt trigger and requires the same input characteristics as other MPC5200 inputs, as specified in the DC Electrical Specifications section. Table 14 specifies the pulse widths of the Reset inputs.

- Power on Reset

- Hard Reset

- Software Reset

Table 14 Reset Pulse Width

Name Description Min Pulse Width

PORESET

nc...

HRESET

SRESET

Notes:

1. For PORESET wards its minimum pulse width equals the minimum given for HRESET

2. The t

3. For t

4. For t

5. Following the deassertion of PORESET

6. The deassertion of HRESET 4096 clock cycles.

Power On Reset t

Hardware Reset 4 clock cycles — SYS_XTAL_IN A3.2

Software Reset 4 clock cycles — SYS_XTAL_IN A3.3

the value of the minimum pulse width reflects the power on sequence. If PORESET is asserted after-

VDD_stable

lock,

up_osc,

describes the time which is needed to get all power supplies stable.

refer to the Oscillator/PLL section of this specification for further details.

VDD_stable+tup_osc+tlock

, HRESET and SRESET remain low for 4096 reference clock cycles.

for at least the minimum pulse width forces the internal resets to be active for an additional

NOTE:

As long as VDD is not stable the HRESET

Table 15 Reset Rise / Fall Timing

Description Min Max Unit SpecID

cale Semiconductor,

PORESET

HRESET

fall time — 1 ms A3.4

rise time — 1 ms A3.5

fall time — TBD ns A3.6

Max Pulse

Width

— SYS_XTAL_IN A3.1

related to the same reference clock.

Reference Clock SpecID

output is not stable.

Frees

HRESET

SRESET

For additional information, see the MPC5200 User Manual [1].

MOTOROLA MPC5200 Hardware Specifications 1 7

rise time — TBD ns A3.7

fall time — TBD ns A3.8

rise time — TBD ns A3.9

NOTE:

Make sure that the PORESET has no filter to prevent them from getting into the chip.

does not carry any glitches. The MPC5200

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Electrical and Thermal Characteristics

3.3.3.1 Reset Configuration Word

During reset (HRESET and PORESET) the Reset Configuration Word is cached in the related Reset Configuration Word Register with each rising edge of the SYS_XTAL signal. If both resets (HRESET PORESET (see Figure 3).

) are inactive (high), the contents of this register get locked after two further SYS_XTAL cycles

SYS_XTAL

PORESET

HRESET

RST_CFG_WRD

4096 clocks 2 clocks

and

nc...

cale Semiconductor,

Frees

sample

Beware of changing the values on the pins of the reset configuration word after the deassertion of PORESET may change the internal clock ratios and so extend the PLL locking process.

sample

Figure 3 Reset Configuration Word Locking

sample sample

sample

sample sample

NOTE:

. This may cause problems because it

sample

LOCK

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Electrical and Thermal Characteristics

3.3.4 External Interrupts

The MPC5200 provides three different kinds of external interrupts:

• Four IRQ interrupts

• Eight GPIO interrupts with simple interrupt capability (not available in power-down mode)

• Eight WakeUp interrupts (special GPIO pins)

The propagation of these three kinds of interrupts to the core is shown in the following graphic:

nc...

cale Semiconductor,

Frees

IRQ0

8 GPIOs

8 GPIOs GPIO WakeUp

IRQ1

IRQ2

IRQ3

Due to synchronization, prioritization, and mapping of external interrupt sources, the propagation of external interrupts to the core processor is delayed by several IP_CLK clock cycles. The following table specifies the interrupt latencies in IP_CLK cycles. The IP_CLK frequency is programmable in the Clock Distribution Module (see Note Table 16).

Interrupt Type Pin Name Clock Cycles Reference Clock Core Interrupt SpecID

Interrupt Requests IRQ0 10 IP_CLK critical (cint) A4.1

GPIO Std

Notes:

1. PIs = Programmable Inputs

2. Grouper and Encoder functions imply programmability in software

Figure 4 External interrupt scheme

Table 16 External interrupt latencies

IRQ0 10 IP_CLK normal (int) A4.2

IRQ1 10 IP_CLK normal (int) A4.3

cint

int

PIs

Main Interrupt

Controller

Encoder

Grouper Encoder

core_cint

core_int

G2_LE Core

IRQ2 10 IP_CLK normal (int) A4.5

IRQ3 10 IP_CLK normal (int) A4.6

MOTOROLA MPC5200 Hardware Specifications 1 9

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Electrical and Thermal Characteristics

Table 16 External interrupt latencies (continued)

Interrupt Type Pin Name Clock Cycles Reference Clock Core Interrupt SpecID

Standard GPIO Interrupts GPIO_PSC3_4 12 IP_CLK normal (int) A4.7

GPIO_PSC3_5 12 IP_CLK normal (int) A4.8

GPIO_PSC3_8 12 IP_CLK normal (int) A4.9

GPIO_USB_9 12 IP_CLK normal (int) A4.10

GPIO_ETHI_4 12 IP_CLK normal (int) A4.11

GPIO_ETHI_5 12 IP_CLK normal (int) A4.12

GPIO_ETHI_6 12 IP_CLK normal (int) A4.13

GPIO_ETHI_7 12 IP_CLK normal (int) A4.14

GPIO WakeUp Interrupts GPIO_PSC1_4 12 IP_CLK normal (int) A4.15

nc...

cale Semiconductor,

Frees

GPIO_PSC2_4 12 IP_CLK normal (int) A4.16

GPIO_PSC3_9 12 IP_CLK normal (int) A4.17

GPIO_ETHI_8 12 IP_CLK normal (int) A4.18

GPIO_IRDA_0 12 IP_CLK normal (int) A4.19

DGP_IN0 12 IP_CLK normal (int) A4.20

DGP_IN1 12 IP_CLK normal (int) A4.21

Notes:

1) The frequency of IP_CLK depends on register settings in Clock Distribution Module. See the MPC5200 User Manual [1].

2) The interrupt latency descriptions in the table above are related to non competitive, non masked but enabled external interrupt sources. Take care of interrupt prioritization which may increase the latencies.

Since all external interrupt signals are synchronized into the internal processor bus clock domain, each of these signals has to exceed a minimum pulse width of more than one IP_CLK cycle.

Table 17 Minimum pulse width for external interrupts to be recognized

Name Min Pulse Width Max Pulse Width Reference Clock SpecID

All external interrupts (IRQs, GPIOs) > 1 clock cycle — IP_CLK A4.22

Notes:

1) The frequency of the IP_CLK depends on the register settings in Clock Distribution Module. See the MPC5200 User Manual [1] for further information.

2) If the same interrupt occurs a second time while its interrupt service routine has not cleared the former one, the second interrupt will not be recognized at all.

Besides synchronization, prioritization, and mapping the latency of an external interrupt to the start of its associated interrupt service routine also depends on the following conditions: To get a minimum interrupt service response time, it is recommended to enable the instruction cache and set up the maximum core clock, XL bus, and IP bus frequencies (depending on board design and programming). In addition, it is advisable to execute an interrupt handler, which has been implemented in assembly code.

20 MPC5200 Hardware Specifications M O T O R O L A

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Electrical and Thermal Characteristics

3.3.5 SDRAM

3.3.5.4 Memory Interface Timing-Standard SDRAM Read Command

Table 18 Standard SDRAM Memory Read Timing

Sym Description Min Max Units SpecID

nc...

cale Semiconductor,

Frees

mem_clk

valid

hold

data

MBA (Bank Selects)

MEM_CLK period 7.5 — ns A5.1

Control Signals, Address and MBA Valid after rising edge of MEM_CLK

Control Signals, Address and MBA Hold after rising edge of MEM_CLK

DQM valid after rising edge of

valid

MEM_CLK

DQM hold after rising edge of MEM_CLK t

hold

MDQ setup to rising edge of MEM_CLK — 0.3 ns A5.6

setup

MDQ hold after rising edge of MEM_CLK 0.2 — ns A5.7

hold

MEM_CLK

Control Signals

DQM (Data Mask)

MDQ (Data)

MA (Address)

—t

mem_clk

valid

hold

Active NOP READ NOPNOPNOP NOP

valid

hold

Row Column

hold

*0.5 — ns A5.3

—t

*0.25-0.7 — ns A5.5

hold

data

setup

mem_clk

NOP

*0.5+0.4 ns A5.2

*0.25+0.4 ns A5.4

data

hold

NOTE: Control Signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN

Figure 5 Timing Diagram—Standard SDRAM Memory Read Timing

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Electrical and Thermal Characteristics

3.3.5.5 Memory Interface Timing-Standard SDRAM Write Command

In Standard SDRAM, all signals are activated on the Mem_clk from the Memory Controller and captured on the Mem_clk clock at the memory device.

Table 19 Standard SDRAM Write Timing

Sym Description Min Max Units SpecID

nc...

cale Semiconductor,

Frees

mem_clk

valid

hold

valid

hold

data

DQM (Data Mask)

MBA (Bank Selects)

MEM_CLK period 7.5 — ns A5.8

Control Signals, Address and MBA Valid after rising edge of MEM_CLK

Control Signals, Address and MBA Hold after rising edge of MEM_CLK

DQM valid after rising edge of MEM_CLK

DQM hold after rising edge of Mem_clk t

MDQ valid after rising edge of

valid

MEM_CLK

MDQ hold after rising edge of

hold

MEM_CLK

Control Signals

MDQ (Data)

MA (Address)

—t

mem_clk

valid

hold

Active NOP WRITE NOPNOPNOPNOP NOP

valid

data

valid

hold

Row Column

hold

*0.5 — ns A5.10

—t

*0.25-0.7 — ns A5.12

—t

*0.75-0.7 — ns A5.14

hold

data

hold

mem_clk

*0.5+0.4 ns A5.9

*0.25+0.4 ns A5.11

*0.75+0.4 ns A5.13

NOTE: Control Signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN

Figure 6 Timing Diagram—Standard SDRAM Memory Write Timing

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Electrical and Thermal Characteristics

3.3.5.6 Memory Interface Timing-DDR SDRAM Read Command

The SDRAM Memory Controller uses an internally skewed clock for reading DDR memory. The programmable bits in the Reset Configuration Register used to account for unknown board delays are in the CDM module. The internal read clock can be delayed up to 3 ns under worst operating conditions in 32 increments of 95 ps, (1.4 ns in 45 ps increments under best case operating conditions) by programming the CDM Reset Configuration Register tap delay bits. Note: These bits in the CDM Reset Configuration register are not ‘reset configured’ but have a hard coded reset value and are writable during operation.

Table 20 DDR SDRAM Memory Read Timing

Sym Description Min Max Units SpecID

mem_clk

valid

hold

nc...

data

cale Semiconductor,

MDQS (Data Strobe)

MEM_CLK period 7.5 — ns A5.15

Control Signals, Address and MBA valid after rising edge of MEM_CLK

Control Signals, Address and MBA hold after rising edge of MEM_CLK

Setup time skewed by CDM Reset

setup

Config Reg [3:7] = 0b00010

Hold time skewed by CDM Reset Con-

hold

fig Reg [3:7] = 0b00010

MEM_CLK

valid

Control Signals

Active NOP READ NOPNOPNOPNOP NOP

hold

—t

mem_clk

*0.5 — ns A5.17

— 0.4 ns A5.18

2.34 — ns A5.19

mem_clk

*0.5+0.4 ns A5.16

Frees

data

MDQ (Data)

valid

MA (Address)

valid

MBA (Bank Selects)

NOTE: Control Signals signals are composed of RAS, CAS, MEM_WE

Row Column

hold

setup

, MEM_CS, MEM_CS1 and CLK_EN

data

hold

Figure 7 Timing Diagram—DDR SDRAM Memory Read Timing

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Electrical and Thermal Characteristics

3.3.5.7 Memory Interface Timing-DDR SDRAM Write Command

Table 21 DDR SDRAM Memory Write Timing

Sym Description Min Max Units SpecID

mem_clk

DQSS

MEM_CLK

nc...

MEM_CLK

Control Signals

MDQS (Data Strobe)

MDQ (Data)

cale Semiconductor,

NOTE: Control Signals signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN

MEM_CLK period 7.5 — ns

Delay from write command to first rising edge of MDQS

Write

dqss

Figure 8 DDR SDRAM Memory Write Timing

Write

—t

mem_clk

+0.4 ns

WriteWrite

A5.20

A5.21

Frees

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Electrical and Thermal Characteristics

3.3.6 PCI

The PCI interface on the MPC5200 is designed to PCI Version 2.2 and supports 33-MHz and 66-MHz PCI operations. See the PCI Local Bus Specification [4]; the component section specifies the electrical and timing parameters for PCI components with the intent that components connect directly together whether on the planar or an expansion board, without any external buffers or other “glue logic.” Parameters apply at the package pins, not at expansion board edge connectors.

The MPC5200 is always the source of the PCI CLK. The clock waveform must be delivered to each 33-MHz or 66-MHz PCI component in the system. Figure 9 shows the clock waveform and required measurement points for 3.3 V signaling environments. Tab le 2 2 summarizes the clock specifications.

cyc

high

0.5Vcc

PCI CLK

nc...

0.4Vcc

0.3Vcc

Figure 9 PCI CLK Waveform

0.6Vcc

low

0.2Vcc

0.4Vcc, p-to-p (minimum)

cale Semiconductor,

Frees

Table 22 PCI CLK Specifications

66 MHz 33 MHz

Sym Description

Min Max Min Max

PCI CLK Cycle Time 15 30 30 ns 1,3 A6.1

cyc

PCI CLK High Time 6 11 ns A6.2

high

PCI CLK Low Time 6 A6.3

low

- PCI CLK Slew Rate 1.5 4 1 4 V/ns 2 A6.4

NOTES:

1. In general, all 66-MHz PCI components must work with any clock frequency up to 66 MHz. CLK requirements vary depending upon whether the clock frequency is above 33 MHz.

2. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown in

3. The minimum clock period must not be violated for any single clock cycle, i.e., accounting for all system jitter.

Figure 9.

Units Notes SpecID

Table 23 PCI Timing Parameters

66 MHz 33 MHz

Sym Description

CLK to Signal Valid Delay -

val

bused signals

Min Max Min Max

2 6 2 11 ns 1,2,3 A6.5

Units Notes SpecID

(ptp) CLK to Signal Valid Delay -

val

MOTOROLA MPC5200 Hardware Specifications 2 5

point to point

Float to Active Delay 2 2 ns 1 A6.7

Active to Float Delay 14 28 ns 1 A6.8

off

2 6 2 12 ns 1,2,3 A6.6

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Electrical and Thermal Characteristics

Table 23 PCI Timing Parameters (continued)

Sym Description

66 MHz 33 MHz

Units Notes SpecID

Min Max Min Max

nc...

cale Semiconductor,

Frees

For Measurement and Test Conditions, see the PCI Local Bus Specification [4].

Input Setup Time to CLK -

bused signals

(ptp) Input Setup Time to CLK -

point to point

Input Hold Time from CLK 0 0 ns 4 A6.11

NOTES:

1. See the timing measurement conditions in the PCI Local Bus Specification [4]. It is important that all driven signal transitions drive to their Voh or Vol level within one Tcyc.

2. Minimum times are measured at the package pin with the load circuit, and maximum times are measured with the load circuit as shown in the PCI Local Bus Specification [4].

3. REQ# and GNT# are point-to-point signals and have different input setup times than do bused signals. GNT# and REQ# have a setup of 5 ns at 66 MHz. All other signals are bused.

4. See the timing measurement conditions in the PCI Local Bus Specification [4].

3 7 ns 3,4 A6.9

5 10,12 ns 3,4 A6.10

3.3.7 Local Plus Bus

The Local Plus Bus is the external bus interface of the MPC5200. Eight configurable Chip-selects are provided. There are two main modes of operation: non-MUXed and MUXED. The reference clock is the PCI CLK. Refer to PCI CLK specification. The maximum bus frequency is 66 MHz.

The following timing numbers indicate when data will be latched or driven onto the external bus, relative to the PCI CLK.

PCI CLK

OUTPUT

SIGNALS

1 PCI CLK to Signal hold 2 PCI CLK to Signal valid 3 PCI CLK to Signal Hi Z

Figure 10 Output Signals Timing

3.3.7.1 Non-MUXed Mode

Table 24 Non-MUXed Mode Timing

Sym Description Min Max Units Notes SpecID

26 MPC5200 Hardware Specifications M O T O R O L A

PCI CLK to ADDR valid - 2 ns A7.1

PCI CLK to ADDR hold 1 - ns A7.2

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Electrical and Thermal Characteristics

Table 24 Non-MUXed Mode Timing (continued)

Sym Description Min Max Units Notes SpecID

CSA

CSN

OEA

OEN

RWV

RWH

TSIZV

nc...

TSIZH

NOTES:

1. Wait states for Reads and Writes can be specified as 0 to 127.

2. Dead cycles can be specified as 0 to 3. Dead cycles will be added to the end of Chip Select read access and will occur

3. Transfer Size TSIZE(1:0) are available in Non-MUXed mode for MOST Graphics or Large Flash Modes only. For understanding the different hold/valid/assertion/negation times refer to Figure 10. The timing values in the above table are for a clock ratio of IP_CLK : PCI_CLK = 1 : 1 only. The values will be different for other IP_CLK : PCI_CLK clock ratios.

cale Semiconductor,

PCI CLK to DATA output valid - 2 ns A7.3

PCI CLK to DATA output Hi Z - 2 ns A7.4

PCI CLK to CS assertion - 1.8 ns A7.5

PCI CLK to CS negation - 1.8 ns A7.6

PCI CLK to OE assertion - 1.5 ns A7.7

PCI CLK to OE negation - 1.5 ns A7.8

PCI CLK to RW valid - 1 ns A7.9

PCI CLK to RW hold 1 - ns A7.10

PCI CLK to TSIZ valid - 2 ns A7.11

PCI CLK to TSIZ hold 1 - ns A7.12

DATA input to PCI CLK setup 2 - ns A7.13

DATA input to PCI CLK hold - 1 ns A7.14

in addition to any cycles which may already exist. These cycles provide a peripheral additional time to tri-state its bus after a read operation. This is for all access types.

Frees

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Electrical and Thermal Characteristics

PCI_CLK

nc...

cale Semiconductor,

Frees

ADDR

CS[x]

R/W

DATA (wr) Valid Write Data

DATA (rd)

Note: 1. The tRD/tWR is wait states as programmed for corresponding access and chip select.

2. OE is active during Read only, tOE is the Output Enable to Output Delay time

3. Read data has nominal setup/hold requirements around the CS negation.

Valid Address

tRD or t

Valid Read Data

Figure 11 Timing Diagram—Non-MUXed Mode

3.3.7.2 MUXed Mode

Table 25 MUXed Mode Timing

Sym Description Min Max Units Notes SpecID

CSA

CSN

OEA

OEN

RWV

RWH

ALEA

ALEN

PCI CLK to ADDR valid

PCI CLK to ADDR hold

PCI CLK to DATA output valid

PCI CLK to DATA output Hi Z

PCI CLK to CS assertion

PCI CLK to CS negation

PCI CLK to OE assertion

PCI CLK to OE negation

PCI CLK to RW valid

PCI CLK to RW hold

PCI CLK to ALE assertion

PCI CLK to ALE negation

DATA input to PCI CLK setup

-2ns A7.15

1-ns A7.16

-2ns A7.17

-2ns A7.18

- 1.8 ns A7.19

- 1.8 ns A7.20

- 1.5 ns A7.21

- 1.5 ns A7.22

-1ns A7.23

1-ns A7.24

-2ns A7.25

-2ns A7.26

2-ns A7.27

28 MPC5200 Hardware Specifications M O T O R O L A

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Table 25 MUXed Mode Timing (continued)

Sym Description Min Max Units Notes SpecID

Electrical and Thermal Characteristics

nc...

cale Semiconductor,

Frees

NOTES:

1. Wait states for Reads and Writes can be inserted when configured.

2. Dead cycles can be specified as 0 to 3. Dead cycles will be added to the end of Chip Select read access and will occur

DATA input to PCI CLK hold

in addition to any cycles which may already exist. These cycles provide a peripheral additional time to tri-state its bus after a read operation. This is for all access types.

-1ns A7.28

Start Bus Tenure End Bus Tenure

PCI CLK AD[31,27] AD[30:28] AD[26:25]

AD[24:0]

ALE

TSIZ[0:2] bits

Bank[0:1] bits

Address[7:31]

short

long

short

Data or tri-state

long

Wait States

(0-127)

Dead Cycles

(0-3)

CSx

tri-state

ACK Input

Address "tenure"

Figure 12 Timing Diagram - MUXed Mode

MOTOROLA MPC5200 Hardware Specifications 2 9

Data "tenure"

"Dack"

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Electrical and Thermal Characteristics

3.3.8 ATA

The MPC5200 ATA Controller is completely software programmable. It can be programmed to operate with ATA protocols using their respective timing, as described in the ANSI ATA-4 specification. The ATA interface is completely asynchronous in nature. Signal relationships are based on specific fixed timing in terms of timing units (nano seconds).

ATA data setup and hold times, with respect to Read/Write strobes, are software programmable inside the ATA Controller. Data setup and hold times are implemented using counters. The counters count the number of ATA clock cycles needed to meet the ANSI ATA-4 timing specifications. For details, see the ANSI ATA-4 specification [5] and how to program an ATA Controller and ATA drive for different ATA protocols and their respective timing. See the MPC5200 User Manual

The MPC5200 ATA Host Controller design makes data available coincidentally with the active edge of the WRITE strobe in PIO and Multiword DMA modes.

• Write data is latched by the drive at the inactive edge of the WRITE strobe. This gives ample

setup-time beyond that required by the ATA-4 specification.

• Data is held unchanged until the next active edge of the WRITE strobe. This gives ample hold-time

nc...

All ATA transfers are programmed in terms of system clock cycles (IP bus clocks) in the ATA Host Controller timing registers. This puts constraints on the ATA protocols and their respective timing modes in which the ATA Controller can communicate with the drive.

beyond that required by the ATA-4 specification.

[1].

cale Semiconductor,

Frees

Faster ATA modes (i.e., UDMA 0, 1, 2) are supported when the system is running at a sufficient frequency to provide adequate data transfer rates. Adequate data transfer rates are a function of the following:

• The MPC5200 operating frequency (IP bus clock frequency )

• Internal MPC5200 bus latencies

• Other system load dependent variables

The ATA clock is the same frequency as the IP bus clock in MPC5200. See the MPC5200 User Manual [1].

NOTE:

All output timing numbers are specified for nominal 50 pF loads.

Table 26 PIO Mode Timing Specifications

Min/Ma

PIO Timing Parameter

(ns)

t0 Cycle Time min 600 383 240 180 120 A8.1

t1 Address valid to DIOR

setup

t2 DIOR

/DIOW pulse width 16-bit

/DIOW

8-bit

min7050303025A8.2

min min

Mode 0

(ns)

165 290

Mode 1

(ns)

125 290

Mode 2

(ns)

100 290

Mode 3

(ns)

80 80

Mode 4

(ns)

70 70

SpecID

A8.3

t2i DIOR

t3 DIOW

t4 DIOW

t5 DIOR

t6 DIOR

30 MPC5200 Hardware Specifications M O T O R O L A

/DIOW recovery time min — — — 70 25 A8.4

data setup min6045303020A8.5

data hold min 30 20 15 10 10 A8.6

data setup min5035202020A8.7

data hold min55555A8.8

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Table 26 PIO Mode Timing Specifications (continued)

Electrical and Thermal Characteristics

nc...

cale Semiconductor,

Frees

Min/Ma

PIO Timing Parameter

(ns)

t9 IOR/DIOW to address

valid hold

tAIORDY setup max3535353535A8.10

tB IORDY pulse width max 1250 1250 1250 1250 1250 A8.11

[0]/CS[3]/DA[2:0]

/DIOW

DIOR

WDATA

RDATA

IORDY

Table 27 Multiword DMA Timing Specifications

Multiword DMA Timing Parameters Min/Max Mode 0(ns) Mode 1(ns) Mode 2(ns) SpecID

min2015101010A8.9

tA tB

Figure 13 PIO Mode Timing

Mode 0

(ns)

Mode 1

(ns)

Mode 2

(ns)

t0t1

t3 t4

t5 t6

Mode 3

(ns)

Mode 4

(ns)

t8t9

SpecID

t0 Cycle Time min 480 150 120 A8.12

tC DMACK

tD DIOR

tE DIOR

tG DIOR

tF DIOR

tH DIOW

MOTOROLA MPC5200 Hardware Specifications 3 1

to DMARQ delay max — — — A8.13

/DIOW pulse width (16-bit) min 215 80 70 A8.14

data access max 150 60 50 A8.15

/DIOW data setup min 100 30 20 A8.16

data hold min 5 5 5 A8.17

data hold min 20 15 10 A8.18

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Electrical and Thermal Characteristics

Table 27 Multiword DMA Timing Specifications (continued)

Multiword DMA Timing Parameters Min/Max Mode 0(ns) Mode 1(ns) Mode 2(ns) SpecID

tI DMACK to DIOR/DIOW setup min 0 0 0 A8.19

nc...

cale Semiconductor,

Frees

tJ DIOR

tKr DIOR

tKw DIOW

tLr DIOR

tLw DIOW

DMACK

NOTE:The directionof signalassertionis towardsthe top of the page, and the direction of negation is towards the bottom of the page, irrespective of the electrical properties of the signal.

/DIOW to DMACK hold min 20 5 5 A8.20

negated pulse width min 50 50 25 A8.21

negated pulse width min 215 50 25 A8.22

to DMARQ delay max 120 40 35 A8.23

to DMARQ delay max 40 40 35 A8.24

DMARQ (Drive)

(Host)

tI tD

DIOR DIOW (Host)

RDATA (Drive)

WDATA (Host)

Figure 14 Multiword DMA Timing

Table 28 Ultra DMA Timing Specification

MODE 0

Name

(t)

2CYC

32 MPC5200 Hardware Specifications M O T O R O L A

(ns)

Min Max Min Max Min Max

240 — 160 — 120 — Typical sustained average two cycle time. A8.25

MODE 1

(ns)

MODE 2

(ns)

Comment SpecID

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Electrical and Thermal Characteristics

Table 28 Ultra DMA Timing Specification (continued)

nc...

cale Semiconductor,

Frees

Name

(t)

CYC

(t)

2CYC

(t)

DVS

(t)

DVH

(t)

ZAH

(t)

ZAD

(t)

ENV

(t)

MLI

MODE 0

(ns)

Min Max Min Max Min Max

114 — 75 — 55 — Cycle time allowing for asymmetry and clock

235 — 156 — 117 — Two-cycle time allowing for clock variations,

15 — 10 — 7 — Data setup time at recipient. A8.28

5 — 5 — 5 — Data hold time at recipient. A8.29

70 — 48 — 34 — Data valid setup time at sender, to STROBE

6 — 6 — 6 — Data valid hold time at sender, from STROBE

0 230 0 200 0 170 First STROBE time for drive to first negate

0 150 0 150 0 150 Limited Interlock time. 1

20 — 20 — 20 — Interlock time with minimum.

0 — 0 — 0 — Unlimited interlock time.

— 10 — 10 — 10 Maximum time allowed for output drivers to

20 — 20 — 20 — Minimum delay time required for output drivers

0—0—0— A8.38

20 70 20 70 20 70 Envelope time—from DMACK to STOP and

—50—30—20STROBE to DMARDY time, if DMARDY is

MODE 1

(ns)

MODE 2

(ns)

Comment SpecID

variations from STROBE edge to STROBE edge

from rising edge to next rising edge or from falling edge to next falling edge of STROBE.

edge.

DSTROBE from STOP during a data-in burst.

1 2

release from being asserted or negated

to assert or negate from released state

HDMARDY

negated before this long after STROBE edge, the recipient receives no more than one additional data word.

during data out burst initiation.

A8.26

A8.27

A8.30

A8.31

A8.32

A8.33

A8.34

A8.35

A8.36

A8.37

A8.39

A8.40

(t)

RFS

(t)

IORDYZ

MOTOROLA MPC5200 Hardware Specifications 3 3

— 75 — 60 — 50 Ready-to-Final STROBE time—no STROBE

edges are sent this long after negation of DMARDY

160 — 125 — 100 — Ready-to-Pause time—the time recipient waits

to initiate pause after negating DMARDY

— 20 — 20 — 20 Pull-up time before allowing IORDY to be

released.

A8.41

A8.42

A8.43

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Electrical and Thermal Characteristics

Table 28 Ultra DMA Timing Specification (continued)

MODE 0

Name

(t)

ZIORDY

(t)

ACK

(t)

1tUI, t

waiting for the other agent to respond with a signal before proceeding.

nc...

2 All timing parameters are measured at the connector of the drive to which the parameter applies. For example, the sender

shall stop generating STROBE edges t ments are taken at the connector of the sender. Even though the sender stops generating STROBE edges, the receiver may receive additional STROBE edges due to propagation delays. All timing measurement switching points (low to high and high to low) are taken at 1.5 V.

cale Semiconductor,

(ns)

Min Max Min Max Min Max

0 — 0 — 0 — Minimum time drive waits before driving

20 — 20 — 20 — Setup and hold times for DMACK, before

50 — 50 — 50 — Time from STROBE edge to negation of

, tLI indicate sender-to-recipient or recipient-to-sender interlocks. That is, one agent (either sender or recipient) is

MLI

•t

is an unlimited interlock that has no maximum time value.

is a limited time-out that has a defined minimum.

•t

MLI

•t

is a limited time-out that has a defined maximum.

DMARQ

(device)

DMACK

(device)

STOP

(host)

HDMARDY

(host)

MODE 1

(ns)

MODE 2

(ns)

IORDY

assertion or negation.

DMARQ or assertion of STOP, when sender terminates a burst.

after negation of DMARDY. Both STROBE and DMARDY timing measure-

RFS

ZIORDY

ACK

ENV

ZAD

Comment SpecID

A8.44

A8.45

A8.46

Frees

DSTROBE

(device)

DD(0 :15 )

DA0, DA1, DA2,

[0:1]1

ACK

DVS

DVH

Figure 15 Timing Diagram—Initiating an Ultra DMA Data In Burst

34 MPC5200 Hardware Specifications M O T O R O L A

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DSTROBE

at device

DD(0:15 )

at device

DSTROBE

at host

Freescale Semiconductor, Inc.

DVH

CYC

DVS

2CYC

DVH

CYC

Electrical and Thermal Characteristics

DVS

DVH

2CYC

nc...

cale Semiconductor,

Frees

DD(0:15 )

at host

Figure 16 Timing Diagram—Sustained Ultra DMA Data In Burst

DMARQ (device)

DMARQ

(host)

STOP (host)

HDMARDY

(host)

DSTROBE

(device)

DD[0:15]

(device)

RFS

Figure 17 Timing Diagram—Host Pausing an Ultra DMA Data In Burst

MOTOROLA MPC5200 Hardware Specifications 3 5

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Electrical and Thermal Characteristics

DMARQ (device)

DMACK

(host)

STOP (host)

HDMARDY

(host)

DSTROBE

(device)

nc...

DD[0:15]

ZAH

DVS

MLI

CRC

ACK

IORDYZ

DVH

cale Semiconductor,

Frees

DA0,DA1,DA2,

[0:1]

Figure 18 Timing Diagram—Drive Terminating Ultra DMA Data In Burst

DMARQ

(device)

DMACK

(host)

STOP (host)

HDMARDY

(host)

DSTROBE

(device)

DD[0:15]

RFS

ACK

ZAH

MLI

DVS

CRC

DVH

ACK

IORDYZ

DA0,DA1,DA2,

CS[0:1]

ACK

Figure 19 Timing Diagram—Host Terminating Ultra DMA Data In Burst

36 MPC5200 Hardware Specifications M O T O R O L A

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nc...

cale Semiconductor,

Frees

DMARQ (device)

DMACK

(host)

STOP (host)

DDMARDY

(host)

HSTROBE

(device)

DD[0:15]

(host)

DA0,DA1,DA2,

CS[0:1]

HSTROBE

(host)

DD[0:15]

(host)

HSTROBE

(device)

DD[0:15]

(device)

Freescale Semiconductor, Inc.

ZIORDY

Electrical and Thermal Characteristics

ACK

ENV

DVS

DVH

Figure 20 Timing Diagram—Initiating an Ultra DMA Data Out Burst

2CYC

DVH

CYC

DVS

DVH

CYC

2CYC

DVS

DVH

Figure 21 Timing Diagram—Sustained Ultra DMA Data Out Burst

MOTOROLA MPC5200 Hardware Specifications 3 7

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Electrical and Thermal Characteristics

DMARQ

(device)

DMACK

(host)

STOP

(host)

DDMARDY

(device)

HSTROBE

RFS

nc...

cale Semiconductor,

Frees

DD[0:15]

(host)

Figure 22 Timing Diagram—Drive Pausing an Ultra DMA Data Out Burst

DMARQ (device)

DMACK

(host)

STOP (host)

DDMARDY

(device)

HSTROBE

(host)

DD[0:15]

(host)

DVS

MLI

CRC

ACK

IORDYZ

DVH

DA0,DA1,DA2,

[0:1]

ACK

Figure 23 Timing Diagram—Host Terminating Ultra DMA Data Out Burst

38 MPC5200 Hardware Specifications M O T O R O L A

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DMARQ

(device)

DMACK

(host)

STOP

(host)

DDMARDY

(device)

Freescale Semiconductor, Inc.

Electrical and Thermal Characteristics

MLI

IORDYZ

ACK

RFS

HSTROBE

nc...

(host)

DD[0:15]

(host)

DA0,DA1,DA2,

[0:1]

Figure 24 Timing Diagram—Drive Terminating Ultra DMA Data Out Burst

Table 29 Timing Specification ata_isolation

Sym Description Min Max Units SpecID

1 ata_isolation setup time 7 - IP Bus cycles A8.47

2 ata_isolation hold time 19 - IP Bus cycles A8.48

cale Semiconductor,

MLI

DVS

CRC

ACK

DVH

Frees

DIOR

ATA_ISOLATION

Figure 25 Timing Diagram-ATA-ISOLATION

MOTOROLA MPC5200 Hardware Specifications 3 9

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Electrical and Thermal Characteristics

3.3.9 Ethernet

AC Test Timing Conditions:

• Output Loading

All Outputs: 25 pF

Table 30 MII Rx Signal Timing

Sym Description Min Max Unit SpecID

M1 RXD[3:0 ], RX_DV, RX_ER to RX_CLK setup 10 — ns A9.1

M2 RX_CLK to RXD[ 3:0], RX_DV, RX_ER hold 10 — ns A9.2

M3 RX_CLK pulse width high 35% 65%

M4 RX_CLK pulse width low 35% 65%

1 RX_CLK shall have a frequency of 25% of data rate of the received signal. See the IEEE 802.3 Specification [6].

RX_CLK Period

A9.3

A9.4

nc...

cale Semiconductor,

Frees

RX_CLK (Input)

RXD[3:0] (inputs)

RX_DV RX_ER

Figure 26 Ethernet Timing Diagram—MII Rx Signal

Table 31 MII Tx Signal Timing

Sym Description Min Max Unit SpecID

M5 TX_CLK rising edge to TXD[3 :0], TX_EN,

TX_ER Delay

M6 TX_CLK pulse width high 35% 65%

M7 TX_CLK pulse width low 35% 65%

025 ns A9.5

TX_CLK Period

A9.6

A9.7

40 MPC5200 Hardware Specifications M O T O R O L A

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1 the TX_CLK frequency shall be 25% of the nominal transmit frequency, e.g., a PHY operating at 100 Mb/s must provide

a TX_CLK frequency of 25 MHz and a PHY operating at 10 Mb/s must provide a TX_CLK frequency of 2.5 MHz. See the IEEE 802.3 Specification [6].

TX_CLK (Input)

TXD[3:0] (Outputs)

TX_EN TX_ER

Figure 27 Ethernet Timing Diagram—MII Tx Signal

Electrical and Thermal Characteristics

nc...

cale Semiconductor,

Frees

Table 32 MII Async Signal Timing

Sym Description Min Max Unit SpecID

M8 CRS, COL minimum pulse width 1.5 — TX_CLK Period A9.8

CRS, COL

Figure 28 Ethernet Timing Diagram—MII Async

Table 33 MII Serial Management Channel Signal Timing

Sym Description Min Max Unit SpecID

M9 MDC falling edge to MDIO output delay 0 25 ns A9.9

M10 MDIO ( input) to MDC rising edge setup 10 — ns A9.10

M11 MDIO ( input) to MDC rising edge hold 10 — ns A9.11

M12 MDC pulse width high

M13 MDC pulse width low

M14 MDC period

160 — ns A9.12

160 — ns A9.13

400 — ns A9.14

1 MDC is generated by MPC5200 with a duty cycle of 50% except when MII_SPEED in the FEC MII_SPEED control

MOTOROLA MPC5200 Hardware Specifications 4 1

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Electrical and Thermal Characteristics

2 The MDC period must be set to a value of less then or equal to 2.5 MHz (to be compliant with the IEEE MII character-

istic) by programming the FEC MII_SPEED control register. See the MPC5200 User Manual [1].

MDC (Output)

MDIO (Output)

MDIO (Input)

nc...

Figure 29 Ethernet Timing Diagram—MII Serial Management

M10

M12

M13

M14

M11

cale Semiconductor,

Frees

3.3.10 USB

Table 34 Timing Specifications—USB Output Line

Sym Description Min Max Units SpecID

1 USB Bit width

2 Transceiver enable time 83.3 667 ns A10.2

3 Signal falling time — 7.9 ns A10.3

4 Signal rising time — 7.9 ns A10.4

1 Defined in the USB config register, (12 Mbit/s or 1.5 Mbit/s mode).

NOTE:

Output timing was specified at a nominal 50 pF load.

83.3 667 ns A10.1

42 MPC5200 Hardware Specifications M O T O R O L A

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USB_OE

Freescale Semiconductor, Inc.

Electrical and Thermal Characteristics

nc...

cale Semiconductor,

Frees

USB_TXN

USB_TXP

Figure 30 Timing Diagram—USB Output Line

3.3.11 SPI

Table 35 Timing Specifications — SPI Master Mode, Format 0 (CPHA = 0)

Sym Description Min Max Units SpecID

1 Cycle time 4 1024 IP-Bus

Cycle

2 Clock high or low time 2 512 IP-Bus

Cycle

3 Slave select clock delay 15.0 — ns A11.3

4 Output Data valid after Slave Select (SS

5 Output Data valid after SCK — 20.0 ns A11.5

6 Input Data setup time 20.0 — ns A11.6

7 Input Data hold time 20.0 — ns A11.7

8 Slave disable lag time 15.0 — ns A11.8

9 Sequential transfer delay 1 — IP-Bus

) — 20.0 ns A11.4

Cycle

A11.1

A11.2

A11.9

10 Clock falling time — 7.9 ns A11.10

11 Clock rising time — 7.9 ns A11.11

1 Inter Peripheral Clock is defined in the MPC5200 User Manual [1].

NOTE:

Output timing was specified at a nominal 50 pF load.

MOTOROLA MPC5200 Hardware Specifications 4 3

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Electrical and Thermal Characteristics

SCK

(CLKPOL=0)

Output

SCK

(CLKPOL=1)

Output

MOSI

nc...

Output

MISO

Input

cale Semiconductor,

Frees

Figure 31 Timing Diagram — SPI Master Mode, Format 0 (CPHA = 0)

Table 36 Timing Specifications — SPI Slave Mode, Format 0 (CPHA = 0)

Sym Description Min Max Units SpecID

1 Cycle time 4 1024

2 Clock high or low time 2 512

3 Slave select clock delay 15.0 — ns A11.14

4 Output Data valid after Slave Select (SS

5 Output Data valid after SCK — 50.0 ns A11.16

6 Input Data setup time 50.0 — ns A11.17

7 Input Data hold time 0.0 — ns A11.18

8 Slave disable lag time 15.0 — ns A11.19

9 Sequential Transfer delay 1 —

1 Inter Peripheral Clock is defined in the MPC5200 User Manual [1].

Output timing was specified at a nominal 50 pF load.

) — 50.0 ns A11.15

NOTE:

IP-Bus Cycle

A11.12

A11.13

A11.20

44 MPC5200 Hardware Specifications M O T O R O L A

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SCK

(CLKPOL=0)

Input

SCK

(CLKPOL=1)

Input

Freescale Semiconductor, Inc.

Electrical and Thermal Characteristics

nc...

cale Semiconductor,

Frees

MOSI

Input

MISO

Output

Figure 32 Timing Diagram — SPI Slave Mode, Format 0 (CPHA = 0)

Table 37 Timing Specifications — SPI Master Mode, Format 1 (CPHA = 1)

Sym Description Min Max Units SpecID

1 Cycle time 4 1024 IP-Bus

2 Clock high or low time 2 512 IP-Bus

3 Slave select clock delay 15.0 — ns A11.23

4 Output data valid — 20.0 ns A11.24

5 Input Data setup time 20.0 — ns A11.25

6 Input Data hold time 20.0 — ns A11.26

A11.21

Cycle

A11.22

Cycle

7 Slave disable lag time 15.0 — ns A11.27

8 Sequential Transfer delay 1 — IP-Bus

Cycle

9 Clock falling time — 7.9 ns A11.29

10 Clock rising time — 7.9 ns A11.30

1 Inter Peripheral Clock is defined in the MPC5200 User Manual [1].

NOTE:

Output timing was specified at a nominal 50 pF load.

MOTOROLA MPC5200 Hardware Specifications 4 5

A11.28

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Electrical and Thermal Characteristics

SCK

(CLKPOL=0)

Output

SCK

(CLKPOL=1)

Output

MOSI

nc...

Output

MISO

Input

cale Semiconductor,

Frees

Figure 33 Timing Diagram — SPI Master Mode, Format 1 (CPHA = 1)

Table 38 Timing Specifications — SPI Slave Mode, Format 1 (CPHA = 1)

Sym Description Min Max Units SpecID

1 Cycle time 4 1024 IP-Bus

Cycle

2 Clock high or low time 2 512 IP-Bus

Cycle

3 Slave select clock delay 15.0 — ns A11.33

4 Output data valid — 50.0 ns A11.34

5 Input Data setup time 50.0 — ns A11.35

6 Input Data hold time 0.0 — ns A11.36

7 Slave disable lag time 15.0 — ns A11.37

8 Sequential Transfer delay 1 — IP-Bus

Cycle

1 Inter Peripheral Clock is defined in the MPC5200 User Manual [1].

NOTE:

Output timing was specified at a nominal 50 pF load.

A11.31

A11.32

A11.38

46 MPC5200 Hardware Specifications M O T O R O L A

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SCK

(CLKPOL=0)

Input

SCK

(CLKPOL=1)

Input

Freescale Semiconductor, Inc.

Electrical and Thermal Characteristics

MOSI

nc...

Input

MISO

Output

Figure 34 Timing Diagram — SPI Slave Mode, Format 1 (CPHA = 1)

cale Semiconductor,

Frees

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Electrical and Thermal Characteristics

3.3.12 MSCAN

The CAN functions are available as RX and TX pins at normal IO pads (I2C1+GPTimer or PSC2). There is no filter for the WakeUp dominant pulse. Any High-to-Low edge can cause WakeUp, if configured.

3.3.13 I2C

Table 39 I2C Input Timing Specifications—SCL and SDA

Sym Description Min Max Units SpecID

nc...

cale Semiconductor,

Frees

1 Start condition hold time 2 — IP-Bus

Cycle

2 Clock low period 8 — IP-Bus

Cycle

4 Data hold time 0.0 — ns A13.3

6 Clock high time 4 — IP-Bus

Cycle

7 Data setup time 0.0 — ns A13.5

8 Start condition setup time (for repeated start con-

dition only )

9 Stop condition setup time 2 — IP-Bus

1 Inter Peripheral Clock is defined in the MPC5200 User Manual [1].

2—IP-Bus

Cycle

A13.1

A13.2

A13.4

A13.6

A13.7

Table 40 I2C Output Timing Specifications—SCL and SDA

Sym Description Min Max Units SpecID

Start condition hold time 6 — IP-Bus

Cycle

Clock low period 10 — IP-Bus

Cycle

SCL/SDA rise time — 7.9 ns A13.10

Data hold time 7 — IP-Bus

Cycle

SCL/ SDA fall time — 7.9 ns A13.12

Clock high time 10 — IP-Bus

Cycle

Data setup time 2 — IP-Bus

Cycle

Start condition setup time (for repeated start con-

dition only )

Stop condition setup time 10 — IP-Bus

20 — IP-Bus

Cycle

A13.8

A13.9

A13.11

A13.13

A13.14

A13.15

A13.16

48 MPC5200 Hardware Specifications M O T O R O L A

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1 Programming IFDR with the maximum frequency ( IFDR=0x20 ) results in the minimum output timings listed. The I2C

interface is designed to scale the data transition time, moving it to the middle of the SCL low period. The actual position is affected by the prescale and division values programmed in IFDR.

2 Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time SCL

or SDA takes to reach a high level depends on external signal capacitance and pull-up resistor values

3 Inter Peripheral Clock is defined in the MPC5200 User Manual [1].

Output timing was specified at a nominal 50 pF load.

Electrical and Thermal Characteristics

NOTE:

nc...

cale Semiconductor,

Frees

SCL

SDA

Figure 35 Timing Diagram—I2C Input/Output

3.3.14 J1850

See the MPC5200 User Manual [1].

3.3.15 PSC

3.3.15.1 Codec Mode (8,16,24 and 32-bit) / I2S Mode

Table 41 Timing Specifications—8,16, 24 and 32-bit CODEC / I2S Master Mode

Sym Description Min Typ Max Units SpecID

1 Bit Clock cycle time, programmed in CCS register 40.0 — — ns A15.1

2 Clock pulse width — 50 —

3 Bit Clock fall time — — 7.9 ns A15.3

4 Bit Clock rise time — — 7.9 ns A15.4

5 FrameSync valid after clock edge — — 8.4 ns A15.5

6 FrameSync invalid after clock edge — — 8.4 ns A15.6

A15.2

7 Output Data valid after clock edge — — 9.3 ns A15.7

8 Input Data setup time 6.0 — — ns A15.8

1 Bit Clock cycle time

NOTE:

Output timing was specified at a nominal 50 pF load.

MOTOROLA MPC5200 Hardware Specifications 4 9

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Electrical and Thermal Characteristics

BitClk

(CLKPOL=0)

Output

BitClk

(CLKPOL=1)

Output

Frame

(SyncPol = 1)

Output

Frame

(SyncPol = 0)

nc...

Output

cale Semiconductor,

Frees

TxD

Output

RxD

Input

Figure 36 Timing Diagram — 8,16, 24, and 32-bit CODEC / I2S Master Mode

Table 42 Timing Specifications — 8,16, 24, and 32-bit CODEC / I2S Slave Mode

Sym Description Min Typ Max Units SpecID

1 Bit Clock cycle time 40.0 — — ns A15.9

2 Clock pulse width — 50 —

3 FrameSync setup time 1.0 — — ns A15.11

4 Output Data valid after clock edge — — 14.0 ns A15.12

5 Input Data setup time 1.0 — — ns A15.13

6 Input Data hold time 1.0 — — ns A15.14

1 Bit Clock cycle time

A15.10

NOTE:

Output timing was specified at a nominal 50 pF load.

50 MPC5200 Hardware Specifications M O T O R O L A

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BitClk

(CLKPOL=0)

Input

BitClk

(CLKPOL=1)

Input

Frame

(SyncPol = 1)

(SyncPol = 0)

nc...

Input

Frame

Input

Electrical and Thermal Characteristics

cale Semiconductor,

Frees

TxD

Output

RxD

Input

Figure 37 Timing Diagram — 8,16, 24, and 32-bit CODEC / I2S Slave Mode

3.3.15.2 AC97 Mode

Table 43 Timing Specifications — AC97 Mode

Sym Description Min Typ Max Units SpecID

1 Bit Clock cycle time — 81.4 — ns A15.15

2 Clock pulse high time — 40.7 — ns A15.16

3 Clock pulse low time — 40.7 — ns A15.17

4 Frame valid after rising clock edge — — 13.0 ns A15.18

5 Output Data valid after rising clock edge — — 14.0 ns A15.19

6 Input Data setup time 1.0 — — ns A15.20

7 Input Data hold time 1.0 — — ns A15.21

NOTE:

Output timing was specified at a nominal 50 pF load.

MOTOROLA MPC5200 Hardware Specifications 5 1

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Electrical and Thermal Characteristics

BitClk

(CLKPOL=0)

Input

Sync

(SyncPol = 1)

Output

Sdata_out

Output

nc...

cale Semiconductor,

Frees

Sdata_in

Input

Figure 38 Timing Diagram — AC97 Mode

3.3.15.3 IrDA Mode

Table 44 Timing Specifications — IrDA Transmit Line

Sym Description Min Max Units SpecID

1 Pulse high time, defined in the IrDA protocol definition 0.125 10000 µsA15.22 2 Pulse low time, defined in the IrDA protocol definition 0.125 10000 µsA15.23

3 Transmitter rising time — 7.9 ns A15.24

4 Transmitter falling time — 7.9 ns A15.25

Output timing was specified at a nominal 50 pF load.

bcfb

NOTE:

IrDA_TX

(SIR / FIR / MIR)

Figure 39 Timing Diagram — IrDA Transmit Line

52 MPC5200 Hardware Specifications M O T O R O L A

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3.3.15.4 SPI Mode

Table 45 Timing Specifications — SPI Master Mode, Format 0 (CPHA = 0)

Sym Description Min Max Units SpecID

1 SCK cycle time, programable in the PSC CCS register 30.0 — ns A15.26

2 SCK pulse width, 50% SCK cycle time 15.0 — ns A15.27

Electrical and Thermal Characteristics

nc...

cale Semiconductor,

Frees

3 Slave select clock delay, programable in the PSC CCS

4 Output Data valid after Slave Select (SS

5 Output Data valid after SCK — 8.9 ns A15.30

6 Input Data setup time 6.0 — ns A15.31

7 Input Data hold time 1.0 — ns A15.32

8 Slave disable lag time — 8.9 ns A15.33

9 Sequential Transfer delay, programable in the PSC

CTUR / CTLR register

10 Clock falling time — 7.9 ns A15.35

11 Clock rising time — 7.9 ns A15.36

Output timing was specified at a nominal 50 pF load.

SCK

(CLKPOL=0)

Output

SCK

(CLKPOL=1)

Output

) — 8.9 ns A15.29

NOTE:

30.0 — ns A15.28

15.0 — ns A15.34

MOSI

Output

MISO

Input

Figure 40 Timing Diagram — SPI Master Mode, Format 0 (CPHA = 0)

MOTOROLA MPC5200 Hardware Specifications 5 3

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Electrical and Thermal Characteristics

Table 46 Timing Specifications — SPI Slave Mode, Format 0 (CPHA = 0)

Sym Description Min Max Units SpecID

1 SCK cycle time, programable in the PSC CCS register 30.0 — ns A15.37

2 SCK pulse width, 50% SCK cycle time 15.0 — ns A15.38

3 Slave select clock delay 1.0 — ns A15.39

4 Input Data setup time 1.0 — ns A15.40

5 Input Data hold time 1.0 — ns A15.41

nc...

cale Semiconductor,

Frees

6 Output data valid after SS

7 Output data valid after SCK — 14.0 ns A15.43

8 Slave disable lag time 0.0 — ns A15.44

9 Minimum Sequential Transfer delay = 2 * IP Bus clock

cycle time

NOTE:

Output timing was specified at a nominal 50 pF load.

SCK

(CLKPOL=0)

Input

SCK

(CLKPOL=1)

Input

MOSI

Input

— 14.0 ns A15.42

30.0 — — A15.45

MISO

Output

Figure 41 Timing Diagram — SPI Slave Mode, Format 0 (CPHA = 0)

54 MPC5200 Hardware Specifications M O T O R O L A

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Table 47 Timing Specifications — SPI Master Mode, Format 1 (CPHA = 1)

Sym Description Min Max Units SpecID

1 SCK cycle time, programable in the PSC CCS register 30.0 — ns A15.46

2 SCK pulse width, 50% SCK cycle time 15.0 — ns A15.47

Electrical and Thermal Characteristics

3 Slave select clock delay, programable in the PSC CCS

4 Output data valid — 8.9 ns A15.49

5 Input Data setup time 6.0 — ns A15.50

6 Input Data hold time 1.0 — ns A15.51

7 Slave disable lag time — 8.9 ns A15.52

8 Sequential Transfer delay, programable in the PSC

CTUR / CTLR register

nc...

cale Semiconductor,

9 Clock falling time — 7.9 ns A15.54

10 Clock rising time — 7.9 ns A15.55

NOTE:

Output timing was specified at a nominal 50 pF load.

SCK

(CLKPOL=0)

Output

SCK

(CLKPOL=1)

Output

30.0 — ns A15.48

15.0 — ns A15.53

Frees

MOSI

Output

MISO

Input

Figure 42 Timing Diagram — SPI Master Mode, Format 1 (CPHA = 1)

MOTOROLA MPC5200 Hardware Specifications 5 5

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Electrical and Thermal Characteristics

Table 48 Timing Specifications — SPI Slave Mode, Format 1 (CPHA = 1)

Sym Description Min Max Units SpecID

1 SCK cycle time, programable in the PSC CCS register 30.0 — ns A15.56

2 SCK pulse width, 50% SCK cycle time 15.0 — ns A15.57

3 Slave select clock delay 0.0 — ns A15.58

4 Output data valid — 14.0 ns A15.59

5 Input Data setup time 2.0 — ns A15.60

6 Input Data hold time 1.0 — ns A15.61

7 Slave disable lag time 0.0 — ns A15.62

nc...

cale Semiconductor,

Frees

8 Minimum Sequential Transfer delay = 2 * IP-Bus clock

cycle time

NOTE:

Output timing was specified at a nominal 50 pF load.

SCK

(CLKPOL=0)

Input

SCK

(CLKPOL=1)

Input

MOSI

Input

30.0 — ns A15.63

MISO

Output

Figure 43 Timing Diagram — SPI Slave Mode, Format 1 (CPHA = 1)

56 MPC5200 Hardware Specifications M O T O R O L A

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Electrical and Thermal Characteristics

3.3.16 GPIOs and Timers

3.3.16.1 General and Asynchronous Signals

The MPC5200 contains several sets if I/Os that do not require special setup, hold, or valid requirements. Most of these are asynchronous to the system clock. The following numbers are provided for test and validation purposes only, and they assume a 133 MHz internal bus frequency.

Figure 44 shows the GPIO Timing Diagram. Table 49 gives the timing specifications.

Table 49 Asynchronous Signals

Sym Description Min Max Units SpecID

nc...

cale Semiconductor,

Clock Period 7.52 — ns A16.1

Input Setup for Async Signal 12 — ns A16.2

Input Hold for Async Signals 1 — ns A16.3

Output Valid — 15.33 ns A16.4

Output Hold 1 — ns A16.5

Output

Input

valid

Frees

Figure 44 Timing Diagram—Asynchronous Signals

3.3.17 IEEE 1149.1 (JTAG) AC Specifications

Table 50 JTAG Timing Specification

Sym Characteristic Min Max Unit SpecID

— TCK frequency of operation. 0 25 MHz A17.1

1 TCK cycle time. 40 — ns A17.2

2 TCK clock pulse width measured at 1.5V. 1.08 — ns A17.3

3 TCK rise and fall times. 0 3 ns A17.4

MOTOROLA MPC5200 Hardware Specifications 5 7

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Electrical and Thermal Characteristics

Table 50 JTAG Timing Specification (continued)

Sym Characteristic Min Max Unit SpecID

4TRST setup time to tck falling edge 1.10—nsA17.5

5TRST

6 Input data setup time

7 Input data hold time

8 TCK to output data valid

9 TCK to output high impedance

10 TMS, TDI data setup time. 5 — ns A17.11

11 TMS, TDI data hold time. 1 — ns A17.12

12 TCK to TDO data valid. 0 15 ns A17.13

nc...

13 TCK to TDO high impedance. 0 15 ns A17.14

1TRST is an asynchronous signal. The setup time is for test purposes only. 2 Non-test, other than TDI and TMS, signal input timing with respect to TCK. 3 Non-test, other than TDO, signal output timing with respect to TCK.

cale Semiconductor,

assert time. 5 — ns A17.6

.5—nsA17.7

.15—nsA17.8

. 0 30 ns A17.9

. 0 30 ns A17.10

TCK

Figure 45 Timing Diagram—JTAG Clock Input

VM = Midpoint Voltage

Numbers shown reference Table 50.

VMVM VM

Frees

TCK

TRST

Numbers shown reference Table 50.

Figure 46 Timing Diagram—JTAG TRST

58 MPC5200 Hardware Specifications M O T O R O L A

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TCK

Freescale Semiconductor, Inc.

Electrical and Thermal Characteristics

nc...

cale Semiconductor,

Frees

DATA INPUTS

DATA OUTPUTS

TCK

TDI, TMS

TDO

INPUT DATA VALID

OUTPUT DATA VALID

Numbers shown reference Table 50.

Figure 47 Timing Diagram—JTAG Boundary Scan

INPUT DATA VALID

OUTPUT DATA VALID

Numbers shown reference Table 50.

Figure 48 Timing Diagram—Test Access Port

MOTOROLA MPC5200 Hardware Specifications 5 9

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Package Description

Freescale Semiconductor, Inc.

4 Package Description

4.1 Package Parameters

The MPC5200 uses a 27 mm x 27 mm TE-PBGA package. The package parameters are as provided in the following list:

• Package outline27 mm x 27 mm

• Interconnects272

• Pitch1.27 mm

4.2 Mechanical Dimensions

Figure 49 provides the mechanical dimensions, top surface, side profile, and pinout for the MPC5200, 272

TE-PBGA package.

nc...

cale Semiconductor,

Frees

60 MPC5200 Hardware Specifications M O T O R O L A

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Package Description

PIN A1 INDEX

0.2

nc...

(E1)

cale Semiconductor,

19X

123 54 678910111213141516171819

TOP VIEW

(D1)

19X

BOTTOM VIEW

272X

0.2

0.3

0.15

M M

0.35

SIDE VIEW

A A

NOTES:

1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994.

2. DIMENSIONS IN MILLIMETERS.

3. DIMENSION IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER PARALLEL TO PRIMARY DATUM A.

4. PRIMARY DATUM A AND THE SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS.

MILLIMETERS

DIM MIN MAX

A 2.05 2.65 A1 0.50 0.70 A2 0.50 0.70 A3 1.05 1.25

b 0.60 0.90

D 27.00 BSC D1 24.13 REF D2 23.30 24.70

E 27.00 BSC E1 24.13 REF E2 23.30 24.70

e 1.27 BSC

0.2

V U T R P N M L K J H G F E D C B A

272X

Frees

CASE 1135A–01

ISSUE B

DATE 10/15/1997

Figure 49 Mechanical Dimensions and Pinout Assignments for the MPC5200, 272

TE-PBGA

MOTOROLA MPC5200 Hardware Specifications 6 1

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Package Description

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5.3 Pinout Listings

See details in the MPC5200 User Manual [1].

Table 51 MPC5200 Pinout Listing

Name Alias Type

MEM_CAS CAS I/O VDD_MEM_IO DRV16_MEM TTL

MEM_CLK_EN CLK_EN I/O VDD_MEM_IO DRV16_MEM TTL

MEM_CS

MEM_DQM[3:0] DQM I/O VDD_MEM_IO DRV16_MEM TTL

nc...

MEM_MA[12:0] MA I/O VDD_MEM_IO DRV16_MEM TTL

MEM_MBA[1:0] MBA I/O VDD_MEM_IO DRV16_MEM TTL

MEM_MDQS[3:0] MDQS I/O VDD_MEM_IO DRV16_MEM TTL

MEM_MDQ[31:0] MDQ I/O VDD_MEM_IO DRV16_MEM TTL

MEM_CLK I/O VDD_MEM_IO DRV16_MEM TTL

MEM_CLK

MEM_RAS

MEM_WE

EXT_AD[31:0] I/O VDD_IO PCI PCI

PCI_CBE_0

RAS I/O VDD_MEM_IO DRV16_MEM TTL

I/O VDD_MEM_IO DRV16_MEM TTL

I/O VDD_IO PCI PCI

Power

Supply

SDRAM

PCI

cale Semiconductor,

PCI_CBE_1

PCI_CBE_2

I/O VDD_IO PCI PCI

Output

Driver Type

Input Type

Pull-up/

down

Frees

PCI_CBE_3

PCI_CLOCK I/O VDD_IO PCI PCI

PCI_DEVSEL

PCI_FRAME

PCI_GNT

PCI_IDSEL I/O VDD_IO DRV8 TTL

PCI_IRDY

PCI_PAR I/O VDD_IO PCI PCI

62 MPC5200 Hardware Specifications M O T O R O L A

I/O VDD_IO PCI PCI

I/O VDD_IO DRV8 TTL

I/O VDD_IO PCI PCI

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Table 51 MPC5200 Pinout Listing (continued)

Package Description

Name Alias Type

PCI_PERR I/O VDD_IO PCI PCI

PCI_REQ

PCI_RESET

PCI_SERR

PCI_STOP

PCI_TRDY

nc...

LP_ACK I/O VDD_IO DRV8 TTL PULLUP

LP_ALE

LP_OE I/O VDD_IO DRV8 TTL

LP_RW I/O VDD_IO DRV8 TTL

LP_TS

LP_CS0

LP_CS1

LP_CS2

LP_CS3

LP_CS4

LP_CS5

I/O VDD_IO DRV8 TTL

I/O VDD_IO PCI PCI

I/O VDD_IO DRV8 TTL

Power

Supply

Local Plus

cale Semiconductor,

ATA

ATA_DACK I/O VDD_IO DRV8 TTL

Output

Driver Type

Input Type

Pull-up/

down

Frees

ATA_DRQ I/O VDD_IO DRV8 TTL PULLDOWN

ATA_INTRQ I/O VDD_IO DRV8 TTL PULLDOWN

ATA_IOCHRDY I/O VDD_IO DRV8 TTL PULLUP

ATA_IOR

ATA_IOW

ATA_ISOLATION I/O VDD_IO DRV8 TTL

ETH_0 TX, TX_EN I/O VDD_IO DRV4 TTL

MOTOROLA MPC5200 Hardware Specifications 6 3

I/O VDD_IO DRV8 TTL

Ethernet

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Table 51 MPC5200 Pinout Listing (continued)

nc...

cale Semiconductor,

Frees

Name Alias Type

ETH_1 RTS, TXD[0] I/O VDD_IO DRV4 TTL

ETH_2 USB_TXP, TX,

TXD[1]

ETH_3 USB_PRTPWR,

TXD[2]

ETH_4 USB_SPEED,

TXD[3]

ETH_5 USB_SUPEND,

TX_ER

ETH_6 USB_OE, RTS,

MDC

ETH_7 TXN, MDIO I/O VDD_IO DRV4 TTL

ETH_8 RX_DV I/O VDD_IO DRV4 TTL

ETH_9 CD, RX_CLK I/O VDD_IO DRV4 Schmitt

ETH_10 CTS, COL I/O VDD_IO DRV4 TTL

ETH_11 TX_CLK I/O VDD_IO DRV4 Schmitt

ETH_12 RXD[0] I/O VDD_IO DRV4 TTL

ETH_13 USB_RXD,

CTS, RXD[1]

ETH_14 USB_RXP,

UART_RX,

RXD[2]

ETH_15 USB_RXN, RX,

RXD[3]

ETH_16 USB_OVRCNT,

CTS, RX_ER

I/O VDD_IO DRV4 TTL

Power

Supply

Output

Driver Type

Input Type

Pull-up/

down

ETH_17 CD, CRS I/O VDD_IO DRV4 TTL

IRDA

PSC6_0 IRDA_RX, TxD I/O VDD_IO DRV4 TTL

PSC6_1 RxD I/O VDD_IO DRV4 TTL

PSC6_2 Frame, CTS I/O VDD_IO DRV4 TTL

PSC6_3 IR_USB_CLK,Bi

tClk, RTS

64 MPC5200 Hardware Specifications M O T O R O L A

I/O VDD_IO DRV4 TTL

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Table 51 MPC5200 Pinout Listing (continued)

Package Description

Name Alias Type

USB_0 USB_OE I/O VDD_IO DRV4 TTL

USB_1 USB_TXN I/O VDD_IO DRV4 TTL

USB_2 USB_TXP I/O VDD_IO DRV4 TTL

USB_3 USB_RXD I/O VDD_IO DRV4 TTL

USB_4 USB_RXP I/O VDD_IO DRV4 TTL

USB_5 USB_RXN I/O VDD_IO DRV4 TTL

nc...

cale Semiconductor,

USB_6 USB_PRTPWR I/O VDD_IO DRV4 TTL

USB_7 USB_SPEED I/O VDD_IO DRV4 TTL

USB_8 USB_SUPEND I/O VDD_IO DRV4 TTL

USB_9 USB_OVRCNT I/O VDD_IO DRV4 TTL

I2C_0 SCL I/O VDD_IO DRV4 Schmitt

I2C_1 SDA I/O VDD_IO DRV4 Schmitt

I2C_2 SCL I/O VDD_IO DRV4 Schmitt

I2C_3 SDA I/O VDD_IO DRV4 Schmitt

PSC1_0 TxD, Sdata_out,

MOSI, TX

PSC1_1 RxD, Sdata_in,

MISO, TX

I/O VDD_IO DRV4 TTL

Power

Supply

USB

I2C

PSC

Output

Driver Type

Input Type

Pull-up/

down

Frees

PSC1_2 Mclk, Sync, RTS I/O VDD_IO DRV4 TTL

PSC1_3 BitClk, SCK,

CTS

PSC1_4 Frame, SS, CD I/O VDD_IO DRV4 TTL

PSC2_0 TxD, Sdata_out,

MOSI, TX

PSC2_1 RxD, Sdata_in,

MISO, TX

PSC2_2 Mclk, Sync, RTS I/O VDD_IO DRV4 TTL

MOTOROLA MPC5200 Hardware Specifications 6 5

I/O VDD_IO DRV4 TTL

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Table 51 MPC5200 Pinout Listing (continued)

nc...

cale Semiconductor,

Frees

Name Alias Type

PSC2_3 BitClk, SCK,

CTS

PSC2_4 Frame, SS, CD I/O VDD_IO DRV4 TTL

PSC3_0 USB_OE, TxDS, TXI/O VDD_IO DRV4 TTL

PSC3_1 USB_TXN, RxD, RXI/O VDD_IO DRV4 TTL

PSC3_2 USB_TXP,

BitClk, RTS

PSC3_3 USB_RXD,

Frame, SS

PSC3_4 USB_RXP, CD I/O VDD_IO DRV4 TTL

PSC3_5 USB_RXN I/O VDD_IO DRV4 TTL

PSC3_6 USB_PRTPWR,

Mclk, MOSI

PSC3_7 USB_SPEED.

PSC3_8 USB_SUPEND,

PSC3_9 USB_OVRCNT,

GPIO_WKUP_6 MEM_CS1 I/O VDD_MEM_IO DRV16_MEM TTL PULLUP_MEM

GPIO_WKUP_7 I/O VDD_IO DRV8 TTL

TIMER_0 I/O VDD_IO DRV4 TTL

TIMER_1 I/O VDD_IO DRV4 TTL

, CTS

MISO

SCK

I/O VDD_IO DRV4 TTL

Power

Supply

GPIO/TIMER

Output

Driver Type

Input Type

Pull-up/

down

TIMER_2 MOSI I/O VDD_IO DRV4 TTL

TIMER_3 MISO I/O VDD_IO DRV4 TTL

TIMER_4 SS I/O VDD_IO DRV4 TTL

TIMER_5 SCK I/O VDD_IO DRV4 TTL

TIMER_6 I/O VDD_IO DRV4 TTL

TIMER_7 I/O VDD_IO DRV4 TTL

66 MPC5200 Hardware Specifications M O T O R O L A

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Table 51 MPC5200 Pinout Listing (continued)

Package Description

Name Alias Type

SYS_XTAL_IN Input VDD_IO

SYS_XTAL_OUT Output VDD_IO

RTC_XTAL_IN Input VDD_IO

RTC_XTAL_OUT Output VDD_IO

PORRESET Input VDD_IO DRV4 Schmitt

nc...

cale Semiconductor,

HRESET

SRESET I/O VDD_IO

IRQ0 I/O VDD_IO DRV4 TTL

IRQ1 I/O VDD_IO DRV4 TTL

IRQ2 I/O VDD_IO DRV4 TTL

IRQ3 I/O VDD_IO DRV4 TTL

SYS_PLL_TPA I/O VDD_IO DRV4 TTL

TEST_MODE_0 Input VDD_IO DRV4 TTL

TEST_MODE_1 Input VDD_IO DRV4 TTL

TEST_SEL_0 I/O VDD_IO DRV4 TTL PULLUP

TEST_SEL_1 I/O VDD_IO DRV8 TTL

JTAG_TCK TCK Input VDD_IO DRV4 TTL PULLUP

I/O VDD_IO

Test/Configuration

Power

Supply

Clock

Misc

Output

Driver Type

DRV8_OD

Input Type

Schmitt

Pull-up/

down

Frees

JTAG_TDI TDI Input VDD_IO DRV4 TTL PULLUP

JTAG_TDO TDO I/O VDD_IO DRV8 TTL

JTAG_TMS TMS Input VDD_IO DRV4 TTL PULLUP

JTAG_TRST

VDD_IO -

VDD_MEM_IO -

MOTOROLA MPC5200 Hardware Specifications 6 7

TRST Input VDD_IO DRV4 TTL PULLUP

Power and Ground

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Package Description

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Table 51 MPC5200 Pinout Listing (continued)

Name Alias Type

VDD_CORE -

VSS_IO/CORE -

SYS_PLL_AVDD -

CORE_PLL_AVDD -

1 All “open drain” outputs of the MPC5200 are actually regular three-state output drivers with the output data tied low

and the output enable controlled. Thus, unlike a true open drain, there is a current path from the external system to the MPC5200 I/O power rail if the external signal is driven above the MPC5200 I/O power rail voltage.

nc...

Power

Supply

cale Semiconductor,

Output

Driver Type

Input Type

Pull-up/

down

Frees

68 MPC5200 Hardware Specifications M O T O R O L A

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System Design Information

6 System Design Information

6.1 Power UP/Down Sequencing

Figure 50 shows situations in sequencing the I/O VDD (VDD_IO), Memory VDD (VDD_IO_MEM), PLL

VDD (PLL_AVDD), and Core VDD (VDD_CORE).

nc...

cale Semiconductor,

Frees

3.3V

2.5V

1.5V

DC Power Supply Voltage

Note:

1. VDD_CORE should not exceed VDD_IO, VDD_IO_MEM or PLL_AVDD by more than 0.4 V at any time, including power-up.

2. It is recommended that VDD_CORE/PLL_AVDD should track VDD_IO/VDD_IO_MEM up to 0.9 V then separate for completion of ramps.

3. Input voltage must not be greater than the supply voltage (VDD_IO, VDD_IO_MEM, VDD_CORE, or PLL_AVDD) by more than 0.5 V at any time, including during power-up.

4. Use 1 microsecond or slower rise time for all supplies.

Figure 50 Supply Voltage Sequencing

The relationship between VDD_IO_MEM and VDD_IO is non-critical during power-up and power-down sequences. Both VDD_IO_MEM (2.5 V or 3.3 V) and VDD_IO are specified relative to VDD_CORE.

VDD_IO, VDD_IO_MEM (SDR)

VDD_IO_MEM (DDR)

VDD_CORE, PLL_AVDD

Time

6.1.1 Power Up Sequence

If VDD_IO/VDD_IO_MEM are powered up with the VDD_CORE at 0V, the sense circuits in the I/O pads will cause all pad output drivers connected to the VDD_IO/VDD_IO_MEM to be in a high-impedance state. There is no limit to how long after VDD_IO/VDD_IO_MEM powers up before VDD_CORE must power up. VDD_CORE should not lead the VDD_IO, VDD_IO_MEM or PLL_AVDD by more than 0.4 V during power ramp up or there will be high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than 1 microsecond to avoid turning on the internal ESD protection clamp diodes.

The recommended power up sequence is as follows:

Use one microsecond or slower rise time for all supplies.

MOTOROLA MPC5200 Hardware Specifications 6 9

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System Design Information

VDD_CORE/PLL_AVDD and VDD_IO/VDD_IO_MEM should track up to 0.9 V and then separate for the completion of ramps with VDD_IO/VDD_IO_MEM going to the higher external voltages. One way to accomplish this is to use a low drop-out voltage regulator.

6.1.2 Power Down Sequence

If VDD_CORE/PLL_AVDD are powered down first, then sense circuits in the I/O pads will cause all output drivers to be in a high impedance state. There is no limit on how long after VDD_CORE and PLL_AVDD power down before VDD_IO or VDD_IO_MEM must power down. VDD_CORE should not lag VDD_IO, VDD_IO_MEM, or PLL_AVDD going low by more than 0.4V during power down or there will be undesired high current in the ESD protection diodes. There are no requirements for the fall times of the power supplies.

The recommended power down sequence is as follows:

Drop VDD_CORE/PLL_AVDD to 0V.

Drop VDD_IO/VDD_IO_MEM supplies.

nc...

6.2 System and CPU Core AVDD power supply filtering

Each of the independent PLL power supplies require filtering external to the device. The following drawing is a recommendation for the required filter circuit.

cale Semiconductor,

Frees

< 1 Ω

AVDD device pinPower

200-400 pF

Supply source

10 Ω

10 µF

Figure 51 Power Supply Filtering

6.3 Pull-up/Pull-down Resistor Requirements

The MPC5200 requires external pull-up or pull-down resistors on certain pins.

6.3.1 Pull-down Resistor Requirements for TEST pins

The MPC5200 requires pull-down resistors on the test pins TEST_MODE_0, TEST_MODE_1, TEST_SEL_1.

6.3.2 Pull-up Requirements for the PCI Control Lines

If the PCI interface is NOT used (and internally disabled) the PCI control pins must be terminated as indicated by the PCI Local Bus specification [4]. This is also required for MOST/Graphics and Large Flash Mode.

PCI control signals always require pull-up resistors on the motherboard (not the expansion board) to ensure that they contain stable values when no agent is actively driving the bus. This includes PCI_FRAME, PCI_TRDY, PCI_IRDY, PCI_DEVSEL, PCI_STOP, PCI_SERR, PCI_PERR, and PCI_REQ.

70 MPC5200 Hardware Specifications M O T O R O L A

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System Design Information

6.3.3 Pull-up/Pull-down Requirements for MEM_MDQS pins (SDRAM)

The MEM_MDQS[3:0] signals are not used with SDR memories and require pull-up or pull-down resistors in SDRAM mode.

6.4 Information about JTAG_TRST

Boundary scan testing is enabled through the JTAG interface signals. The JTAG_TRST signal is optional in the IEEE 1149.1 specification but is provided on all processors that implement the PowerPC architecture. To obtain a reliable power-on reset performance, the JTAG_TRST signal must be asserted during power-on reset.

6.4.1 JTAG_TRST and PORRESET

The JTAG interface can control the direction of the MPC5200 I/O pads via the boundary scan chain. The JTAG module must be reset before the MPC5200 comes out of power-on reset; do this by asserting JTAG_TRST before PORRESET is released.

For more details refer to the Reset and JTAG Timing Specification.

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PORRESET

required assertion of JTAG_TRST optional assertion of JTAG_TRST

JTAG_TRST

Figure 52 PORRESET vs. JTAG_TRST

6.5 Connecting JTAG_TRST

The wiring of the JTAG_TRST is dependent of the existence of a board-related debug interface.

Normally this interface is implemented, using a COP (common on-chip processor) connector. The COP allows a remote computer system (typically, a PC with dedicated hardware and debugging software) to access and control the internal operations of the MPC5200. The COP port requires the ability to independently assert HRESET

There are two possibilities to connect the JTAG interface: using it with a COP connector and without a COP connector.

6.5.1 Boards interfacing the JTAG port via a COP connector

For a board with a COP (common on-chip processor) connector, which accesses the JTAG interface and which needs to reset the JTAG module, simply wiring TRST and PORRESET

and JTAG_TRST in order to fully control the processor.

is not recommended.

To reset the MPC5200 via the COP connector, the HRESET HRESET

The circuitry shown in Figure 53 allows the COP to assert HRESET other board sources can drive PORRESET

MOTOROLA MPC5200 Hardware Specifications 7 1

pin of the MPC5200.

pin of the COP should be connected to the

or JTAG_TRST separately, while any

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System Design Information

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PORRESET

COP Header

COP Connector Physical Pinout

K16Key

Key 14

HRESET

SRESET

TRST

TMS

TCK

TDI

CKSTP_OUT

TDO

halted

qack

10Kohm

10Kohm 10Kohm

10Kohm

VDD

10Kohm

PORRESET

HRESET

VDD

SRESET

VDD

JTAG_TRST

VDD

JTAG_TMS

VDD

JTAG_TCK

VDD

JTAG_TDI

TEST_SEL_0

JTAG_TDO

MPC5200

Figure 53 COP Connector Diagram

6.5.2 Boards without COP connector

If the JTAG interface is not used, JTAG_TRST should be tied to PORRESET, so that it is asserted when the system reset signal (PORRESET during power on. Figure 54 shows the connection of the JTAG interface without COP connector.

) is asserted. This ensures that the JTAG scan chain is initialized

72 MPC5200 Hardware Specifications M O T O R O L A

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System Design Information

PORRESET

HRESET

SRESET

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Figure 54 JTAG_TRST wiring for boards without COP connector

10Kohm

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PORRESET

HRESET

VDD

SRESET

JTAG_TRST

VDD

JTAG_TMS

VDD

JTAG_TCK

VDD

JTAG_TDI

TEST_SEL_0

JTAG_TDO

MPC5200

Frees

MOTOROLA MPC5200 Hardware Specifications 7 3

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Ordering Information

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7 Ordering Information

Table 52 Ordering Information

Part Number Speed Ambient Temp Qualification

MPC5200BV400 400 0C to 70C Commercial

MPC5200CBV266 266 -40C to 85C Industrial

MPC5200CBV400 400 -40C to 85C Industrial

SPC5200CBV400 400 -40C to 85C Automotive - AEC

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74 MPC5200 Hardware Specifications M O T O R O L A

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8 Document Revision History

Ta ble 5 3 provides a revision history for this hardware specification.

Table 53 Document Revision History

Document Revision History

Rev.

No.

0.1 First Preliminary release with some TBD’s in spec tables (6/2003)

0.2 Added AC specs for missing modules, power-on sequence, misc other updates (7/2003)

0.2.1 Corrected maximum core operating frequency (7/2003)

0.3 Added Memory Interface Timing values, misc other updates (8/2003)

1.0 Added Information about JTAG_TRST (11/2003)

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2.0 Added Power Numbers (Section 3.1.5), updated Oscillator and PLL Characteristics (Section

3.2), updated SDRAM AC Characteristics (Section 3.3.5)

Substantive Change(s)

For more detailed information, refer to the following documentation:

[1] MPC5200 User Manual MPC5200UM

[2] PowerPC Microprocessor Family: The Programming Environments for 32-bit Microprocessors,

Rev. 2: MPCFPE32B/AD

[3] G2 Core Reference Manual, Rev. 0: G2CORERM/D

[4] PCI Local Bus Specification, Revision 2.2, December 18, 1998

[5] ANSI ATA-4 Specification

[6] IEEE 802.3 Specification (ETHERNET)

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HOW TO REACH US:

USA/EUROPE/LOCATIONS NOT LISTED:

Motorola Literature Distribution P.O. Box 5405 Denver, Colorado 80217 1-800-521-6274 or 480-768-2130

JAPAN:

Motorola Japan Ltd. SPS, Technical Information Center 3-20-1, Minami-Azabu, Minato-ku Tokyo 106-8573, Japan 81-3-3440-3569

ASIA/PACIFIC:

Motorola Semiconductors H.K. Ltd. Silicon Harbour Centre 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong 852-26668334

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MOTOROLA MPC5200, MPC5200D Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual