Motorola MPC2605ZP66, MPC2605ZP66R Datasheet

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SEMICONDUCTOR TECHNICAL DATA

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Integrated Secondary Cache for PowerPC Microprocessors

The MPC2605 is a single chip, 256KB integrated look–aside cache with copy–back capability designed for PowerPC applications (MPC603 and MPC604). Using 0.38 µm technology along with standard cell logic technology , the MPC2605 integrates data, tag, host interface, and least recently used (LRU) memory with a cache controller to provide a 256KB, 512KB, or 1 MB Level 2 cache with one, two, or four chips on a 64–bit PowerPC bus.

• Single Chip L2 Cache for PowerPC

• 66 MHz Zero Wait State Performance (2–1–1–1 Burst)

• Four–Way Set Associative Cache Design

• 32K x 72 Data Memory Array

• 8K x 18 Tag Array

• Address Parity Support

• LRU Cache Control Logic

• Copy–Back or Write–Through Modes of Operation

• Copy–Back Buffer for Improved Performance

• Single 3.3 V Power Supply

• 5 V Tolerant I/O

• One, Two, or Four Chip Cache Solution (256KB, 512KB, or 1MB)

• Single Clock Operation

• Compliant with IEEE Standard 1 149.1 Test Access Port (JTAG)

• Supports up to Four Processors in a Shared Cache Configuration

• High Board Density 25 mm 241 PBGA Package

BLOCK DIAGRAM

Order this document

by MPC2605/D

MPC2605

ZP PACKAGE

PBGA

CASE 1138–01

COPY–BACK

BUFFER

CONTROL

RD/WR

60X BUS

INTERFACE

A0 – A31

The PowerPC name is a trademark of IBM Corp., used under license therefrom.

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

REV 6 2/26/98

CONTROLLER

AND

BUS INTERFACE

2K x 8 LRU

A27, A28

RD/WR

8K x 72 x 4 DATA RAM

2K x 18 x 4

TAG RAM

WAY SELECT

COMPARE

DH0 – DH31 DL0 – DL31 DP0 – DP7

 Motorola, Inc. 1998

MOTOROLA

MPC2605

PIN ASSIGNMENT

L2 BR

ARTRY

HRESET

ABB

L2 BG

CPU3BGCFG4 L2

FDN

CPU DBG

TEA

TT1

TT4

TT3

MISS INH

CPU3

CPU2

L2 DBG

L2 CLAIM

CI AACK

CPU

DBB

TT0

TT2

CPU BG

CPU3

DBG

CPU2

DBG

CPU2

BG NC

PWRDN

TBST

CLK

DH19 DH29

DH20

DH23

DH17

DH18

DH21

DH22

DP2 DP3

DH31

DH16

8543219

DH27

DH28

DH30

DL16 DL19 DP6

DH25 DL17 DL20 DL23

DH24

DL18 DL21 V

DL22DH26

DL24

15 16

DL25

DL26

DL27

DL28

171413121110 18

DL29 DL30

DL31

DP7

AP2

AP3

AP0

FLUSH

APEN

CFG3

TSIZ1

TSIZ0

A14

A15

A18A19 A17V

A22A20 A21V

A24A25 A23V

A27A28 A26V

APE

AP1

L2 CI

GBL

TSIZ2

A13

A16

SRESET

TDI

TDO

CPU4

CFG2

L2 UPDATE

TAG CLR

TCK

TMS

TRST

CPU4

DBG

CFG0

CFG1

DP0 DH6 DL13

INH

DH7

VSSVSSVSSDH14 DH10 DL1 DL4 V

DH3

DH5

DH4

DH0 DH15 DH12 DH9 DH8 DL2 DL5 DL7 DL8 DL9 DL11DH2

SSVSSVSSVDD

DP5

TOP VIEW (X–RAY VIEW)

DL15DH1 DP1 DH13 DH11 DL0 DL3 DL6 DP4 DL10 DL12 DL14

A30A31 A29

A11A10 A12

A8A7 A9

MPC2605

MOTOROLA

PIN DESCRIPTIONS

Pin Locations Pin Name Type Description

19G, 17H – 19H, 17J – 19J,

17K – 19K, 17L – 19L,

17M – 19M, 17N – 19N,

17P – 19P, 17R – 19R,

18T, 19T, 18U, 19U,

18V, 19V, 18W

3G AACK I/O Address acknowledge input/output.

2A ABB I/O Used as an input to qualify bus grants. Driven as an output during address tenure

17C – 19C, 17D *

A0 – A31 I/O Address inputs from processor. Can also be outputs for processor snoop

addresses. A0 is the MSB. A31 is the LSB.

initiated by the MPC2605.

AP0 – AP3 I/O Address parity.

19B APE O Address parity error. When an address parity error is detected, APE will be driven

18E APEN I Address parity enable. When tied low, enables address parity bits and the

1G ARTRY I/O Address retry status I/O. Generated when a read or write snoop to a dirty

2U 2V 1V

17E

2G CI I/O Cache inhibit I/O. 3M CLK I Clock input. This must be the same as the processor clock input. 2M CPU BG I CPU bus grant input.

3E CPU2 BG I MPC2605 logically ORs this signal with CPU BG. Used in multiprocessor

1B CPU3 BG I MPC2605 logically ORs this signal with CPU BG. Used in multiprocessor

1T CPU4 BG I MPC2605 logically ORs this signal with CPU BG. Used in multiprocessor

2H CPU BR I CPU bus request input. 2D CPU2 BR I MPC2605 logically ORs this signal with CPU BR. Used in multiprocessor

2C CPU3 BR I MPC2605 logically ORs this signal with CPU BR. Used in multiprocessor

1U CPU4 BR I MPC2605 logically ORs this signal with CPU BR. Used in multiprocessor

1F CPU DBG I CPU data bus grant input from arbiter. 3D CPU2 DBG I MPC2605 logically ORs this signal with CPU DBG. Used in multiprocessor

3C CPU3 DBG I MPC2605 logically ORs this signal with CPU DBG. Used in multiprocessor

*See pin diagram (page 2) for specific pin assignment of these bus signals.

CFG0 CFG1 CFG2 CFG3 CFG4

low one clock cycle after the assertion of TS

address parity error bit.

processor cache line has occurred.

I Configuration inputs. These must be tied to either VDD or VSS.

CFG0

0 0 0 256KB 0 1 0 512KB; A26 = 0 0 1 1 512KB; A26 = 1 1 0 0 1MB; A25 – A26 = 00 1 0 1 1MB; A25 – A26 = 01 1 1 0 1MB; A25 – A26 = 10 1 1 1 1MB; A25 – A26 = 11

CFG3 Snoop Data Tenure Selector

CFG4 AACK

configuration as the second CPU BG

configuration as the third CPU BG

configuration as the fourth CPU BG

configuration as the second CPU BR

configuration as the third CPU BR

configuration as the fourth CPU BR

configuration as the second CPU DBG

configuration as the third CPU DBG

then High–Z following clock cycle.

CFG1 CFG2

0 Supports snoop data tenure 1 Does not support snoop data tenure

Driver Enable 0 Disable AACK 1 Enable AACK

driver

MOTOROLA

MPC2605

Pin Locations Pin Name

2T CPU4 DBG I MPC2605 logically ORs this signal with CPU DBG. Used in multiprocessor

11A – 13A, 15A – 18A,

11B – 17B, 11C, 12C, 10U,

11U, 10V – 12V, 14V – 17V,

11W – 17W

4A – 10A, 4B – 10B, 6C,

10C, 8U, 9U, 3V – 6V,

8V, 9V, 3W –10W *

14A, 18B, 5C, 8C,

16U, 7V , 13V, 2W

*See pin diagram (page 2) for specific pin assignment of these bus signals.

2J DBB I/O Data bus busy. Used as input when processor is master , driven as an output after

1C FDN I/O Flush done I/O used for communication between other MPC2605 devices. Must

19E GBL O Global transaction. Always negated when MPC2604 is bus master.

1J HRESET I Hard reset input from processor bus. This is an asynchronous input that must be

3A L2 BG I Bus grant input from arbiter. 1D L2 BR I/O Bus request I/O. Normally used as an output.

19D L2 CI I Secondary cache inhibit sampled, after assertion of TS. Assertion prevents

2F L2 CLAIM O L2 cache claim output. Used to claim the bus for processor initiated memory

2E L2 DBG I Data bus grant input. Comes from system arbiter, used to start data tenure for

18D L2 FLUSH I Causes cache to write back dirty lines and clears all tag valid bits.

3B L2 MISS INH I Prevents line fills on misses when asserted. 2N L2 TAG CLR I Invalidates all tags and holds cache in a reset condition. 3N L2 UPDATE

3J PWRDN I Provides low power mode. Prevents address and data transitions into the RAM

1N SRESET I Soft reset input from processor bus. 1E TA I/O Transfer acknowledge status I/O from processor bus. 3K TBST I/O Transfer burst status I/O from processor bus. Used to distinguish between

2P TCK I T est clock input for IEEE 1149.1 boundary scan (JTAG). 1P TDI I Test data input for IEEE 1 149.1 boundary scan (JTAG). 1R TDO O Test data output for IEEE 1149.1 boundary scan (JTAG). 1H TEA I Transfer error acknowledge status input from processor bus. 3P TMS I Test mode select for IEEE 1149.1 boundary scan (JTAG).

DL0 – DL31 I/O Data bus low input and output. DL0 is the MSB. DL31 is the LSB.

DH0 – DH31 I/O Data bus high input and output. DH0 is the MSB. DH31 is the LSB.

DP0 – DP7 I/O Data bus parity input and output.

INH

Type Description

configuration as the fourth CPU DBG

a qualified L2 DBG L2 mode, this pin must be tied high.

be tied together between all MPC2605 parts along with a pullup resistor.

low for at least 16 clock cycles to ensure the MPC2605 is properly reset. For proper initialization, TRST

linefill.

operations that hit the L2 cache. L2 CLAIM of CLK following TS resistor may be necessary to ensure proper system functioning.

bus operations where MPC2605 is the bus master.

I Cache disable. When asserted, the MPC2605 will not respond to signals on the

local bus and internal states do not change.

array. MPC2605 becomes active 4 µs after deassertion. Clock must be externally disabled.

burstable and non–burstable memory operations.

when MPC2605 is the bus master. Note: To operate in Fast

must be asserted before HRESET is asserted.

goes true (low) before the rising edge

true. Because this output is not always driven, a pullup

MPC2605

MOTOROLA

Pin Locations Pin Name

2R TRST I T est reset input for IEEE 1 149.1 boundary scan (JT AG). If JTAG will not be used,

3L TS I/O Transfer start I/O from processor bus (can also come from any bus master on the

17F – 19F *

1K, 2K, 1L, 2L, 1M *

3H WT I/O Write through status input from processor bus. When tied to ground, the

4C, 15C, 16C, 9D – 11D,

8H – 10H, 4J, 8J, 9J, 16J, 4K,

8K, 12K, 16K, 4L, 11L, 12L,

16L, 10M – 12M, 3T, 9T – 11T,

17T, 3U, 4U, 15U, 17U

7C, 9C, 13C, 14C, 7D, 8D, 12D, 13D, 4G, 16G – 18G,

4H, 11H, 12H, 16H, 10J – 12J,

9K – 11K, 8L – 10L, 4M, 8M, 9M, 16M, 4N, 16N, 7T, 8T, 12T, 13T, 5U – 7U, 12U – 14U

3F, 3R NC — No connection: There is no connection to the chip.

*See pin diagram (page 2) for specific pin assignment of these bus signals.

TSIZ0–TSIZ2 I/O Transfer size I/O from processor bus.

TT0–TT4 I/O Transfer type I/O from processor bus.

Type Description

TRST

should be tied low.

processor bus). Signals the start of either a processor or bus master cycle.

MPC2605 will operate in write–through mode only (no copy–back).

Supply Power supply: 3.3 V ± 5%.

Supply Ground.

ABSOLUTE MAXIMUM RATINGS (See Note 1)

Rating Symbol Value Unit

Power Supply Voltage V Voltage Relative to V Output Current (per I/O) I Power Dissipation (Note 2) P Temperature Under Bias T Operating Temperature T Storage Temperature T

NOTES:

1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.

2. Power dissipation capability is dependent upon package characteristics and use environment. See Package Thermal Characteristics.

Vin, V

out

bias

stg

out

– 0.5 to + 4.6 V

– 0.5 to VDD + 0.5 V

± 20 mA

— W

– 10 to + 85 °C

0 to + 125 °C

– 55 to + 125 °C

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high–impedance circuit.

This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established.

MOTOROLA

MPC2605

DC OPERA TING CONDITIONS AND CHARACTERISTICS

(TJ = 20 to + 1 10 °C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS

Parameter

Supply Voltage (Operating Voltage Range) V Input High Voltage V Input Low Voltage V

*VIL(min) = – 2.0 V ac (pulse width ≤ 20 ns).

(Voltages Referenced to VSS = 0 V)

Symbol Min Typ Max Unit

DC CHARACTERISTICS

Parameter Symbol Min Max Unit

Input Leakage Current (All Inputs, Vin = 0 to VDD) I Output Leakage Current (High–Z State, V AC Supply Current (I

Cycle Time = 15 ns, max value assumes a constant burst read hit, with 100% bus utilization, and 100% hit rate)

AC Quiescent Current (I Cycle Time = 15 ns, All Other Inputs DC)

Output Low Voltage (IOL = + 8.0 mA) V Output High Voltage (IOH = – 4.0 mA) V

= 0 mA, All inputs = VIL or VIH, VIL = 0 V, and VIH≥ 3.0 V,

out

= 0 mA, All inputs = VIL or VIH, VIL = 0 V and VIH ≥ 3.0 V ,

out

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T

Input Capacitance C Output Capacitance C Input/Output Capacitance C

= 0 to VDD) I

out

= 25°C, Periodically Sampled Rather Than 100% Tested)

Parameter Symbol Typ Max Unit

3.135 3.3 3.465 V

2.0 — 5.5 V

– 0.5* — 0.8 V

lkg(I)

lkg(O)

CCA

OL OH

out

I/O

— ± 1.0 µA — ± 1.0 µA — 720 mA

— 195 mA

— 0.4 V

2.4 — V

4 6 pF 6 8 pF 8 10 pF

PACKAGE THERMAL CHARACTERISTICS

Rating Symbol Max Unit

Thermal Resistance Junction to Ambient (Still Air, Test Board with Two Internal Planes) R Thermal Resistance Junction to Ambient (200 lfpm, Test Board with Two Internal Planes) R Thermal Resistance Junction to Board (Bottom) R Thermal Resistance Junction to Case (Top) R

θJA θJA θJB θJC

26.5 °C/W

23.2 °C/W

15.9 °C/W

6.6 °C/W

MPC2605

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AC OPERA TING CONDITIONS AND CHARACTERISTICS

Timing

(TJ = 20 to + 1 10 °C, Unless Otherwise Noted)

Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .

Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time 2 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output Measurement Timing Level 1.5 V. . . . . . . . . . . . . . . . . . . . . . .

Output Load 50 Ω T ermination to 1.5 V. . . . . . . . . . . . . . . . . . . . . . . .

AC CLOCK SPECIFICATIONS

Timing

Parameter

Frequency of Operation — 66.67 MHz Clock Cycle Time Clock Rise and Fall Time Clock Duty Cycle Measured at 1.5 V 40 60 % Clock Short–Term Jitter (Cycle to Cycle) — ± 150 ps 1

NOTES:

1. This parameter is sampled and not 100% tested.

2. Rise and fall times for the clock input are measured from 0.4 to 2.4 V .

Reference



, 

MPC2605–66

Min Max

15 — ns

1.0 2.0 ns 1, 2

Unit Notes

CLOCK INPUT TIMING DIAGRAM



VM = Midpoint Voltage (1.5 V)





MOTOROLA

MPC2605

AC SPECIFICATIONS

Timing

Parameter

Clock Cycle Time Input Setup Time Clock to Input Invalid (Input Hold) Clock to Output Driven Clock to Output Valid Clock to Output Invalid Clock to Output High–Z PWRDN Disable to Recovery — 4 µs 2

NOTES:

1. All input specifications are measured from the TTL level (0.8 or 2.0 V) of the signal in question to the 1.4 V level of the rising edge of the input clock. Both input and output timings are measured at the pin.

2. This parameter is sampled and not 100% tested.

CLK

INPUTS





Reference















MPC2605–66

Min Max

15 — ns

4.5 — ns 1 2 — ns 1 2 9 ns 2 2 9 ns 2 — ns 2 2 12 ns 2

Unit Notes

OUTPUTS











MPC2605

MOTOROLA

MPC2605 RESPONSE TO 60X TRANSFER ATTRIBUTES

TT0 – TT4 TBST CI WT Tag Status MPC2605 Response Notes

X1X10 0 1 X Miss Line–fill (processor read miss) 1, 2, 3 X1X10 0 1 X Hit L2 CLAIM, AACK, TA (processor read hit) 4 X1010 1 0 X Hit Clean Paradox — Invalidate the line (processor n–cacheable read hit

X1010 1 0 X Hit Dirty Paradox — ARTRY, L2 BR, then write back data, invalidate the line

00110 0 1 X Miss Line–fill except right after a snoop hit to processor (processor write

00110 0 1 1 Hit L2 CLAIM, AACK, TA except after a snoop hit to processor

00X10 X 1 0 Hit Clean Cache update (processor write through WT hit clean) 00110 0 1 0 Hit Dirty Cache update, clear dirty bit 00010 1 1 0 Hit Dirty Paradox — ARTRY, L2 BR, write back data, keep valid, clear dirty

X0010 1 0 X Hit Clean Paradox — Invalidate the line (processor n–cacheable write hit

X0010 1 0 X Hit Dirty Paradox — ARTRY, L2 BR, then write back data, invalidate the line

00100 X X X Hit Clean Invalidate tag (flush block address–only) 00100 X X X Hit Dirty ARTRY, L2 BR, write back data, invalidate tag (flush block

00000 X X X Hit Clean No action (clean block address–only) 00000 X X X Hit Dirty ARTRY, L2 BR, write back data, reset dirty bit (clean block

01100 X X X Hit Invalidate tag (kill block address–only)

NOTES:

1. If a line fill is going to replace a dirty line and the cast out buffer (COB) is full, the line fill will be cancelled. (Unless the line fill is a write which hits in the COB. In this case, the line fill will occur.)

2. If a burst read misses the cache but hits the COB, the MPC2605 will supply the data from the COB, but not perform a line fill.

3. If ARTRY dirty, tag field), and the COB goes back to an invalid condition, even if the line fill is a burst write to the line in the COB.

4. If ARTRY

5. If a processor burst write occurs right after a snoop write that was a cache hit, the MPC2605 will invalidate the line. If the snoop was a cache miss, the MPC2605 will not perform a write allocate.

6. If a processor burst write occurs right after a snoop read that was a cache hit, the MPC2605 will update the cache and clear the dirty bit. If the snoop was a cache miss, the MPC2605 will perform a write allocate.

is asserted during a line fill to replace a dirty line, the line fill will be cancelled, the to–be–replaced line will recover its old tag (valid,

is asserted during a read hit, the MPC2605 will abort the process.

clean line)

(processor n–cacheable read hit dirty line)

1, 3, 5, 6

miss)

(processor write hit)

bit

clean line)

(processor n–cacheable SB write hit dirty line)

address–only)

5, 6

MPC2605 RESPONSE TO CHIPSET TRANSFER ATTRIBUTES

TT0 – TT4 Tag Status MPC2605 Response

00100 X0010 X1110

00000 X1010

0110X 00110

NOTE: In all snoop push cases, BR is sampled the cycle after the ARTRY window. If BR is asserted in this cycle, L2 BR will be immediately negated

and an assertion of L2 BG

Hit Clean Invalidate line

Hit Dirty ARTRY and L2 BR write back data, invalidate line (see Note)

Hit Clean No action

Hit Dirty ARTRY and L2 BR, write back data, reset dirty bit (see Note)

Hit Invalidate (kill block)

will be ignored.

TRANSFER ATTRIBUTES GENERATED FOR L2 COPYBACK

TT0 – TT4 TBST CI WT

00010 0 1 1

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MPC2605

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