Motorola MPC2106SG66, MPC2107, MPC2107SG66, MPC2105SG66, MPC2106 Datasheet
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MPC2104•MPC2105•MPC2106•MPC2107
1
MOTOROLA FAST SRAM
Advance Information
256KB and 512KB BurstRAM
Secondary Cache Modules for
PowerPC PReP/CHRP Platforms
The MPC2104/5/6/7 are des igned to provide burstable, high performance L2
cache for the PowerPC 60x microprocessor family in conformance with the
PowerPC Reference Platform (PReP) and the PowerPC Common Hardware
Reference Platform (CHRP) specifications. These products utilize synchronous or
asynchronous data RAMs.
The MPC2104, MPC2105, and MPC2106 utilize synchronous BurstRAMs.
The modules are configured as 32K x 72, 64K x 72, and 128K x 72 bits in a 182
(91 x 2) pin DIMM format. The MPC2104 uses four of Motorola’s 5 V 32K x 18;
the MPC2105 uses four of the 5 V 64K x 18; the MPC2106 uses eight of the
5 V 64K x 18. For tag bits, a 5 V cache ta g RA M configured as 16K x 12 for tag field
plus 16K x 2 for valid and dirty status bits is used.
Bursts can be initiated with the ADS
signal. Subsequent burst addresses are
generated internal to the BurstRAM by the CNTEN
signal.
Write cycles are internally self timed and are initiated by the rising edge of the
clock (CLKx) inputs. Eight write enables are provided for byte write control.
The MPC2107 utilizes asynchronous data RAMs. The module is configured as
32K x 64 in the same 182 pin DIMM format. Again, 5 V cache tag RAMs configured
as 16K x 12 for tag field plus 16K x 2 for valid and dirty status bits are used. Burst
capability is provided in that two burst addresses bypass the address latch.
Presence detect pins are available for auto configuration of the cache control. A serial EEPROM is optional to provide more in–depth description of the
cache module. This EEPROM will be available on future revisions of the module
family.
The module family pinout will support 5 V and 3.3 V components for a clear
path to lower voltage and power savings. Both power supplies must be connected.
All of these cache modules are plug and pin compatible with each other.
• PowerPC–style Burst Counter on Chip (MPC2104/5/6)
• Flow–Through Data I/O (MPC2104/5/6)
• Plug and Pin Compatibility of entire Module Family
• Multiple Clock Pins for Reduced Loading
• All Cache Data and Tag I/Os are LVTTL (3.3 V) Compatible (MPC2104/5/6)
• Three State Outputs
• Byte Write Capability
• Fast Module Clock Rates: Up to 66 MHz
• Fast SRAM Access Times: 10 ns for Tag RAM Match
9 ns for Data RAM (MPC2104/5/6)
15 ns for Data RAM (MPC2107)
• Decoupling Capacitors for Each Fast Static RAM
• High Quality Multi–Layer FR4 PWB With Separate Power and Ground Planes
• 182 Pin Card Edge Module
• Burndy Connector, Part Number: ELF182JSC–3Z50
BurstRAM is a trademark of Motorola.
PowerPC is a trademark of International Business Machines Corp.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Order this document
by MPC2104/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MPC2104
MPC2105
MPC2106
MPC2107
11/8/95
Motorola, Inc. 1995
PIN ASSIGNMENT
182–LEAD DIMM
TOP VIEW – CASE TBD
V
SS
PD1/IDSDATA
PD3
DH31
DH29
DH27
DH25
VCC3
CWE3
DH23
DH21
DH18
V
SS
DH16
CWE2
DH14
DH13
VCC5
DH10
DH8
CWE1
DH6
VCC3
DH4
V
SS
CLK0
V
SS
DH1
CWE0
DL31
DL30
V
SS
DL29
DL27
DL25
VCC5
CWE7
DL23
DL21
DL19
V
SS
DL17
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
V
SS
PD0/IDSCLK
PD2
DH30
DH28
DH26
DH24
VCC3
DP3
DH22
DH20
DH19
V
SS
DH17
DP2
DH15
DH12
VCC5
DH11
DH9
DP1
DH7
VCC3
DH5
DH3
DH2
DH0
DP0
V
SS
CLK1
VSS
DL28
DL26
DL24
DP7
VCC5
DL22
DL20
DL18
DL16
V
SS
DP6
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
CWE6
DL15
DL13
V
SS
DL10
DL8
CWE5
DL6
VCC3
DL5
DL2
V
SS
CLK3
V
SS
CLK4
V
SS
CWE4
ALE
VCC3
ADDR1
RESERVED
CNTEN0
CNTEN1
VCC5
VCC5
A27
A24
A22
A20
V
SS
A18
A16
A15
A14
VCC3
A10
A8
A6
V
SS
A4
A2
A1
BURSTMODE
VCC5
VALIDIN
TWE
STANDBY
DIRTYOUT
V
SS
DL14
DL12
DL11
V
SS
DL9
DP5
DL7
DL4
VCC3
DL3
DL1
DL0
V
SS
CLK2
V
SS
DP4
COE0
COE1
VCC3
ADDR0
RESERVED
ADS0
ADS1
VCC5
VCC5
A28
A26
A25
A23
V
SS
A21
A19
A17
A13
VCC3
A12
A11
A9
V
SS
A7
A5
A3
A0
VCC5
TCLR
MATCH
TOE
DIRTYIN
V
SS
NOTES:
1. VCC5 and VCC3 must be connected on all modules.
MPC2104•MPC2105•MPC2106•MPC2107
2
MOTOROLA FAST SRAM
MPC2104•MPC2105•MPC2106•MPC2107
3
MOTOROLA FAST SRAM
MPC2104/MPC2105 BLOCK DIAGRAM
MCM67Mx18
A15
K
G
E
DQ0 – DQ8
A13
STANDBY
TSC
COE0
TSP
A14 – A26
VCC5 via 100
Ω
A2 – A14
A14 – A26
LW
BAA
ADS0
CWE0
A2 – A12
A1
TCLR
TWE
CLK2
MATCH
DIRTYOUT
VALIDIN
DIRTYIN
TOE
TAG: 16K x 12 + V + D
A13
RESET
A0 – A12
TAG
, TAD, E2
SFUNC, SG
TDQ0 – TDQ10
TDQ11
SW
TW
K
MATCH
DIRTYQ
VALIDD
DIRTYD
TG
CLK3 = NC
CLK4 = NC
ALE = NC
ADS1
= NC
CNTEN1
= NC
COE1
= NC
ADDR0 = NC
ADDR1 = NC
PD2 = NC
PD3
J0
X24C00
(OPTIONAL)
SCL
SDA
PD0/IDSCLK PD1/IDSDATA
J2
J3
DQ9 – DQ17
UW
CLK0
DH0 – DH7 + DP0
DH8 – DH15 + DP1
CWE1
CNTEN0
A1
A27
A0
A28
MCM67Mx18
A15
K
G
E
DQ0 – DQ8
TSC
TSP
A2 – A14
LW
BAA
CWE2
DQ9 – DQ17
UW
CLK0
DH16 – DH23 + DP2
DH24 – DH31 + DP3
CWE3
A1
A0
MCM67Mx18
A15
K
G
E
DQ0 – DQ8
TSC
TSP
A2 – A14
LW
BAA
CWE4
DQ9 – DQ17
UW
CLK1
DL0 – DL7 + DP4
DL8 – DL15 + DP5
CWE5
A1
A0
MCM67Mx18
A15
K
G
E
DQ0 – DQ8
TSC
TSP
A2 – A14
LW
BAA
CWE6
DQ9 – DQ17
UW
CLK1
DL16 – DL23 + DP6
DL24 – DL31 + DP7
CWE7
A1
A0
’244
TT1, WTD, E1
TAH, PWRDN
J5
V
SS
VCC5 via 100
Ω
WTQ
VALIDQ
V
CCQ
VCC3
NC
256KB 512KB EEPROM EEPROM
256KB 512KB
J5 no stuff 0
Ω
no stuff 0
Ω
J4 0
Ω
0
Ω
no stuff no stuff
J3 0
Ω
0
Ω
no stuff no stuff
J2 0
Ω
no stuff no stuff no stuff
J1 0
Ω
no stuff 0
Ω
no stuff
J0 no stuff 0
Ω
no stuff 0
Ω
J4
J1
Note: MPC2104 utilizes 32K x 18 BurstRAMs. MPC2105 utilizes 64K x 18 BurstRAMs.
NC
MPC2104•MPC2105•MPC2106•MPC2107
4
MOTOROLA FAST SRAM
MPC2106 BLOCK DIAGRAM
64K X 18 BURST
K
G
E
DQ0 – DQ8
STANDBY
TSC
COE0
A13 – A26
A0 – A15
A13 – A28
LW
BAA
ADS0
CWE0
A0 – A11
TCLR
TWE
CLK2
MATCH
DIRTYOUT
VALIDIN
DIRTYIN
TOE
TAG: 16K x 12 + V + D
A0 – A13
RESET
TAH, TAG, TAD
SFUNC, SGTDQ0 – TDQ11
SW
TW
K
MATCH
DIRTYQ
VALIDD
DIRTYD
TG
ALE = NC
ADDR0 = NC
ADDR1 = NC
PD2 = NC
PD3
X24C00
(OPTIONAL)
SCL
SDA
PD0/IDSCLK PD1/IDSDATA
J0
DQ9 – DQ17
UW
CLK0
DH0 – DH7 + DP0
DH8 – DH15 + DP1
CWE1
CNTEN0
64K X 18 BURST
K
G
E
DQ0 – DQ8TSC
A0 – A15
LW
BAA
CWE2
DQ9 – DQ17
UW
CLK1
DH16 – DH23 + DP2
DH24 – DH31 + DP3
CWE3
64K X 18 BURST
K
G
E
DQ0 – DQ8
TSC
A0 – A15
LW
BAA
CWE4
DQ9 – DQ17
UW
CLK3
DL0 – DL7 + DP4
DL8 – DL15 + DP5
CWE5
64K X 18 BURST
K
G
E
DQ0 – DQ8
TSC
A0 – A15
LW
BAA
CWE6
DQ9 – DQ17
UW
CLK4
DL16 – DL23 + DP6
DL24 – DL31 + DP7
CWE7
’244
TT1, WTD
PWRDN
V
SS
VCC5
via 100
Ω
WTQ
TA
, VALIDQ
V
CCQ
VCC3
NC
1M EEPROM 1M
J1 0
Ω
no stuff
J0 0
Ω
no stuff
A12
64K X 18 BURST
K
G
E
DQ0 – DQ8
TSC
A0 – A15
LW
BAA
CWE0
DQ9 – DQ17
UW
CLK0
DH0 – DH7 + DP0
DH8 – DH15 + DP1
CWE1
64K X 18 BURST
K
G
E
DQ0 – DQ8
TSC
A0 – A15
LW
BAA
CWE2
DQ9 – DQ17
UW
CLK1
DH16 – DH23 + DP2
DH24 – DH31 + DP3
CWE3
64K X 18 BURST
K
G
E
DQ0 – DQ8
TSC
A0 – A15
LW
BAA
CWE4
DQ9 – DQ17
UW
CLK3
DL0 – DL7 + DP4
DL8 – DL15 + DP5
CWE5
64K X 18 BURST
K
G
E
DQ0 – DQ8
TSC
A0 – A15
LW
BAA
CWE6
DQ9 – DQ17
UW
CLK4
DL16 – DL23 + DP6
DL24 – DL31 + DP7
CWE7
COE1
ADS1
CNTEN1
E2
E1
A12
V
DD
A13 – A26
A0 – A11
TCLR
TWE
CLK2
MATCH
DIRTYOUT
VALIDIN
DIRTYIN
TOE
TAG: 16K x 12 + V + D
A0 – A13
RESET
TAH, TAG, TAD
SFUNC, SGTDQ0 – TDQ11
SW
TW
K
MATCH
DIRTYQ
VALIDD
DIRTYD
TG
TT1, WTD
PWRDN
V
SS
VCC5
via 100
Ω
WTQ
TA
, VALIDQ
V
CCQ
VCC3
NC
E2
E1
V
SS
A12
Note: All 64K X 18 TSP signals are tied to VCC via a 100 Ω resistor. Edge connector A28 connects to the 64K x 18 A0; edge
connector A27 connects to the 64K x 18 A1.
J1
14
PAL
PA12
PA12L
NC
NC
MPC2104•MPC2105•MPC2106•MPC2107
5
MOTOROLA FAST SRAM
MPC2107 BLOCK DIAGRAM
MCM6206
G
E
STANDBY
A0
COE0
A14 – A26
A2 – A14
A14 – A26
W
A1
ADDR0
CWE0
A2 – A13
TCLR
TWE
CLK2
MATCH
DIRTYOUT
VALIDIN
DIRTYIN
TOE
TAG: 16K x 12 + V + D
A0 – A12
RESET
TAH, TAG, TAD
SFUNC, SGTDQ0 – TDQ11
SW
TW
K
MATCH
DIRTYQ
VALIDD
DIRTYD
TG
CLK0, 1, 3, 4 = NC
ADS0
, ADS1 = NC
CNTEN0
, CNTEN1 = NC
A27, A28 = NC
DP0 – DP7 = NC
BURSTMODE = NC
PD2
PD3 = NC
X24C00
(OPTIONAL)
SCL
SDA
PD0/IDSCLK PD1/IDSDATA
J2
DQ0 – DQ7
DH0 – DH7
ADDR1
MCM6206
MCM6206
MCM6206
’373
TT1, WTD, E1
E2, PWRDN
V
SS
VCC5
via 100
Ω
WTQ
TA
, VALIDQ
V
CCQ
VCC3
NC
256KB EEPROM 256KB
J3 0
Ω
no stuff
J2 0
Ω
no stuff
J1 0
Ω
no stuff
MCM6206
MCM6206
MCM6206
MCM6206
13
ALE
G
E
A0
A2 – A14
W
A1
CWE1
DQ0 – DQ7
DH8 – DH15
G
E
A0
A2 – A14
W
A1
CWE2
DQ0 – DQ7
DH16 – DH23
G
E
A0
A2 – A14
W
A1
CWE3
DQ0 – DQ7
DH24 – DH31
G
E
A0
A2 – A14
W
A1
CWE4
DQ0 – DQ7
DL0 – DL7
COE1
G
E
A0
A2 – A14
W
A1
CWE5
DQ0 – DQ7
DL8 – DL15
G
E
A0
A2 – A14
W
A1
CWE6
DQ0 – DQ7
DL16 – DL23
G
E
A0
A2 – A14
W
A1
CWE7
DQ0 – DQ7
DL24 – DL31
J3
V
SS
A13
J1
NC
MPC2104•MPC2105•MPC2106•MPC2107
6
MOTOROLA FAST SRAM
PIN DESCRIPTIONS
Pin Locations Symbol
Type Description
68, 69, 70, 71, 73, 74, 75, 76,
78, 79, 80, 82, 83, 84, 85,
159, 160, 161, 162, 164, 165,
166, 167, 169, 170, 171, 173,
174, 175
A0 – A28 Input Address Inputs – (MSB:0, LSB:28)
62 ADDR0 Input Least significant address bit when asynchronous Data RAMs are used.
153 ADDR1 Input Next to least significant address bit when asynchronous Data RAMs are used.
30, 56, 117, 146, 148 CLK0 – CLK4 Input Clock Inputs – CLK2 is for Tag RAM, CLK0, 1, 3, and 4 are for Data RAMs only .
For MPC2106 use all the clocks. For MPC2104 or MPC2105 use CLK0–CLK2
only. For MPC2107 use CLK2 only.
4, 5, 6, 7, 10, 11, 12, 14, 16,
17, 19, 20, 22, 24, 25, 26, 27,
95, 96, 97, 98, 101, 102, 103,
105, 107, 108, 110, 111, 113,
115, 119
DH0 – DH31 I/O High Data Bus – (MSB:0, LSB:31)
32, 33, 34, 37, 38, 39, 40, 43,
44, 45, 47, 49, 50, 52, 53, 54,
121, 122, 124, 125, 126, 129,
130, 131, 133, 135, 136, 138,
139, 141, 143, 144
DL0 – DL31 I/O Low Data Bus – (MSB:0, LSB:31)
9, 15, 21, 28, 35, 42, 48, 58 DP0 – DP7 I/O Data Parity Bits – (MSB:0, LSB:7)
3, 94 PD2, PD3 Output Presence detect bits.
2 PD0/IDSCLK Input Presence detect bit 0/EEPROM serial clock. (EEPROM option only.)
93 PD1/IDSDATA I/O Presence detect bit 1/EEPROM serial data. (EEPROM option only.)
64, 65 ADS0, ADS1 Input Data RAM Address Strobe – For MPC2104 or MPC2105 use ADS0 only. For
MPC2106 use ADS0
, ADS1.
151 ALE Input Data RAM Address Latch Enable – Use for asynchronous Data RAM only.
155, 156 CNTEN0,
CNTEN1
Input Data RAM Count Enables – For MPC2104 or MPC2105 use CNTEN0 only. For
MPC2106 use CNTEN0
, CNTEN1.
59, 60 COE0,
COE1
Input Data RAM Output Enables – For MPC2104 or MPC2105 use COE0 only. For
all others use COE0
, COE1.
100, 106, 112, 120,
128, 134, 140, 150
CWE0 – CWE7 Input Data RAM Write Enables – (MSB:0, LSB:7)
87 TCLR Input Tag RAM clear.
88 MATCH Output Tag RAM active high match indication.
178 VALIDIN Input Tag RAM valid bit.
179 TWE Input T ag RAM write enable.
89 TOE Input Tag RAM output enable.
90 DIRTYIN Input Dirty input bit.
181 DIRTYOUT Output Dirty output bit.
180 STANDBY Input Standby pin. Reduces standby power consumption.
176, 63, 154 RESERVED Reserved pin.
8, 23, 51, 61, 77, 99, 114,
142, 152, 168
VCC3 Input + 3.3 V power supply. Must be connected.
18, 36, 66, 67, 86, 109, 127,
157, 158, 177
VCC5 Input + 5 V power supply. Must be connected.
1, 13, 29, 31, 41, 46, 55, 57,
72, 81, 91, 92, 104, 116,
118, 123, 132, 137, 145,
147, 149, 163, 172, 182
V
SS
Input Ground
176 BURSTMODE Input Burstmode. 0 = Linear, 1 = Interleaved.
MPC2104•MPC2105•MPC2106•MPC2107
7
MOTOROLA FAST SRAM
DATA RAM MCM67M518, MCM67M618 SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, and 3)
STANDBY
ADS0 CNTEN0 CWEx CLKx Address Used Operation
H L X X L–H N/A Deselected
L L X L L–H External Address Write Cycle, Begin Burst
L L X H L–H External Address Read Cycle, Begin Burst
X H L L L–H Next Address Write Cycle, Continue Burst
X H L H L–H Next Address Read Cycle, Continue Burst
X H H L L–H Current Address Write Cycle, Suspend Burst
X H H H L–H Current Address Read Cycle, Suspend Burst
NOTES:
1. X means Don’t Care.
2. All inputs except COE
must meet set–up and hold times for the low–to–high transition of clock (CLK0 – CLK4).
3. Wait states are inserted by suspending burst.
ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2)
Operation
COE I/O Status
Read L Data Out (DQ0 – DQ8)
Read H High–Z
Write X High–Z — Data In
Deselected X High–Z
NOTES:
1. X means Don’t Care.
2. For a write operation following a read operation, COE
must be high before the input
data required set–up time and held high through the input data hold time.
DATA RAM MCM6206 ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2)
STANDBY
COE0, COE1 CWE0 – CWE7 Operation I/O Status
H X X Deselected High–Z
L H H Output Disabled High–Z
L L H Read Data Out
L X L Write High–Z
NOTES:
1. X means Don’t Care.
2. For a write operation following a read operation, COE0
, and COE1 must be high before the input data required set–up time, and held high
through the input data hold time.
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to V
SS
= 0 V)
Rating
Symbol Value Unit
Power Supply Voltage V
CC
– 0.5 to + 7.0 V
Voltage Relative to V
SS
Vin, V
out
– 0.5 to VCC + 0.5 V
Output Current (per I/O) Data RAM
Tag
I
out
± 30
± 20
mA
Power Dissipation P
D
8.1 W
Temperature Under Bias T
bias
– 10 to + 85 °C
Operating Temperature T
A
0 to +70 °C
Storage Temperature T
stg
– 55 to + 125 °C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high–impedance
circuit.
This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.
This device contains circuitry that will
ensure the output devices are in High–Z at
power up.
MPC2104•MPC2105•MPC2106•MPC2107
8
MOTOROLA FAST SRAM
DC OPERA TING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
(Voltages referenced to VSS = 0 V)
Parameter
Symbol Min Max Unit
Supply Voltage (Operating Voltage Range) V
CC
4.75 5.25 V
Input High Voltage V
IH
2.2 VCC + 0.3** V
Input Low Voltage V
IL
– 0.5* 0.8 V
*VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.
**VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.
DC CHARACTERISTICS
Parameter Symbol Min Max Unit
Input Leakage Current (All Inputs, Vin = 0 to VCC) Data RAM
Tag
I
lkg(I)
— ± 1.0
± 5.0
µA
Output Leakage Current (COE = VIH, V
out
= 0 to VCC) Data RAM
Tag
I
lkg(O)
— ± 1.0
± 5.0
µA
TTL Output Low Voltage (IOL = + 8.0 mA) V
OL
— 0.4 V
TTL Output High Voltage (IOH = – 4.0 mA) V
OH
2.4 — V
POWER SUPPLY CURRENTS
Parameter Symbol Max Unit
AC Supply Current (COE = VIH, E = VIL, I
out
= 0 mA, All Inputs = VIL and VIH,
VIL = 0.0 V and VIH ≥ 3.0 V, Cycle Time ≥ 20 ns) MPC2104
MPC2105
MPC2106
MPC2107
I
CCA
1480
1420
2840
1400
mA
AC Standby Current (E = VIH, I
out
= 0 mA, All Inputs = VIL or VIH,
VIL = 0.0 V and VIH ≥ 3.0 V, Cycle Time ≥ 20 ns) MPC2104
MPC2105
MPC2106
MPC2107
I
SB1
620
700
1400
960
mA
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T
A
= 25°C, Periodically Sampled Rather Than 100% Tested)
Parameter
Symbol Typ Max Unit
Input Capacitance (A13 – A28)
(Data RAM Control Pins)
(CLK0 – CLK4)
(Tag Control Pins)
C
in
—
16
8
—
15
20
10
5
pF
Tag Output Capacitance (MATCH, DIRTYOUT) C
out
— 7 pF
Data RAM Input/Output Capacitance (DH0 – DH31, DL0 – DL31) C
I/O
6 8 pF
Tag Input/Output Capacitance (A0 – A11) C
I/O
— 7 pF
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