Motorola MPC2106C, MPC2105C, MPC2105CDG66 Datasheet
MPC2105C•MPC2106C
1
MOTOROLA FAST SRAM
512KB and 1MB BurstRAM
Secondary Cache Modules for
PowerPC PReP/CHRP Platforms
The MPC2105C and the MPC2106C are designed to provide burstable, high
performance L2 cache for the PowerPC 60x microprocessor family in conformance
with the PowerPC Reference Platform (PReP) and the PowerPC Common Hardware
Reference Platform (CHRP) specifications.
The MPC2105C and MPC2106C utilize synchronous BurstRAMs. The modules
are configured as 64K x 72, and 128K x 72 bits in a 178 (89 x 2) pin DIMM format.
The MPC2105C uses four of the 3 V 64K x 18; the MPC2106C uses eight of the 3
V 64K x 18. For tag bits, a 5 V cache ta g RA M c onfigured as 16K x 12 for tag field plus
16K x 2 for valid and dirty status bits is used.
Bursts can be initiated with the ADS
signal. Subsequent burst addresses are
generated internal to the BurstRAM by the CNTEN signal.
Write cycles are internally self timed and are initiated by the rising edge of the clock
(CLKx) inputs. Eight write enables are provided for byte write control.
Presence detect pins are available for auto configuration of the cache control.
The module family pinout will support 5 V and 3.3 V components for a clear path
to lower voltage and power savings. Both power supplies must be connected.
All of these cache modules are plug and pin compatible with each other.
• PowerPC–style Burst Counter on Chip
• Flow–Through Data I/O
• Plug and Pin Compatibility
• Multiple Clock Pins for Reduced Loading
• All Cache Data and Tag I/Os are LVTTL (3.3 V) Compatible
• Three State Outputs
• Byte Write Capability
• Fast Module Clock Rates: Up to 66 MHz
• Fast SRAM Access Times: 10 ns for Tag RAM Match
9 ns for Data RAM
• Decoupling Capacitors for Each Fast Static RAM
• High Quality Multi–Layer FR4 PWB With Separate Power and Ground Planes
• 178 Pin Card Edge Module
• Burndy Connector, Part Number: ELF178KSC–3Z50
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
Order this document
by MPC2105C/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MPC2105C
MPC2106C
178–LEAD CARD EDGE
TOP VIEW
MPC2105C CASE 1132A–01
MPC2106C CASE 1132–01
89
25
24
1
48
47
10/14/97
Motorola, Inc. 1997
MPC2105C•MPC2106C
2
MOTOROLA FAST SRAM
A0 = NC
CLK3 = NC
CLK4 = NC
ALE = NC
ADS1
= NC
CNTEN1
= NC
CG1
= NC
ADDR0 = NC
ADDR1 = NC
DH24 – DH31 + DP3
CLK1
DL16 – DL23 + DP6
DL24 – DL31 + DP7
Note: BA28 is tied to SA0 on SRAM;
BA27 is tied to SA1 on SRAM;
STANDBY is tied to SE3
on SRAM.
69F618CTQ
G
SE1
ADSC
CG0
SA
ADV
ADS0
CWE1
CLK0
DH0 – DH7 + DP0
DH8 – DH15 + DP1
CWE0
CNTEN0
CWE2
CLK0
DH16 – DH23 + DP2
CWE3
K
DQB
DQA
CWE4
SBB
SBA
CLK1
DL0 – DL7 + DP4
DL8 – DL15 + DP5
CWE5
CWE6
CWE7
V
SS
K
DQB
DQA
SBB
SBA
K
DQB
DQA
SBB
SBA
K
DQB
DQA
SBB
SBA
69F618CTQ
69F618CTQ
69F618CTQ
G
SE1
ADSC
SA
ADV
G
SE1
ADSC
SA
ADV
G
SE1
ADSC
SA
ADV
’244
A13 – A28
BA13 – BA28
PD3
PD2
PD1
PD0
J2
J0
J3
A13 – A26
A1 – A12
TCLR
TWE
CLK2
MATCH
VALIDIN
DIRTYIN
TG
TAG: 16K x 12 + V + D
A0 – A13
RESET
TAG0 –11
TAH, TAG
, TAD
SFUNC, SG
SW
TW
K
VALIDD
DIRTYD
TG
TT1, WTD, E1
E2, PWRDN
V
SS
VCC via 100
Ω
WTQ
TA
, VALIDQ
V
CCQ
V
DD
NC
MATCH
DIRTYOUT
DIRTYQ
SE2
SGW
ADSP
SW
ZZ
SRAM TIE OFF
J1
V
CC
V
CC
V
DD
MPC2105C BLOCK DIAGRAM
MPC2105C•MPC2106C
3
MOTOROLA FAST SRAM
A13 – A26
A0 – A11
TCLR
TWE
CLK2
MATCH
VALIDIN
DIRTYIN
TG
TAG: 16K x 12 + V + D
A0 – A13
RESET
TAG0 –11
TAH, TAG, TAD
SFUNC, SG
SW
TW
K
E2
VALIDD
DIRTYD
TG
ALE = NC
ADDR0 = NC
ADDR1 = NC
DH24 – DH31 + DP3
CLK4
DL16 – DL23 + DP6
DL24 – DL31 + DP7
TT1, WTD
PWRDN
V
SS
VCC via 100
Ω
WTQ
TA
, VALIDQ
V
CCQ
V
DD
NC
A12
69F618CTQ
G
SE1
ADSC
CG0
SA
ADV
ADS0
CWE0
CLK0
DH0 – DH7 + DP0
DH8 – DH15 + DP1
CWE1
CNTEN0
CWE2
CLK1
DH16 – DH23 + DP2
CWE3
K
DQB
DQA
CWE4
SBB
SBA
CLK3
DL0 – DL7 + DP4
DL8 – DL15 + DP5
CWE5
CWE6
CWE7
K
DQB
DQA
SBB
SBA
K
DQB
DQA
SBB
SBA
K
DQB
DQA
SBB
SBA
69F618CTQ
69F618CTQ
69F618CTQ
G
SE1
ADSC
SA
ADV
G
SE1
ADSC
SA
ADV
G
SE1
ADSC
SA
ADV
’244
A13 – A28
BA13 – BA28
PD3
PD2
PD1
PD0
J2
J0
J3
J1
69F618CTQ
G
SE2
ADSC
CG1
SA
ADV
ADS1
CNTEN1
K
DQA
DQB
SBA
SBB
K
DQA
DQB
SBA
SBB
K
DQA
DQB
SBA
SBB
K
DQA
DQB
SBA
SBB
69F618CTQ
69F618CTQ
69F618CTQ
G
SE2
ADSC
SA
ADV
G
SE2
ADSC
SA
ADV
G
SE2
ADSC
SA
ADV
A12
BA12
BANK A: SE2 TIED TO.
VDD VIA 100
Ω.
BANK B: SE1 TIED TO. V
SS
MATCH
DIRTYOUT
DIRTYQ
E1
V
CC
E2
A12
E1 V
SS
Note: BA28 is tied to SA0 on SRAM;
BA27 is tied to SA1 on SRAM;
STANDBY is tied to SE3
on SRAM.
SGW
ADSP
SW
ZZ
SRAM TIE OFF
V
DD
V
CC
V
CC
MPC2106C BLOCK DIAGRAM
MPC2105C•MPC2106C
4
MOTOROLA FAST SRAM
PIN ASSIGNMENT
178–LEAD DIMM
TOP VIEW
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
VALIDIN
TWE
STANDBY
DIRTYOUT
TCLR
MATCH
TG
DIRTYIN
DP5
DL7
DL4
V
DD
DL3
DL1
DL0
V
SS
DP4
CG0
CG1
V
DD
ADDR0
RESERVED
ADS0
ADS1
A28
A26
A25
A23
V
SS
A21
A19
A17
A13
V
DD
A12
A11
A9
V
SS
A7
A5
V
CC
A3
A0
DL8
CWE5
DL6
V
DD
DL5
DL2
V
SS
CLK3
V
SS
CLK4
V
SS
CWE4
ALE
V
DD
ADDR1
RESERVED
CNTEN0
CNTEN1
A27
A24
A22
A20
V
SS
A18
A16
A15
A14
V
DD
A10
A8
A6
V
SS
A4
A2
A1
BURSTMODE
V
SS
V
CC
CLK0
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
016
107
108
109
110
111
112
113
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
V
SS
DP3
DH22
DH20
DH19
PD0/IDSCLK
PD2
DH30
DH28
DH26
DH24
DH5
V
DD
V
SS
DH17
DP2
DH15
DH12
V
CC
DH11
DH9
DP1
DH7
V
DD
DH3
DH2
DH0
DP0
V
SS
DL28
DL26
DL24
DP7
V
CC
DP6
DL14
DL12
DL11
V
SS
DL22
DL20
DL18
DL16
V
SS
V
SS
DH1
CWE0
DL31
DL30
V
CC
DL29
DL27
DL25
V
SS
CWE7
DL23
DL21
DL19
V
SS
DL17
CWE6
DL15
DL13
V
SS
V
SS
PD1/IDSDATA
PD3
DH31
DH29
DH27
DH25
V
DD
CWE3
DH23
DH21
DH18
V
SS
DH16
CWE2
DH14
DH13
V
CC
DH10
DH8
CEW1
DH6
V
DD
DH4
V
SS
V
SS
CLK1
DL9DL10
V
SS
CLK2
V
SS
MPC2105C•MPC2106C
5
MOTOROLA FAST SRAM
PIN DESCRIPTIONS
Pin Locations Symbol
Type Description
66, 67, 68, 69, 71, 72, 73,
74, 76, 77, 78, 80, 81, 82,
83, 155, 156, 157, 158,
160, 161, 162, 163, 165,
166, 167, 169, 170, 171
A0 – A28 Input Address Inputs – (MSB:0, LSB:28).
62 ADDR0 Input Least significant address bit when asynchronous Data RAMs are used.
151 ADDR1 Input Next to least significant address bit when asynchronous Data RAMs are used.
64, 65 ADS0, ADS1 Input Data RAM Address Strobe – For MPC2105C use ADS0 only. For MPC2106C
use ADS0
, ADS1..
149 ALE Input Data RAM Address Latch Enable – Use for asynchronous Data RAM only.
172 BURSTMODE Input Burstmode. 0 = Linear, 1 = Interleaved.
59, 60 CG0,
CG1
Input Data RAM Output Enables. – For MPC2105C use CG0 only. For MPC2106C
use CG0
, CG1.
30, 56, 115, 144, 146 CLK0 – CLK4 Input Clock Inputs – CLK2 is for T ag RAM, CLK0, 1, 3, and 4 are for Data RAMs only .
For MPC2106C use all the clocks. For MPC2105C use CLK0 – CLK2 only.
153, 154 CNTEN0,
CNTEN1
Input Data RAM Count Enables – For MPC2105C use CNTEN0 only. For
MPC2106C use CNTEN0
, CNTEN1.
98, 104, 110, 118,
126, 132, 138, 148
CWE0 – CWE7 Input Data RAM Write Enables – (MSB:0, LSB:7).
4, 5, 6, 7, 10, 11, 12, 14,
16, 17, 19, 20, 22, 24, 25,
26, 27, 93, 94, 95, 96, 99,
100, 101, 103, 105, 106,
108, 109, 111, 113, 117
DH0 – DH31 I/O High Data Bus – (MSB:0, LSB:31).
88 DIRTYIN Input Dirty input bit.
177 DIRTYOUT Output Dirty output bit.
32, 33, 34, 37, 38, 39, 40, 43,
44, 45, 47, 49, 50, 52, 53, 54,
119, 120, 122, 123, 124, 127,
128, 129, 131, 133, 134, 136,
137, 139, 141, 142
DL0 – DL31 I/O Low Data Bus – (MSB:0, LSB:31).
9, 15, 21, 28, 35, 42, 48, 58 DP0 – DP7 I/O Data Parity Bits – (MSB:0, LSB:7)
86 MATCH Output Tag RAM active high match indication.
2 PD0/IDSCLK Input Presence detect bit 0/EEPROM serial clock. (EEPROM option only).
91 PD1/IDSDATA I/O Presence detect bit 1/EEPROM serial data. (EEPROM option only).
3, 92 PD2, PD3 Output Presence detect bits.
63, 152 RESERVED Reserved pin.
176 STANDBY Input Standby pin. Reduces standby power consumption.
85 TCLR Input Tag RAM clear.
87 TG Input Tag RAM output enable.
175 TWE Input Tag RAM write enable.
174 VALIDIN Input Tag RAM valid bit.
18, 36, 84, 107, 125, 173 V
CC
Input + 5 V power supply. Must be connected.
8, 23, 51, 61, 75, 97,
112, 140, 150, 164
V
DD
Input + 3.3 V power supply. Must be connected.
1, 13, 29, 31, 41, 46, 55, 57,
70, 79, 89, 90, 102, 114,
116, 121, 130, 135, 143,
145, 147, 159, 168, 178
V
SS
Input Ground.
MPC2105C•MPC2106C
6
MOTOROLA FAST SRAM
DATA RAM MCM69F618C SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, and 3)
STANDBY
ADSx CNTENx CWEx CLKx Address Used Operation
H L X X L–H N/A Deselected
L L X L L–H External Address Write Cycle, Begin Burst
L L X H L–H External Address Read Cycle, Begin Burst
X H L L L–H Next Address Write Cycle, Continue Burst
X H L H L–H Next Address Read Cycle, Continue Burst
X H H L L–H Current Address Write Cycle, Suspend Burst
X H H H L–H Current Address Read Cycle, Suspend Burst
NOTES:
1. X means don’t care.
2. All inputs except CG
must meet set–up and hold times for the low–to–high transition of clock (CLK0 – CLK4).
3. Wait states are inserted by suspending burst.
ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2)
Operation
CG I/O Status
Read L Data Out (DQ0 – DQ8)
Read H High–Z
Write X High–Z — Data In
Deselected X High–Z
NOTES:
1. X means don’t care.
2. For a write operation following a read operation, CG
must be high before the input data required set–up time and held high through the input
data hold time.
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to V
SS
= 0 V)
Rating
Symbol Value Unit
Power Supply Voltage V
CC
– 0.5 to + 7.0 V
Voltage Relative to V
SS
Vin, V
out
– 0.5 to VCC + 0.5 V
Output Current (per I/O) Data RAM
Tag
I
out
± 30
± 20
mA
Power Dissipation MPC2105C
MPC2106C
P
D
4.6
9.2
W
Temperature Under Bias T
bias
– 10 to + 85 °C
Operating Temperature T
A
0 to +70 °C
Storage Temperature T
stg
– 55 to + 125 °C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high–impedance
circuit.
This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.
This device contains circuitry that will
ensure the output devices are in High–Z at
power up.
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