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1
Motorola Bipolar Power Transistor Device Data
DPAK For Surface Mount Applications
. . . designed for low voltage, low–power, high–gain audio amplifier applications.
• Collector–Emitter Sustaining Voltage — V
CEO(sus)
= 100 Vdc (Min) @ IC = 10 mAdc
• High DC Current Gain — hFE= 40 (Min) @ IC = 200 mAdc
= 15 (Min) @ IC = 1.0 Adc
• Lead Formed for Surface Mount Applications in Plastic Sleeves (No Suffix)
• Straight Lead Version in Plastic Sleeves (“–1” Suffix)
• Lead Formed Version in 16 mm Tape and Reel (“T4” Suffix)
• Low Collector–Emitter Saturation Voltage —
V
CE(sat)
= 0.3 Vdc (Max) @ IC = 500 mAdc
= 0.6 Vdc (Max) @ IC = 1.0 Adc
• High Current–Gain — Bandwidth Product — fT = 40 MHz (Min) @ IC = 100 mAdc
• Annular Construction for Low Leakage — I
CBO
= 100 nAdc @ Rated V
CB
Collector–Emitter Voltage
Collector Current — Continuous
Peak
Total Device Dissipation @ TC = 25_C
Derate above 25_C
Total Device Dissipation @ TA = 25_C*
Derate above 25_C
Operating and Storage Junction
Temperature Range
Thermal Resistance, Junction to Case
Junction to Ambient*
_
C/W
*When surface mounted on minimum pad sizes recommended.
25
25
Figure 1. Power Derating
T, TEMPERATURE (°C)
0
50 75 100 125 150
15
10
T
C
5
20
P
D
, POWER DISSIPATION (WATTS)
2.5
0
1.5
1
T
A
0.5
2
T
C
TA (SURFACE MOUNT)
Preferred devices are Motorola recommended choices for future use and best overall value.
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MJD243/D
NPN SILICON
POWER TRANSISTOR
4 AMPERES
100 VOLTS
12.5 WATTS
*Motorola Preferred Device
MINIMUM PAD SIZES
RECOMMENDED FOR
SURFACE MOUNTED
APPLICATIONS
0.243
6.172
0.063
1.6
0.118
3.0
0.07
1.8
0.165
4.191
0.190
4.826
inches
mm
CASE 369A–13
CASE 369–07
REV 1
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MJD243
2
Motorola Bipolar Power Transistor Device Data
ELECTRICAL CHARACTERISTICS (T
C
= 25_C unless otherwise noted)
Collector–Emitter Sustaining Voltage (1) (IC = 10 mAdc, IB = 0)
Collector Cutoff Current (VCB = 100 Vdc, IE = 0)
Collector Cutoff Current (VCB = 100 Vdc, IE = 0, TJ = 125_C)
Emitter Cutoff Current (VBE = 7 Vdc, IC = 0)
DC Current Gain (1) (IC = 200 mAdc, VCE = 1 Vdc)
DC Current Gain (1) (IC = 1 Adc, VCE = 1 Vdc)
Collector–Emitter Saturation Voltage (1)
(IC = 500 mAdc, IB = 50 mAdc)
(IC = 1 Adc, IB = 100 mAdc)
Base–Emitter Saturation Voltage (1) (IC = 2 Adc, IB = 200 mAdc)
Base–Emitter On Voltage (1) (IC = 500 mAdc, VCE = 1 Vdc)
Current–Gain — Bandwidth Product (2) (IC = 100 mAdc, VCE = 10 Vdc, f
test
= 10 MHz)
Output Capacitance (VCB = 10 Vdc, IE = 0, f = 0.1 MHz)
pF
(1) Pulse Test: Pulse Width = 300 µs, Duty Cycle [ 2%.
(2) fT = hFE• f
test
.
Figure 2. Active Region Maximum Safe
Operating Area
10
VCE, COLLECTOR–EMITTER VOLTAGE (VOLTS)
0.01
100
2
5
0.1
BONDING WIRE LIMITED
THERMALLY LIMITED @ TC = 25
°
C
(SINGLE PULSE)
SECOND BREAKDOWN LIMITED
CURVES APPLY BELOW
RATED V
CEO
500µs
dc
1
1 ms
502010521
100µs
I
C
, COLLECTOR CURRENT (AMPS)
0.02
0.05
0.2
0.5
5 ms
There are two limitations on the power handling ability of a
transistor: average junction temperature and second breakdown. Safe operating area curves indicate IC – VCE limits of
the transistor that must be observed for reliable operation;
i.e., the transistor must not be subjected to greater dissipation than the curves indicate.
The data of Figure 2 is based on T
J(pk)
= 150_C; TC is
variable depending on conditions. Second breakdown pulse
limits are valid for duty cycles to 1 0% provided T
J(pk)
v
150_C. T
J(pk)
may be calculated from the data in Figure 3. At high case temperatures, thermal limitations will reduce the power that can be handled to values less than the
limitations imposed by second breakdown.
t, TIME (ms)
0.01
0.02 0.05 1 2 5 10 20 50 100 2000.1 0.50.2
1
0.2
0.1
0.05
r(t), TRANSIENT THERMAL
R
θ
JC
(t) = r(t)
θ
JC
R
θ
JC
= 10
°
C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
1
T
J(pk)
– TC = P
(pk)
θ
JC
(t)
P
(pk)
t
1
t
2
DUTY CYCLE, D = t1/t
2
0.2
RESISTANCE (NORMALIZED)
0.5
D = 0.5
0.05
0.3
0.7
0.07
0.03
0.02
0 (SINGLE PULSE)
Figure 3. Thermal Response
0.1
0.02
0.01