Motorola MCM69Q536TQ8, MCM69Q536TQ8R, MCM69Q536TQ6R, MCM69Q536TQ10, MCM69Q536TQ10R Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Advance Information

32K x 36 Bit Synchronous
Separate I/O SRAM

The Motorola MCM69Q536 is a 1 Megabit static random access memory , organized
as 32K words of 36 bits. It features separate data input and data output buffers and
incorporates input and output registers on board with high speed SRAM.

The MCM69Q536 allows the user to perform transparent writes and data pass
through. Two data bus ports are provided — a data input (D) and a data output (Q) port.

The synchronous design allows for precise cycle control with the use of an external
single clock (K). Address port, data input (D0 – D35), data output (Q0 – Q35), write en­able (W
rising edge of clock (K).

writes can be intermixed. Thus, one can perform a read, a write, or a combination read/
write during any one cycle. For a combination read/write, the contents of the array are
read before the new data is written.

the contents of the array or the data presented to the input port D. For read/write or a
read cycle with G
is asserted, the Q port will instead output the data presented at the D input port.

• Single 3.3 V ± 5% Power Supply

• Fast Access Times: 6/8/10 ns Max

• Sustained Throughput of 2.98 Gigabits/Second

• Single Clock Operation

• Address, Data Input, E1

• 83 MHz Maximum Clock Cycle Time

• Self Timed Write

• Separate Data Input and Data Output Pins

• Pass–Through Feature

• Asynchronous Output Enable (G

• L VTTL Compatible I/O

• No Dead Cycles Required for Reads after Writes or for Writes after Reads

• 176 Pin TQFP Package

• Simultaneous Reads and Writes

), chip enables (E1, E2), and pass–through enable (PT) are registered on the

Any given cycle operates on only one address. However, for any cycle, reads and

By using the pass–through function, the output port Q can be made to reflect either

low, the Q port will output the contents of the array. However, if PT

, E2, PT, W, and Data Output Registers on Chip

)

Order this document

by MCM69Q536/D

MCM69Q536

TQ PACKAGE

176 LEAD TQFP

CASE 1101–01

Suggested Applications

— A TM — Ethernet Switches — Routers
— Cell/Frame Buffers — SNA Switches — Shared Memory

Product Family Configurations

Part

Number

MCM69D536
MCM69D618
MCM69Q536
MCM69Q618
MCM67Q709
MCM67Q909

NOTES:

1. Tie AX and AY address ports together for the part to function as a single address part.

2. Tie GX

This document contains information on a new product. Specifications and information herein are subject to change without notice.

REV 3
11/20/97

 Motorola, Inc. 1997

MOTOROLA FAST SRAM

high for DQX to be inputs and tie WY high and GY low for DQY to be outputs.

Dual

Address

n
n

Single

Address

Note 1
Note 1

n n
n n
n n
n n

Dual

I/O

n
n

Separate

I/O

Note 2
Note 2

MCM69Q536

1

BLOCK DIAGRAM

K

A0 – A14

W

PT

E1

E2

G

15

ADDRESS

REGISTER

REGISTER

REGISTER

ENABLE

REGISTER 1

WRITE

PT

ENABLE

REGISTER 2

32K x 36 ARRAY

WRITE

DRIVER

PASS–THROUGH

DATA INPUT

REGISTER

D0 – D35 Q0 – Q35

SENSE

AMP

DATA OUTPUT

REGISTER

MCM69Q536
2

MOTOROLA FAST SRAM

PIN ASSIGNMENT

V

SS

D20

Q20

V

DD

V

SS
D21
Q21
D22
Q22

V

DD

V

SS
D23
Q23
D24
Q24

V

DD

V

SS
D25
Q25
D26
Q26

V

DD

V

SS
Q27
D27

Q28

D28

V

DD

V

SS
Q29

D29
Q30
D30

V

DD

V

SS
Q31
D31
Q32

D32

V

DD

V

SS
Q33
D33

V

SS

1
2
3
4

5
6
7

8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

SS

V

176

Q19

175

DD

D19

174

SS

V

173

V

172

NC

A6

D18

Q18

171

170

168

169

51 524849 50 56 575354 55 59605845 46 47 64636261

A7

167

NC

166

SS

V

165

NC

164

NC

163

NC

162

NC

161

NCKNC

NC

160

159

NC

158

157

156

VDDV

155

SS

154

NC

153

NC

E2

G

152

W

E1

151

150

148

149

71 726968 70 76 7773 74 75 79 8078656667 84838281

NC

147

PT

146

A8

145

NC

144

A9

143

NC

142

NC

141

NC

140

D17

139

Q17

138

DD

V

137

SS

V

136

D16

135

Q16

134

132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112

111

110
109
108
107
106
105
104
103
102

101
100

88878685

SS

V

133

99
98

97
96

95
94
93

92
91
90
89

V

SS

D15
Q15

V

SS

V

DD

D14
Q14
D13
Q13
V

SS

V

DD
D12
Q12

D11
Q11
V

SS
V

DD

D10

Q10
D9
Q9
V

SS

V

DD

Q8
D8
Q7
D7

V

SS

V

DD

Q6
D6

Q5
D5

V

SS

V

DD
Q4
D4

Q3
D3
V

SS

V

DD

Q2
D2
V

SS

SSVSS

V

Q34

D34

DD

V

Q35

MOTOROLA FAST SRAM

SSNCA5NCA4NCA3NCA2

SS

V

V

D35

NCA1NC

A0VSS

DD

V

A10

NC

A11

NC

A12NCA13NCA14

NC

NCNCNC

NC

D0

Q0

DD

V

SSVSS

Q1

D1

V

MCM69Q536

3

PIN DESCRIPTIONS

Pin Locations Symbol Type Description

55, 57, 59, 61, 63, 65, 68, 70, 72, 74, 76,

143, 145, 167, 169

2, 6, 8, 12, 14, 18, 20, 25, 27, 31, 33, 37,

39, 43, 47, 51, 82, 86, 90, 94, 96, 100,

102, 106, 108, 113. 115, 119, 121, 125,

127, 131, 135, 139, 170, 174

150 E1 Input Synchronous Chip Enable: Active low for depth expansion.
151 E2 Input Synchronous Chip Enable: Active high for depth expansion.
152 G Input Asynchronous Output Enable Input:

156 K Input Clock: This signal registers the address, data in, and all control signals

146 PT Input Pass–through enable: Synchronous.

3, 7, 9, 13, 15, 19, 21, 24, 26, 30, 32, 36,

38, 42, 46, 50, 83, 87, 91, 95, 97, 101,

103, 107, 109, 112, 114, 118, 120, 124,

126, 130, 143, 138, 171, 175

148 W Input Synchronous Write.

4, 10, 16, 22, 28, 34, 40, 49, 67, 84, 98,

104, 110, 116, 122, 128, 137, 155, 172

1, 5, 11, 17, 23, 29, 35, 41, 44, 45, 48,
52, 53, 66, 85, 88, 89, 93, 99, 105, 111,
117, 123. 129, 132, 133, 136, 154, 165,

173, 176

54, 56, 58, 60, 62, 64, 69, 71, 73, 75,

77 – 81, 140, 141, 142, 144, 147, 149,

153, 157 – 164, 166, 168

A0 – A14 Input Synchronous Address Inputs: These inputs are registered and must

D0 – D35 Input Synchronous Data Input.

Q0 – Q35 Output Synchronous Data Output.

V

DD

V

SS

NC — No Connection: There is no connection to the chip.

Supply + 3.3 V Power Supply.

Supply Ground.

meet setup and hold times.

Low — enables output buffers (Qx pins).
High — Qx pins are high impedance.

except G

.

TRUTH TABLE

Input at tn Clock Result from tn + 1 Clock Notes

Operation

Write and Pass–Through L H L L D written to A D data appears 1

Write/Read L H L H D written to A Q out from A 2

Pass–Through L H H L D data D data appears 3

Read L H H H Don’t Care Q out from A 4
Deselected X L X X Don’t Care Q is high–Z 5
Deselected H X X X Don’t Care Q is high–Z 6

NOTES:

1. W rite D to array and output D at Q.

2. Output contents of array to Q then write D to array.

3. Output D at Q. Do not write.

4. Output contents of array to Q. Do not write.

5. No operation.

6. No operation.

E1 E2 W PT Data Input D Data Output Q

MCM69Q536
4

MOTOROLA FAST SRAM