Motorola MCM69P817ZP3R, MCM69P817ZP3, MCM69P817ZP3.5, MCM69P817ZP2.5, MCM69P817ZP3.5R Datasheet

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SEMICONDUCTOR TECHNICAL DATA

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MCM69P817

256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM

The MCM69P817 is a 4M bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the PowerPC and other high performance microprocessors. It is organized as 256K words of 18 bits each. This device integrates input registers, an output register, a 2–bit address counter, and a high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K).

Addresses (SA), data inputs (DQx), and all control signals except output enable (G edge–triggered noninverting registers.

addresses can be generated internally by the MCM69P817 (burst sequence operates in linear or interleaved mode dependent upon the state of LBO controlled by the burst address advance (ADV

clock (K) input. This feature eliminates complex off–chip write pulse generation and provides increased timing flexibility for incoming signals.

nous write enable (SW to all bytes. The two bytes are designated as “a” and “b”. SBa SBb asserted with SW SW

edge–triggered output register and then released to the output buffers at the next rising edge of clock (K).

operate on a 3.3 V or 2.5 V power supply . All inputs and outputs are JEDEC standard JESD8–5 compatible.

• MCM69P817 Speed Options

• 3.3 V + 10%, – 5% Core Power Supply , Operates with a 3.3 V or 2.5 V I/O

• ADSP

• Selectable Burst Sequencing Order (Linear/Interleaved)

• Single–Cycle Deselect Timing

• Internally Self–Timed Write Cycle

• Byte Write and Global Write Control

• PB1 Version 2.0 Compatible

• JEDEC Standard 119–Pin PBGA Package

BurstRAM is a trademark of Motorola, Inc. The PowerPC name is a trademark of IBM Corp., used under license therefrom.

This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.

) and linear burst order (LBO) are clock (K) controlled through positive–

Bursts can be initiated with either ADSP

Write cycles are internally self–timed and are initiated by the rising edge of the

Synchronous byte write (SBx

) are provided to allow writes to either individual bytes or

controls DQb. Individual bytes are written if the selected byte writes SBx are

. All bytes are written if either SGW is asserted or if all SBx and

are asserted.

For read cycles, pipelined SRAMs output data is temporarily stored by an

The MCM69P817 operates from a 3.3 V core power supply and all outputs

Speed t

200 MHz 5 ns 2.5 ns 0.5 ns 1 ns 475 mA PBGA 180 MHz 5.5 ns 3.0 ns 0.5 ns 1 ns 450 mA PBGA 166 MHz 6 ns 3.5 ns 0.5 ns 1 ns 425 mA PBGA

Supply

, ADSC, and ADV Burst Control Pins

KHKH

), synchronous global write (SGW), and synchro-

Pipelined

KHQV

or ADSC input pins. Subsequent burst

) and

) input pin.

controls DQa and

Setup Hold I

Pkg

ZP PACKAGE

PBGA

CASE 999–01

6/10/97

 Motorola, Inc. 1997

MOTOROLA FAST SRAM

MCM69P817

LBO ADV

K ADSC ADSP

SA SA1 SA0

FUNCTIONAL BLOCK DIAGRAM

ADDRESS

BURST

COUNTER

CLR

256K x 18 ARRAY

SGW

SBa

SBb

SE1 SE2

SE3

WRITE

K2 K

ENABLE

DATA–IN

DATA–OUT REGISTER

DQa – DQb

MCM69P817 2

MOTOROLA FAST SRAM

PIN ASSIGNMENT

6543217 A B C

D E

F G

H J

K L

M N P R T U

SA SA SA SA

DDQ

NC SE2 SA ADSC

SA SA SA SA

DQb NC VSSNC DQa

DQbNC

NC V

DDQ

DQb

NC VSSSGW

DDQ NC DQb V

NCDQb

DQb V

DDQ

NCDQb

NC DQb VSSSA0

SA SA

SA SA SA SA

NC DDQ

SS SS

SBbDQbNC

SS SS SS

LBO

NCNC

ADSP

SE3

SS V V V

V V V

NCV

DQa

DQa V

DQaSBa

DQaSA1V

KV NC SW

NCSE1

NCADV

DDQ NC

NC NC

DQa

DDQ

DQa

DDQ

DQa

DDQ NC

DQa

DDQ

TOP VIEW 119 BUMP PBGA

Not to Scale

MOTOROLA FAST SRAM

MCM69P817

PBGA PIN DESCRIPTIONS

Pin Locations Symbol Type Description

4B ADSC Input Synchronous Address Status Controller: Active low, interrupts any

4A ADSP Input Synchronous Address Status Processor: Active low , interrupts any

4G ADV Input Synchronous Address Advance: Increments address count in

(a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P

(b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P

4F G Input Asynchronous Output Enable Input:

4K K Input Clock: This signal registers the address, data in, and all control signals

3R LBO Input Linear Burst Order Input: This pin must remain in steady state (this

2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C,

5C, 6C, 2R, 6R, 2T, 3T, 5T, 6T

4N, 4P SA1, SA0 Input Synchronous Address Inputs: These pins must be wired to the two

5L, 3G (a) (b)

4E SE1 Input Synchronous Chip Enable: Active low to enable chip.

2B SE2 Input Synchronous Chip Enable: Active high for depth expansion. 6B SE3 Input Synchronous Chip Enable: Active low for depth expansion. 4H SGW Input Synchronous Global Write: This signal writes all bytes regardless of the

4M SW Input Synchronous Write: This signal writes only those bytes that have been

4C, 2J, 4J, 6J, 4R V

1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U V

3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H, 3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P

1B, 7B, 1C, 7C, 2D, 4D, 7D, 1E, 6E,

2F, 1G, 6G, 2H, 7H, 3J, 5J, 1K, 6K, 2L, 4L, 7L, 6M, 2N, 7N, 1P, 6P, 1R,

5R, 7R, 1T, 4T, 7T, 2U, 3U, 4U, 5U, 6U

ongoing burst and latches a new external address. Used to initiate a READ, WRITE, or chip deselect.

ongoing burst and latches a new external address used to initiate a new READ or chip deselect (exception — chip deselect does not occur when ADSP

accordance with counter type selected (linear/interleaved).

DQx I/O Synchronous Data I/O: “x” refers to the byte being read or written

SA Input Synchronous Address Inputs: These inputs are registered and must

SBx Input Synchronous Byte Write Inputs: “x” refers to the byte being written (byte

DDQ

NC — No Connection: There is no connection to the chip.

Supply Core Power Supply. Supply I/O Power Supply. Supply Ground.

(byte a, b).

Low — enables output buffers (DQx pins). High — DQx pins are high impedance.

except G

signal not registered or latched). It must be tied high or low. Low — linear burst counter (68K/PowerPC). High — interleaved burst counter (486/i960/Pentium).

meet setup and hold times.

LSBs of the address bus for proper burst operation. These inputs are registered and must meet setup and hold times.

a, b). SGW

Negated high — blocks ADSP asserted.

status of the SBx being used, tie this pin high.

selected using the byte write SBx are being used, tie this pin low.

is asserted and SE1 is high).

and LBO.

overrides SBx.

or deselects chip when ADSC is

and SW signals. If only byte write signals SBx are

pins. If only byte write signals SBx

MCM69P817 4

MOTOROLA FAST SRAM

TRUTH TABLE (See Notes 1 Through 5)

Address

Next Cycle

Deselect None 1 X X X 0 X X High–Z X Deselect None 0 X 1 0 X X X High–Z X Deselect None 0 0 X 0 X X X High–Z X Deselect None X X 1 1 0 X X High–Z X Deselect None X 0 X 1 0 X X High–Z X Begin Read External 0 1 0 0 X X X High–Z X Begin Read External 0 1 0 1 0 X X High–Z READ Continue Read Next X X X 1 1 0 1 High–Z READ Continue Read Next X X X 1 1 0 0 DQ READ Continue Read Next 1 X X X 1 0 1 High–Z READ Continue Read Next 1 X X X 1 0 0 DQ READ Suspend Read Current X X X 1 1 1 1 High–Z READ Suspend Read Current X X X 1 1 1 0 DQ READ Suspend Read Current 1 X X X 1 1 1 High–Z READ Suspend Read Current 1 X X X 1 1 0 DQ READ Begin Write External 0 1 0 1 0 X X High–Z WRITE Continue Write Next X X X 1 1 0 X High–Z WRITE Continue Write Next 1 X X X 1 0 X High–Z WRITE Suspend Write Current X X X 1 1 1 X High–Z WRITE Suspend Write Current 1 X X X 1 1 X High–Z WRITE

NOTES:

1. X = don’t care. 1 = logic high. 0 = logic low.

2. Write is defined as either (a) any SBx

3. G

is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (t

4. On write cycles that follow read cycles, G also remain negated at the completion of the write cycle to ensure proper write data hold times.

5. This read assumes the RAM was previously deselected.

Used

SE1 SE2 SE3 ADSP ADSC ADV G

and SW low or (b) SGW is low.

must be negated prior to the start of the write cycle to ensure proper write data setup times. G must

GLQX

DQx Write 2,

) following G going low.

LINEAR BURST ADDRESS TABLE (LBO = V

1st Address (External)

X . . . X00 X . . . X01 X . . . X10 X . . . X11 X . . . X01 X . . . X10 X . . . X11 X . . . X00 X . . . X10 X . . . X11 X . . . X00 X . . . X01 X . . . X11 X . . . X00 X . . . X01 X . . . X10

2nd Address (Internal) 3rd Address (Internal) 4th Address (Internal)

INTERLEAVED BURST ADDRESS TABLE (LBO = V

1st Address (External) 2nd Address (Internal) 3rd Address (Internal) 4th Address (Internal)

X . . . X00 X . . . X01 X . . . X10 X . . . X11 X . . . X01 X . . . X00 X . . . X11 X . . . X10 X . . . X10 X . . . X11 X . . . X00 X . . . X01 X . . . X11 X . . . X10 X . . . X01 X . . . X00

)

WRITE TRUTH TABLE

Cycle Type SGW SW SBa SBb

Read H H X X Read H L H H Write Byte a H L L H Write Byte b H L H L Write All Bytes H L L L Write All Bytes L X X X

MOTOROLA FAST SRAM

MCM69P817

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