Motorola MCM6946YJ12R, MCM6946YJ15, MCM6946YJ15R, MCM6946YJ8, MCM6946YJ8R Datasheet
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Advance Information
512K x 8 Bit Static Random
Access Memory
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by MCM6946/D
MCM6946
The MCM6946 is a 4,194,304–bit static random access memory organized as
524,288 words of 8 bits. Static design eliminates the need for external clocks or
timing strobes.
The MCM6946 is equipped with chip enable (E
allowing for greater system flexibility and eliminating bus contention problems.
Either input, when high, will force the outputs into high–impedance.
The MCM6946 is available in a 400 mil, 36–lead surface–mount SOJ package.
• Single 3.3 V – 5%, + 10% Power Supply
• Fast Access Time: 8/10/12/15 ns
• Equal Address and Chip Enable Access Time
• All Inputs and Outputs are TTL Compatible
• Three–State Outputs
• Power Operation: 195/185/180/175 mA Maximum, Active AC
• Available in TSOP or SOJ Packages
) and output enable (G) pins,
PIN NAMES
A0 – A18 Address Inputs. . . . . . . . . . . . . . .
W
G
E
DQ Data Input/Output. . . . . . . . . . . . . . . . .
NC No Connection. . . . . . . . . . . . . . . . . . . .
V
CC
V
SS
+ 3.3 V Power Supply. . . . . . . . . . . . .
YJ PACKAGE
400 MIL SOJ
CASE 893–02
TS PACKAGE
44–LEAD
TSOP TYPE II
CASE 924A–02
Write Enable. . . . . . . . . . . . . . . . . . . . . . .
Output Enable. . . . . . . . . . . . . . . . . . . . .
Chip Enable. . . . . . . . . . . . . . . . . . . . . . . .
Ground. . . . . . . . . . . . . . . . . . . . . . . . .
This document contains information on a new product. Specifications and information herein are subject to change without notice.
REV 5
3/31/98
Motorola, Inc. 1998
MOTOROLA FAST SRAM
MCM6946
1
BLOCK DIAGRAM
A
A
A
A
A
A
A
A
A
A
ROW
DECODER
MEMORY MATRIX
DQ
DQ
COLUMN I/O
INPUT
DATA
CONTROL
AAAAAAAAA
E
W
G
COLUMN DECODER
DQ
DQ
MCM6946
2
MOTOROLA FAST SRAM
PIN ASSIGNMENTS
400 MIL SOJ TSOP TYPE II
NC
1
A
2
A
3
A
4
5
A
6
E
DQ
7
DQ
8
V
9
CC
V
10
SS
DQ
11
DQ
12
13
W
14
A
15
A
A
16
A
17
A
18
36
35
34
33A
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A
A
A
A
G
DQ
DQ
V
V
DQ
DQ
A
A
A
A
A
NC
SS
CC
1
NC
2
A
3
A
4
A
5
6
A
7
A
E
8
9
DQ
10
DQ
V
11
DD
12
V
SS
13
DQ
14
DQ
15
W
16
A
17
18
A
19
A
20
A
21
NC
22
NC
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
A
A
A
A
G
DQ
DQ
V
V
DQ
DQ
A
A
AA
A
A
NC
NC
NC
SS
DD
MOTOROLA FAST SRAM
MCM6946
3
TRUTH TABLE (X = Don’t Care)
E G W Mode I/O Pin Cycle Current
H X X Not Selected High–Z — I
L H H Output Disabled High–Z — I
L L H Read D
L X L Write High–Z Write I
out
Read I
SB1
, I
CCA
CCA
CCA
SB2
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating Symbol Value Unit
Power Supply Voltage Relative to V
Voltage Relative to VSS for Any Pin
Except V
Output Current (per I/O) I
Power Dissipation P
Temperature Under Bias T
Operating Temperature T
Storage Temperature — Plastic T
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
CC
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
SS
V
CC
Vin, V
out
bias
stg
– 0.5 to + 5.0 V
– 0.5 to VCC + 0.5 V
out
± 20
D
– 10 to + 85 °C
A
0 to + 70 °C
– 55 to + 150 °C
mA
1.0 W
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to these high–impedance
circuits.
This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board and
transverse air flow of at least 500 linear feet per
minute is maintained.
MCM6946
4
MOTOROLA FAST SRAM
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