MOTOROLA MCM6323A Technical data

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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

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64K x 16 Bit 3.3 V Asynchronous
Fast Static RAM

The MCM6323A is a 1,048,576 bit static random access memory organized
as 65,536 words of 16 bits. Static design eliminates the need for external clocks
or timing strobes; CMOS circuitry reduces power consumption and provides for
greater reliability .

The MCM6323A is equipped with chip enable (E
enable (G

) pins, allowing for greater system flexibility and eliminating bus contention
problems. Separate byte enable controls (LB
written and read. LB

controls the 8 DQa bits, while UB controls the 8 DQb bits.

The MCM6323A is available in a 400 mil small–outline J–leaded (SOJ) pack­age and a 44–lead TSOP Type II package in copper leadframe for optimum
printed circuit board (PCB) reliability.

• Single 3.3 V ± 0.3 V Power Supply

• Fast Access Time: 10, 12, 15 ns

• Equal Address and Chip Enable Access Time

• All Inputs and Outputs are TTL Compatible

• Data Byte Control

• Fully Static Operation

• Power Operation: 140/135/130 mA Maximum, Active AC

• Industrial Temperature Option: – 40 to + 85°C

Part Number: SCM6323A YJ10A

BLOCK DIAGRAM

OUTPUT

G

ENABLE
BUFFER

A

ADDRESS
BUFFERS

16

CHIP

E

ENABLE
BUFFER

WRITE

W

ENABLE
BUFFER

LB

BYTE

ENABLE

UB

BUFFER

This document contains information on a new product under development. Motorola reserves the right
to change or discontinue this product without notice.

7

9

ROW

DECODER

HIGH BYTE OUTPUT ENABLE

LOW BYTE OUTPUT ENABLE

COLUMN

DECODER

64K x 16

BIT

MEMORY

ARRAY

HIGH BYTE WRITE ENABLE

LOW BYTE WRITE ENABLE

), write enable (W), and output

and UB) allow individual bytes to be

HIGH

8

BYTE
OUTPUT
BUFFER

HIGH

8

BYTE

WRITE

DRIVER

SENSE

16

AMPS

LOW

8

BYTE
OUTPUT
BUFFER

LOW

BYTE

WRITE

DRIVER

Order this document

by MCM6323A/D

MCM6323A

YJ PACKAGE

400 MIL SOJ

CASE 919–01
TS PACKAGE

44–LEAD

TSOP TYPE II

CASE 924A–01

PIN ASSIGNMENT

A

1

A

2

A

3

A

4

A

5
6

E

DQa

7

DQa

8

DQa

9

DQa

10

V

11

DD

V

12

SS

DQa

13

DQa

14

DQa

15

8

DQb

8

8

8

DQa

8

A Address Input. . . . . . . . . . . . . . . . . . . . . . . .

E

88

W
G
UB
LB

DQa Lower Data Input/Output. . . . . . . . . . . .

DQb Upper Data Input/Output. . . . . . . . . . . .

V
V

NC No Connection. . . . . . . . . . . . . . . . . . . . .

DD
SS

DQa

A
A

A
A

NC

PIN NAMES

16
17
18
19
20
21
22

+ 3.3 V Power Supply. . . . . . . . . . . . . .

44
43
42
41
40
39
38
37
36
35

34
33
32
31
30
29
28
27
26
25
24
23

Output Enable. . . . . . . . . . . . . . . . . . . . . .

A
A
A
G
UB
LB
DQb
DQb
DQb
DQb

V

SS

V

DD

DQb
DQb
DQb
DQb
NCW
A
A
A
A
NC

Chip Enable. . . . . . . . . . . . . . . . . . . . . . . . .

Write Enable. . . . . . . . . . . . . . . . . . . . . . . .

Upper Byte. . . . . . . . . . . . . . . . . . . . . . . .

Lower Byte. . . . . . . . . . . . . . . . . . . . . . . . .

Ground. . . . . . . . . . . . . . . . . . . . . . . . . .

REV 1
10/17/97

 Motorola, Inc. 1997

MOTOROLA FAST SRAM

MCM6323A

1

TRUTH TABLE (X = Don’t Care)

G W LB UB Mode VDD Current DQa’s DQb’s

E

H X X X X Not Selected I

L H H X X Output Disabled I
L X X H H Output Disabled I
L L H L H Low Byte Read I
L L H H L High Byte Read I
L L H L L Word Read I
L X L L H Low Byte Write I
L X L H L High Byte Write I
L X L L L Word Write I

SB1

, I

DDA
DDA
DDA
DDA
DDA
DDA
DDA
DDA

SB2

ABSOLUTE MAXIMUM RATINGS (See Notes)

Rating

Supply Voltage V
Voltage on Any Pin V
Output Current per Pin I
Package Power Dissipation P
Temperature Under Bias Commerial

Industrial

Operating Temperature Commerial

Industrial

Storage Temperature T

NOTES:

1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER­ATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.

2. All voltages are referenced to VSS.

3. Power dissipation capability will be dependent upon package characteristics and use
environment.

Symbol Value Unit

– 0.5 to + 4.6 V

– 0.5 to VDD + 0.5 V

± 20 mA

.75 W

– 10 to + 85
– 45 to + 90

0 to + 70

– 40 to + 85

– 55 to + 150 °C

T

DD

in

out

D

bias

T

A

stg

High–Z High–Z
High–Z High–Z
High–Z High–Z

D

out

High–Z D

D

out

D

in

High–Z D

D

in

°C

°C

High–Z

out

D

out

High–Z

in

D

in

This device contains circuitry to protect the
inputs against damage due to high static volt­ages or electric fields; however, it is advised
that normal precautions be taken to avoid appli­cation of any voltage higher than maximum
rated voltages to these high–impedance cir­cuits.

This CMOS memory circuit has been de­signed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board
and transverse air flow of at least 500 linear feet
per minute is maintained.

MCM6323A
2

MOTOROLA FAST SRAM

DC OPERA TING CONDITIONS AND CHARACTERISTICS

(VDD = 3.3 V ± 0.3 V, TA = 0 to 70°C, Unless Otherwise Noted)

(TA = – 40 to + 85°C for Industrial Temperature Offering)

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Typ Max Unit

Power Supply Voltage V
Input High Voltage V
Input Low Voltage V

*VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.

**VIH (max) = VDD + 0.3 V dc; VIH (max) = VDD + 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.

DD

IH

IL

DC CHARACTERISTICS

Parameter Symbol Min Max Unit

Input Leakage Current (All Inputs, Vin = 0 to VDD) I
Output Leakage Current (E = VIH, V
Output Low Voltage (IOL = + 4.0 mA)

Output High Voltage (IOH = – 4.0 mA)

= 0 to VDD) I

out

(IOL = + 100 µA)

(IOH = – 100 µA)

POWER SUPPLY CURRENTS (See Note 1)

Parameter

AC Active Supply Current (I
(VDD = max, f = f

AC Standby Current (E = VIH, VDD = max, Commerical
f = f

CMOS Standby Current (VDD = max, f = 0 MHz, Commerical
E
or ≥ VDD – 0.2 V)

NOTES:

) Industrial

max

≥ VDD – 0.2 V, Vin ≤ VSS + 0.2 V, Industrial

1. Typical current = 25°C @ 3.3 V.

2. Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3.0 V, VIH = 3.0 V, VIL = 0 V).

) Industrial

max

= 0 mA) Commerical

out

Symbol 6323A–10 6323A–12 6323A–15 Unit Notes

I

DDA

I

SB1

I

SB2

3.0 3.3 3.6 V

2.2 —

– 0.5*

lkg(I)

lkg(O)

V

V

140
150

40
45

5
5

OL

OH

— 0.8 V

— ± 1.0 µA
— ± 1.0 µA
— 0.4

2.4

VDD – 0.2

135
140

35
40

5
5

VDD + 0.3**

VSS + 0.2

130
135

30
35

5
5

— V

mA 2

mA 2

mA

V

V

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T

Address Input Capacitance C
Control Input Capacitance C
Input/Output Capacitance C

= 25°C, Periodically Sampled Rather Than 100% Tested)

A

Parameter

MOTOROLA FAST SRAM

Symbol Typ Max Unit

in
in

I/O

— 6 pF
— 6 pF
— 8 pF

MCM6323A

3

AC OPERA TING CONDITIONS AND CHARACTERISTICS

(VDD = 3.3 V ± 0.3 V, TA = 0 to +70°C, Unless Otherwise Noted)

(TA = – 40 to + 85°C for Industrial Temperature Offering)

Logic Input Timing Measurement Reference Level 1.50 V. . . . . . . .

Logic Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time 2 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output Timing Reference Level 1.50 V. . . . . . . . . . . . . . . . . . . . . . . . .

Output Load See Figure 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

READ CYCLE TIMING (See Notes 1, 2, 3, and 4)

MCM6323A–10 MCM6323A–12 MCM6323A–15

Parameter Symbol

Read Cycle Time t
Address Access Time t
Enable Access Time t
Output Enable Access Time t
Output Hold from Address Change t
Enable Low to Output Active t
Output Enable Low to Output Active t
Enable High to Output High–Z t
Output Enable High to Output High–Z t
Byte Enable Access Time t
Byte Enable Low to Output Active t
Byte High to Output High–Z t

NOTES:

1. W

is high for read cycle.

2. For common I/O applications, minimization, or elimination of bus contention conditions is necessary during read and write cycles.

3. Device is continuously selected (E

4. Addresses valid prior to or coincident with E

5. All read cycle timings are referenced from the last valid address to the first transitioning address.

6. Transition is measured 200 mV from steady–state voltage.

7. At any given voltage and temperature, t
device to device.

8. This parameter is sampled and not 100% tested.

= VIL, G = VIL, and LB and/or UB = VIL).

going low.

EHQZ

AVAV
AVQV
ELQV
GLQV
AXQX
ELQX
GLQX
EHQZ

GHQZ

BLQV
BLQX
BHQZ

(max) < t

Min Max Min Max Min Max

10 — 12 — 15 — ns 5
— 10 — 12 — 15 ns
— 10 — 12 — 15 ns
— 4 — 5 — 6 ns 6

3 — 3 — 3 — ns
3 — 3 — 3 — ns 6, 7, 8

0 — 0 — 0 — ns 6, 7, 8
— 4 — 5 — 6 ns 6, 7, 8
— 4 — 5 — 6 ns 6, 7, 8
— 4 — 5 — 6 ns

0 — 0 — 0 — ns 6, 7, 8

0 5 0 5 0 5 ns 6, 7, 8

ELQX

(min), and t

GHQZ

(max) < t

(min), both for a given device and from

GLQX

Unit Notes

MCM6323A
4

MOTOROLA FAST SRAM