Motorola MCM6265CJ20, MCM6265CJ15, MCM6265CJ12, MCM6265CJ12R2, MCM6265CP35 Datasheet

MCM6265C

1

MOTOROLA FAST SRAM

8K x 9 Bit Fast Static RAM

The MCM6265C is fabricated using Motorola’s high–performance silicon–gate
CMOS technology. Static design eliminates the need for external clocks or timing
strobes, while CMOS circuitry reduces power consumption and provides for
greater reliability.

This device meets JEDEC standards for functionality and pinout, and is avail­able in plastic dual–in–line and plastic small–outline J–leaded packages.

• Single 5 V ± 10% Power Supply

• Fully Static — No Clock or Timing Strobes Necessary

• Fast Access Times: 12, 15, 20, 25, and 35 ns

• Equal Address and Chip Enable Access Times

• Output Enable (G

) Feature for Increased System Flexibility and to

Eliminate Bus Contention Problems

• Low Power Operation: 110 – 150 mA Maximum AC

• Fully TTL Compatible — Three State Output

ROW

DECODER

MEMORY MATRIX

256 ROWS x 32

x 9 COLUMNS

INPUT

DATA

CONTROL

COLUMN I/O

COLUMN DECODER

DQ0

E1

W

V

CC

V

SS

A1

DQ8

G

BLOCK DIAGRAM

E2

A0 A6 A8 A12

A11

A10

A9

A7

A5

A4

A3

A2

Order this document

by MCM6265C/D

PIN ASSIGNMENT

MCM6265C

P PACKAGE

300 MIL PLASTIC

CASE 710B–01

A0 – A12 Address Input. . . . . . . . . . . . .

DQ0 – DQ8 Data Input/Data Output. . .
W

Write Enable. . . . . . . . . . . . . . . . . . . .

G

Output Enable. . . . . . . . . . . . . . . . . . .

E1

, E2 Chip Enable. . . . . . . . . . . . . . . . .

V

CC

Power Supply (+ 5 V). . . . . . . . . . .

V

SS

Ground. . . . . . . . . . . . . . . . . . . . . . .

PIN NAMES

J PACKAGE

300 MIL SOJ

CASE 810B–03

5

4

3

2

1

10

9

8

7

6

11
12
13

14

20

21

22

23

24

25

26

19

27

28

18
17
16

15

A2

A5

A6

A7

A8

DQ1

A1

A4

V

SS

DQ3

DQ2

A3

A0

DQ0

A10

A9

E2

W

V

CC

DQ5

DQ6

DQ7

DQ4

E1

G

A11

DQ8

A12

REV 2
5/95

 Motorola, Inc. 1994

MCM6265C
2

MOTOROLA FAST SRAM

TRUTH TABLE (X = Don’t Care)

E1

E2 G W Mode VCC Current Output Cycle

H X X X Not Selected I

SB1

, I

SB2

High–Z —

X L X X Not Selected I

SB1

, I

SB2

High–Z —

L H H H Output Disabled I

CCA

High–Z —

L H L H Read I

CCA

D

out

Read Cycle

L H X L Write I

CCA

High–Z Write Cycle

ABSOLUTE MAXIMUM RATINGS (See Note)

Rating

Symbol Value Unit

Power Supply Voltage V

CC

– 0.5 to + 7.0 V

Voltage Relative to VSS for Any Pin
Except V

CC

Vin, V

out

– 0.5 to VCC + 0.5 V

Output Current I

out

± 20 mA

Power Dissipation P

D

1.0 W

Temperature Under Bias T

bias

– 10 to + 85 °C

Operating Temperature T

A

0 to + 70 °C

Storage Temperature — Plastic T

stg

– 55 to + 125 °C

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are

exceeded. Functional operation should be restricted to RECOMMENDED OPER­ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to +70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Typ Max Unit

Supply Voltage (Operating Voltage Range) V

CC

4.5 5.0 5.5 V

Input High Voltage V

IH

2.2 — VCC + 0.3** V

Input Low Voltage V

IL

– 0.5* — 0.8 V

*VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns)

**VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2 V ac (pulse width ≤ 20 ns)

DC CHARACTERISTICS

Parameter Symbol Min Max Unit

Input Leakage Current (All Inputs, Vin = 0 to VCC) I

lkg(I)

— ± 1 µA

Output Leakage Current (E1 = VIH, E2 = VIL, or G = VIH, V

out

= 0 to VCC) I

lkg(O)

— ± 1 µA

Output Low Voltage (IOL = 8.0 mA) V

OL

— 0.4 V

Output High Voltage (IOH = – 4.0 mA) V

OH

2.4 — V

POWER SUPPLY CURRENTS

Parameter Symbol – 12 – 15 – 20 – 25 – 35 Unit

AC Active Supply Current (I

out

= 0 mA, VCC = Max, f = f

max

) I

CCA

150 140 130 120 110 mA

AC Standby Current (E1 = VIH or E2 = V

IL, VCC

= Max, f = f

max

) I

SB1

45 40 35 30 30 mA

Standby Current (E1 ≥ VCC – 0.2 V or E2 ≤ VSS + 0.2 V,
Vin ≤ VSS + 0.2 V or ≥ VCC – 0.2 V)

I

SB2

20 20 20 20 20 mA

CAPACITANCE (f = 1 MHz, dV = 3 V, T

A

= 25°C, Periodically Sampled Rather Than 100% Tested)

Parameter

Symbol Max Unit

Address Input Capacitance C

in

6 pF

Control Pin Input Capacitance (E1, E2, G, W) C

in

6 pF

I/O Capacitance C

I/O

7 pF

device contains circuitry to protect the
inputs against damage due to high static volt­ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi­mum rated voltages to these high–impedance
circuits.

This CMOS memory circuit has been de­signed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board
and transverse air flow of at least 500 linear
feet per minute is maintained.

This

MCM6265C

3

MOTOROLA FAST SRAM

AC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)

Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .

Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time 5 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . .

Output Load See Figure 1A Unless Otherwise Noted. . . . . . . . . . . .

READ CYCLE (See Notes 1 and 2)

– 12 – 15 – 20 – 25 – 35

Parameter Symbol Min Max Min Max Min Max Min Max Min Max Unit Notes

Read Cycle Time t

AVAV

12 — 15 — 20 — 25 — 35 — ns 3

Address Access Time t

AVQV

— 12 — 15 — 20 — 25 — 35 ns

Enable Access Time t

ELQV

— 12 — 15 — 20 — 25 — 35 ns 4

Output Enable Access Time t

GLQV

— 6 — 8 — 10 — 11 — 12 ns

Output Hold from Address Change t

AXQX

4 — 4 — 4 — 4 — 4 — ns

Enable Low to Output Active t

ELQX

4 — 4 — 4 — 4 — 4 — ns 5,6,7

Enable High to Output High–Z t

EHQZ

0 6 0 8 0 9 0 10 0 11 ns 5,6,7

Output Enable Low to Output Active t

GLQX

0 — 0 — 0 — 0 — 0 — ns 5,6,7

Output Enable High to Output High–Z t

GHQZ

0 6 0 7 0 8 0 9 0 10 ns 5,6,7

Power Up Time t

ELICCH

0 — 0 — 0 — 0 — 0 — ns

Power Down Time t

EHICCL

— 12 — 15 — 20 — 25 — 35 ns

NOTES:

1. W

is high for read cycle.

2. E1

and E2 are represented by E in this data sheet. E2 is of opposite polarity to E.

3. All timings are referenced from the last valid address to the first transitioning address.

4. Addresses valid prior to or coincident with E

going low.

5. At any given voltage and temperature, t

EHQZ

(max) is less than t

ELQX

(min), and t

GHQZ

(max) is less than t

GLQX

(min), both for a given

device and from device to device.

6. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1B.

7. This parameter is sampled and not 100% tested.

8. Device is continuously selected (E1

= VIL, E2 = VIH, G = VIL).

Z0 = 50

Ω

50

Ω

VL = 1.5 V

Figure 1A Figure 1B

5 pF

+ 5 V

OUTPUT

255

Ω

480

Ω

AC TEST LOADS

The table of timing values shows either
a minimum or a maximum limit for each pa­rameter. Input requirements are specified
from the external system point of view.
Thus, address setup time is shown as a
minimum since the system must supply at
least that much time (even though most
devices do not require it). On the other
hand, responses from the memory are
specified from the device point of view.
Thus, the access time is shown as a maxi­mum since the device never provides data
later than that time.

TIMING LIMITS

OUTPUT