Motorola MC74HC158AJ, MC74HC158ADT, MC74HC158AD Datasheet

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SEMICONDUCTOR TECHNICAL DATA

3–1

REV 0

 Motorola, Inc. 1996

3/96

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High–Performance Silicon–Gate CMOS

The MC74HC158A is identical in pinout to the LS158. The device
inputs are compatible with Standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.

These devices route 2 nibbles (A or B) to a single port (Y) as deter­mined by the Select input. The data is presented at the outputs in inverted
form for the HC158A. A high level on the Output Enable input sets all four
Y outputs to a high level for the HC158A.

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS and TTL

• Operating Voltage Range: 2 to 6V

• Low Input Current: 1µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance With the JEDEC Standard No. 7A Requirements

• Chip Complexity: 74 FETs or 18.5 Equivalent Gates

LOGIC DIAGRAM

Select

Nibble

A Inputs

Pin 16 = VCC
Pin 8 = GND

1

A3

14

A2

11

A1

5

A0

2

Y3

12

Y2

9

Y1

7

Y0

4

Output

Enable

15

Data
Outputs

Nibble

B Inputs

B3

13

B2

10

B1

6

B0

3

1516 14 13 12 11 10

21 3 4 5 6 7

V

CC

9

8

Output
Enable

A3 B3 Y3 A2 B2 Y2

Select A0 B0 Y0 A1 B1 Y1 GND

Pinout: 16–Lead Plastic Package (Top View)

This document contains information on a new product. Specifications and information herein are subject to
change without notice.

X = Don’t Care
A0–A3, B0–B3 = the levels of the respec-

tive Data–Word inputs.

H
L
L

X
L
H

FUNCTION TABLE

Inputs Outputs

Output
Enable

Select

H

A0

–A3

B0–B3

Y0–Y3



D SUFFIX

SOIC PACKAGE

CASE 751B–05

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

ORDERING INFORMATION

MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT

Plastic
SOIC
TSSOP

1

16

1

16

1

16

DT SUFFIX

TSSOP PACKAGE

CASE 948F-01

MC74HC158A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

3–2

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

V

CC

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

V

V

in

DC Input Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

V

out

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

I

in

DC Input Current, per Pin

± 20

mA

I

out

DC Output Current, per Pin

± 25

mA

I

CC

DC Supply Current, VCC and GND Pins

± 50

mA

P

D

Power Dissipation in Still Air, Plastic DIP†

SOIC Package†

TSSOP Package†

750
500
450

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

T

L

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP, SOIC or TSSOP Package)

260

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

Max

Unit

V

CC

DC Supply Voltage (Referenced to GND)

2.0

6.0

V

Vin, V

out

DC Input Voltage, Output Voltage (Referenced to GND)

0

V

CC

V

T

A

Operating Temperature, All Package Types

– 55

+ 125

_

C

tr, t

f

Input Rise and Fall Time VCC = 2.0 V

(Figure 2) VCC = 3.0 V

VCC = 4.5 V
VCC = 6.0 V

0
0
0
0

1000

600
500
400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

Symbol

Parameter

Test Conditions

V

CC

V

–55_C to

25_C

v

85_Cv 125_C

Unit

V

IH

Minimum High–Level Input
Voltage

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

2.0

3.0

4.5

6.0

1.5

2.1

3.15

4.2

1.5

2.1

3.15

4.2

1.5

2.1

3.15

4.2

V

V

IL

Maximum Low–Level Input
Voltage

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

2.0

3.0

4.5

6.0

0.5

0.9

1.35

1.8

0.5

0.9

1.35

1.8

0.5

0.9

1.35

1.8

V

V

OH

Minimum High–Level Output
Voltage

Vin = VIH or V

IL

|I

out

| v 20 µA

2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

V

Vin = VIH or VIL|I

out

| v 2.4 mA

|I

out

| v 4.0 mA

|I

out

| v 5.2 mA

3.0

4.5

6.0

2.48

3.98

5.48

2.34

3.84

5.34

2.20

3.70

5.20

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir­cuit. For proper operation, Vin and
V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

MC74HC158A

High–Speed CMOS Logic Data
DL129 — Rev 6

3–3 MOTOROLA

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

Unit

v

125_C

v

85_C

–55_C to

25_C

V

CC

V

Test Conditions

Parameter

Symbol

V

OL

Maximum Low–Level Output
Voltage

Vin = VIH or V

IL

|I

out

| v 20 µA

2.0

4.5

6.0

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

V

Vin = VIH or VIL|I

out

| v 2.4 mA

|I

out

| v 4.0 mA

|I

out

| v 5.2 mA

3.0

4.5

6.0

0.26

0.26

0.26

0.33

0.33

0.33

0.40

0.40

0.40

I

in

Maximum Input Leakage Current

Vin = VCC or GND

6.0

± 0.1

± 1.0

± 1.0

µA

I

CC

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
I

out

= 0 µA

6.0

4

40

160

µA

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

AC ELECTRICAL CHARACTERISTICS (C

L

= 50 pF, Input tr = tf = 6.0 ns)

Guaranteed Limit

Symbol

Parameter

V

CC
V

–55_C to

25_C

v

85_Cv 125_C

Unit

t

PLH

,

t

PHL

Maximum Propagation Delay, Input A to Output Y

(Figures 1 and 4)

2.0

3.0

4.5

6.0

125

85
25
21

155

95
31
26

190
110

38
32

ns

t

PLH

,

t

PHL

Maximum Propagation Delay, CS1 to Output Y

(Figures 2 and 4)

2.0

3.0

4.5

6.0

125

85
25
21

155

95
31
26

190
110

38
32

ns

t

PLH

,

t

PHL

Maximum Propagation Delay, CS2 or CS3 to Output Y

(Figures 3 and 4)

2.0

3.0

4.5

6.0

115

80
23
20

145

90
29
25

175
100

35
30

ns

t

TLH

,

t

THL

Maximum Output Transition Time, Any Output

(Figures 2 and 4)

2.0

3.0

4.5

6.0

75
27
15
13

95
32
19
16

110

36
22
19

ns

C

in

Maximum Input Capacitance

—

10

10

10

pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–

Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

C

PD

Power Dissipation Capacitance (Per Package)*

35

pF

*Used to determine the no–load dynamic power consumption: PD = CPD V

CC

2

f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).