MOTOROLA MC68322 Technical data
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Microprocessor and Memory
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MC68322
Product Brief
Integrated Printer Processor
The MC68322 is a high-performance integrated printer processor, which combines an MC68000 compatible
EC000 Core processor, a RISC graphics processor (RGP) and a print engine video controller (PVC) with
numerous system integration features on a single integrated circuit. It is the first of Motorola's M68000 family
designed specifically for laser printers. The MC68322 provides a unique solution for new designs as well as
an excellent migration path for existing M68000-powered printers. Additionally, the new chip will find ready
application to the inkjet printer and multifunction-peripheral (Fax/Modem/Printer) markets and other
embedded control applications, which require very fast bit manipulations. The MC68322 provides
outstanding performance at an extremely affordable price.
Historically, printer applications have been solved using a single general purpose processor and external
application specific circuitry. The MC68322 employs a highly specialized, multi-processor architecture, which
enables the user to take advantage of memory reduction techniques. This design implementation provides a
technically superior and more cost effective system solution. Specialized display list banding techniques
executed by the dedicated RISC graphics processor enable system memory requirements to be significantly
reduced.
The use of software memory reduction techniques alone, an approach taken by conventional controllers,
lack the power needed to handle complex pages, causing the controller to fall back to lower resolution or
reduced page throughput. By integrating an EC000 Core, RGP, and PVC using a unique dual bus
architecture, the MC68322 optimizes overall system performance. The dual bus architecture eliminates bus
contention between processing units creating a true parallel processing environment. The additional
bandwidth allows each processing unit to operate at peak performance. Working in conjunction with an on chip, programmable, bursting DRAM controller, the processing units are capable of achieving outstanding
throughput. These dedicated processing units enable the MC68322 to produce 600 dot per inch images
using substantially less memory than conventional controllers. The MC68322 extends these benefits to lowcost 4–8 page per minute printers.
The MC68322 significantly reduces component count, board space, power consumption and their inherent
costs while yielding higher reliability and shorter design time. The MC68322 provides support for toner
conservation, enabling the print controller to conserve toner when printing in draft mode. The MC68322
provides the perfect printing environment for users of complex page description languages (such as PCL
and PostScript) and less scaleable graphics imaging models such as Windows Printing System and
QuickDraw). Complete code compatibility with the M68000 Family provides the designer access to a broad
base of established real-time kernels, operating systems, languages, applications and development tools,
many of which are optimized for embedded processing and printing applications. Figure 1 shows a block
diagram of the MC68322.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without
notice.Company and product names that appear in this document are for identification purposes and should be considered registered trademarks of their
respective owners.
SEMICONDUCTOR PRODUCT INFORMATION
PARALLEL PORT
IEEE 1284
PROM
PERIPHERAL
(OPTIONAL)
STATIC
EC000 CORE
SYSTEM
INTEGRATION
MODULE (SIM)
EC000 BUS
IN-CIRCUIT
EMULATION
(OPTIONAL)
PARALLEL PORT
DMA
DMA
BUS
INTERFACE UNIT
DRAM CONTROL
GRAPHICS
EXECUTION UNIT (GEU)
RISC GRAPHICS
PROCESSOR (RGP)
GRAPHICS BUS
PRINT ENGINE VIDEO
CONTROLLER (PVC)
SERIAL
ETHERNET
LOCAL TALK
SCSI
CLOCK
DRAM
Figure 1. System Block Diagram
PRINT ENGINE
2 MC68322 PRODUCT INFORMATION MOTOROLA
FEATURES
• Static EC000 Core Processor
– Complete Code Compatibility with M68000 Family
– Glueless Interface to Peripherals
– 256 Mbyte Address Range
• Graphics Execution Unit (GEU)
– Memory Reduction Techniques
- Run Length Encoded Scan Line Tables
– RISC Graphics Processor (RGP)
- Processes Multi-Operation Graphics Orders from Display List
- Produces Compressed Bit Map Image using Hardware Banding
- Dedicated Graphics Bus Allows up to 8 PPM Performance at 600 DPI Resolution
– Print Engine Video Controller (PVC)
- Converts Bit Map Image to Serial Data Stream and Feeds Print Engine
- Generic, Programmable, Non-Impact Printer Communications Interface
- Toner Conservation Technique
– Dedicated High-Performance DMA Controller for GEU Operations
• Bus Interface Unit (BIU)
– Dual Bus Architecture Allows Separate Buses to Function Independently
– Distributed Processing Optimizes System Performance
• System Integration Module (SIM)
– 8 Programmable Chip Selects
– 256 Kbytes to 512 Mbytes of PROM Address Space
– Independently Programmable Timing Parameters for each ROM Bank
– Integrated System Timer
• DRAM System Integration Module (DSIM)
– Supports 512 Kbyte, 2 Mbyte, and 8 Mbyte DRAM Bank Sizes
– Directly Controls up to 6 Banks of DRAM; Supports up to 48 Mbytes of DRAM
– Programmable Transparent Refresh of DRAM Banks
– Bursting DRAM Interface
• General-Purpose DMA Controller Module
– Provides High Speed Downloads Without Impact to Core Processor Performance
• IEEE 1284 Parallel Port Controller Module
– DMA Controller Supports 2 Mbyte/sec Bidirectional Communication Transfers
• 16MHz or 20MHz Operation
• 160 Pin Plastic Quad Flat Pack (QFP)
MOTOROLA MC68322 PRODUCT INFORMATION 3
MC68322 SIGNAL DESCRIPTION
Figure 2 illustrates the MC68322 input and output signals within their functional groups. Table 1 lists the
signal names, mnemonics, and functional descriptions of the MC68322 signals.
PARALLEL PORT
INTERFACE
PVC
INTERFACE
PRINTER
COMMUNICATION
INTERFACE
PD7–PD0
SELECTIN
STROBE
AUTOFD
INIT
ACK
BUSY
SELECT
PERROR
FAULT
VCLK
FSYNC
LSYNC
VIDEO
PRINT
CCLK
CBSY
SBSY
CMD/STS
STS
MC68322
A25–A1
D15–D0
CS7–CS0
RD
WRU
WRL
WAIT
IRQ1–IRQ0
CLK2
RESET
TEST
MA10–MA0
MD15–MD0
RAS5–RAS0
CAS1–CAS0
WE
DREQ
DACK
AS
R/W
EDTACK
BR
BG
ADDRESS BUS
DATA BUS
EC000 CORE
INTERFACE
SYSTEM
INTERFACE
MEMORY ADDRESS BUS
MEMORY DATA BUS
DRAM
INTERFACE
DMA
INTERFACE
EXTERNAL
BUS MASTER
INTERFACE
Figure 2. MC68322 Functional Signal Groups
4 MC68322 PRODUCT INFORMATION MOTOROLA
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