MOTOROLA MC34016 Technical data

Device

Operating

Temperature Range

Package



SEMICONDUCTOR

TECHNICAL DATA

CORDLESS UNIVERSAL

TELEPHONE INTERFACE

ORDERING INFORMATION

MC34016P
MC34016DW

DIP

SO–20

DW SUFFIX

PLASTIC PACKAGE

CASE 751D

20

1

(Top View)

PIN CONNECTIONS

Order this document by MC34016/D

P SUFFIX

PLASTIC PACKAGE

CASE 738

20

1

1 20

19
18
17
16
15
14
13

2
3
4
5
6
7
8

Clk
Data
Out2
Stab

Out1

BEN

LAI

AGC

T

x1

R

x1

12

9

V

CC

I

ref

R

x2

1110

HYL HYS

T

x2

SRF

LAO

Gnd

HKSW

TA = –20° to +70°C

1

MOTOROLA ANALOG IC DEVICE DATA

 
 

The MC34016 is a telephone line interface meant for use in cordless
telephone base stations for CT0, CT1, CT2 and DECT. The circuit forms the
interface towards the telephone line and performs all speech and line
interface functions like dc and ac line termination, 2–4 wire conversion,
automatic gain control and hookswitch control. Adjustment of transmission
parameters is accomplished by two 8–bit registers accessible via the
integrated serial bus interface and by external components.

• DC Masks for Voltage and Current Regulation

• Supports Passive or Active AC Set Impedance Applications

• Double Wheatstone Bridge Sidetone Architecture

• Symmetrical Inputs and Outputs with Large Signal Swing Capability

• Gain Setting and Mute Function for T

x

and Rx Amplifiers

• Very Low Noise Performance

• Serial Bus Interface SPI Compatible

• Operation from 3.0 to 5.5 V

FEATURES

Line Driver Architecture

• Two DC Masks for Voltage Regulation

• Two DC Masks for Current Regulation

• Passive or Active Set Impedance Adjustment

• Double Wheatstone Bridge Architecture

• Automatic Gain Control Function

Transmit Channel

• Symmetrical Inputs Capable of Handling Large Voltage Swing

• Gain Select Option via Serial Bus Interface

• Transmit Mute Function, Programmable via Bus

• Large Voltage Swing Capability at the Telephone Line

Receive Channel

• Double Sidetone Architecture for Optimum Line Matching

• Symmetrical Outputs Capable of Producing High Voltage Swing

• Gain Select Option via Serial Bus Interface

• Receive Mute Function, Programmable via Serial Bus

Serial Bus Interface

• 3–Wire Connection to Microcontroller

• One Programmable Output Meant for Driving a Hookswitch

• Two Programmable Outputs Capable of Driving Low Ohmic Loads

• Two 8–Bit Registers for Parameter Adjustment

 Motorola, Inc. 1996 Rev 1

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MC34016

2

MOTOROLA ANALOG IC DEVICE DATA

Representative Block Diagram

This device contains 610 active transistors + 242 gates.

R

x

T

x

Supply Serial Bus Interface AGC

Line

Driver

Serial Bus

Inputs

Logic

Outputs

R

x1

R

x2

T

x1

T

x2

R

x

Outputs

T

x

Inputs

HYS HYL LAI SRF

LAO

Gnd

VCCI

ref

Clk Data BEN Out1 Out2 HKSW AGC

Hook
Switch

A (Tip)

B (Ring)

I

BG

V

BG

+

–

MC34016

+5.0 V

MAXIMUM RATINGS

Rating Symbol Value Unit

Operation Supply Voltage V

CC

–0.5, 6.5 V

All Other Inputs V

in

–0.5,

VCC +0.5

V

Operating Ambient Temperature T

A

–20 to +70 °C

Junction Temperature T

J

+150 °C

NOTE: ESD data available upon request.

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MC34016

3

MOTOROLA ANALOG IC DEVICE DATA

DC ELECTRICAL CHARACTERISTICS (All parameters are specified with Bit 0 of Register 1 set to 1, the rest of the

bits in both registers set to 0, TA = 25°C, VCC = 5.0 V, I

line

= 15 mA, f = 1.0 kHz, Test Circuit in Figure 9, unless otherwise noted.)

Parameter

Condition Min Typ Max Unit

VOLTAGE REGULATION

= 5.0 mA

Line Voltage V

line

I

line

= 5.0 mA

I

line

= 15 mA

3.7

4.2

4.0

4.5

4.3

4.8

V

line

= 15 mA

I

line

= 60 mA

CURRENT REGULATION (Bit 4, Reg.1 = 1; Bit 1, Reg. 2 = 1; R

AGC

= 47 kΩ)

Line Voltage V

line

I

line

= 15 mA 4.2 4.5 4.8 V

line

line

= 10 V

Line Current I

line

V

line

= 10 V

V

line

= 35 V

––3556––mA

Line Current I

line

in Protection Mode V

line

= 70 V – 28 – mA

DC BIASING

Operating Supply Voltage V

CC

– 3.0 – 5.5 V

CC

CC

= 3.0 V, all Bits to 0

Current Consumption from V

CC

VCC = 3.0 V, all Bits to 0
VCC = 5.0 V, all Bits to 0

––3.0

3.5

4.0

4.5

mA

Source Capabiltiy Pin LAO in Speech Mode V

LAO

= 0.7 V – – –2.0 mA

Source Capability Pin LAO in Dialing Mode

(Bit 5, Reg. 1 = 1)

V

LAO

= 0.7 V – – –5.0 mA

Internal Pull Down Resistor at Pin LAO – – 11 – kΩ
Bias Voltage at Pins HYL, HYS and LAI – – 1.3 – V
Bias Voltage at Pins Tx1 and T

x2

– – 1.5 – V

Bias Voltage at Pins Rx1 and R

x2

– – 1.3 – V

LOGIC INPUTS

Logic Low Level Pins Clk, Data, BEN – – – 0.6 V
Logic High Level Pins Clk, Data, BEN – 2.2 – – V

LOGIC OUTPUTS

Source Capability from Pins HKSW, Out1, Out2 Output Voltage at VCC – 1.3 V – – –1.0 mA
Sink Capability into Pins HKSW, Out1, Out2 Output Voltage at 0.5 V 5.0 – – mA

AC ELECTRICAL CHARACTERISTICS (All parameters are specified with Bit 0 of Register 1 set to 1, the rest of the

bits in both registers set to 0, TA = 25°C, VCC = 5.0 V, I

line

= 15 mA, f = 1.0 kHz, Test Circuit in Figure 9, unless otherwise noted.)

Parameter

Condition Min Typ Max Unit

TRANSMIT CHANNEL

Transmit Gain from VTx to V

line

MC34016P

MC34016DW

VTx = 0.1 Vrms

–1.0

–1.25

0.25

–0.20

1.5

0.85

dB

Gain Variation with Line Current Referred to

I

line

= 15 mA with the AGC Function Switched “Off”

I

line

= 70 mA,

Bit 0, Reg. 2 = 1

–0.7 – 0.7 dB

Gain Increase in 6.0 dB Mode Bit 4, Reg. 2 = 1 5.3 6.0 6.7 dB
Gain Reduction in Mute Condition Bit 2, Reg. 2 = 1 65 – – dB
Input Impedance at Tx1 or T

x2

– – 30 – kΩ

Maximum Input Swing for VT

x

THD ≤ 2% – 4.0 – Vpp

THD at the Line (V

line

) VTx = 3.0 dBm – 1.0 2.0 %

Psophometrically Weighted Noise Level at the Line

(V

line)

200 Ω Between Tx1 and T

x2

– –79 – dBmp

RECEIVE CHANNEL

Receive Gain from V

line

to VR

x

V

line

= 0.1 Vrms –1.0 0 1.0 dB

Gain Variation with Line Current Referred to

I

line

= 15 mA with the AGC Function Switched “Off”

I

line

= 70 mA,

Bit 0, Reg. 2 = 1

–0.7 – 0.7 dB

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Line Voltage V

I

3.7 4.0 4.3 V

6.6 6.85 7.1

Line Current I

Current Consumption from V

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V

V

–

–

35

3.0

–

4.0

mA

mA

MC34016

4

MOTOROLA ANALOG IC DEVICE DATA

AC ELECTRICAL CHARACTERISTICS (continued)

(All parameters are specified with Bit 0 of Register 1 set to 1, the rest of the

bits in both registers set to 0, TA = 25°C, VCC = 5.0 V, I

line

= 15 mA, f = 1.0 kHz, Test Circuit in Figure 9, unless otherwise noted.)

Parameter UnitMaxTypMinCondition

RECEIVE CHANNEL

Gain Increase in 6.0 dB Mode Bit 5, Reg. 2 = 1 5.3 6.0 6.7 dB
Gain Reduction in Mute Condition Bit 3, Reg. 2 = 1 70 – – dB
Input Impedance at HYL or HYS – – 30 – kΩ
Output Impedance at Rx1 or R

x2

– – 150 – Ω
Maximum Input Swing at HYL or HYS for THD ≤ 2% – 800 – mVpp
Maximum Output Swing VR

x

for THD ≤ 10% – 3.5 – Vpp

Total Harmonic Distortion at VR

x

V

line

= 3.0 dBm – 1.0 2.0 %

Psophometrically Weighted Noise Level at VR

x

200 Ω Between Tx1 and T

x2

– 80 – µVrms

AUTOMATIC GAIN CONTROL

Gain Reduction in Transmit and Receive Channel with

Respect to I

line

= 15 mA

I

line

= 70 mA 5.0 6.0 7.0 dB

Highest Line Current for Maximum Gain – – 20 – mA
Lowest Line Current for Minimum Gain – – 60 – mA
Gain Reduction in Transmit and Receive Channel with

Respect to I

line

= 35 mA

I

line

= 85 mA,

Bit 1, Reg. 2 = 1

5.0 6.0 7.0 dB

Highest Line Current for Maximum Gain Bit 1, Reg. 2 = 1 – 40 – mA
Lowest Line Current for Minimum Gain Bit 1, Reg. 2 = 1 – 80 – mA

BALANCE RETURN LOSS

Balance Return Loss with Respect to 600Ω f = 1.0 kHz 20 – – dB

SIDETONE

Voltage Gain from VTx to VR

x

I

line

= 15 mA,

Bit 0, Reg. 2 = 1

– – –20 dB

SERIAL BUS

Clock Frequency – – – 550 kHz
BEN Rising Edge Setup Time Before First Clk Rising

Edge

See t1 in Timing Diagram 500 – – ns

Data Setup Time Before Clk Rising Edge See t2 in Timing Diagram 500 – – ns
Data Hold Time After Clk Rising Edge See t3 in Timing Diagram 500 – – ns
BEN Falling Edge Delay Time After Last Clk Rising

Edge

See t4 in Timing Diagram 1.5 – – µs

BEN Rising Edge Delay Time After Last BEN Falling

Edge

See t5 in Timing Diagram 6.0 – – µs

Power Supply Reset Voltage V

CC

– – 2.5 – V

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MOTOROLA ANALOG IC DEVICE DATA

PIN FUNCTION DESCRIPTION

Pin Symbol Description

1 Clk Serial bus clock input
2 Data Serial bus data input
3 Out2 Logic output 2
4 Stab Line driver compensation
5 Gnd Ground
6 HKSW Logic output for the hook switch
7 Out1 Logic output 1
8 V

CC

Supply input (+5.0 V)

9 I

ref

Reference current adjustment
10 HYL Hybrid input for long lines
11 HYS Hybrid input for short lines
12 R

x2

Receive output 2
13 R

x1

Receive output 1
14 T

x1

Transmit input 1
15 T

x2

Transmit input 2
16 AGC Automatic gain control input
17 SRF Sidetone reference input
18 LAI Line amplifier input
19 LAO Line amplifier output
20 BEN Serial bus enable input

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