MOTOROLA MC14585BDR2, MC14585BF, MC14585BFR1, MC14585BCP, MC14585BD Datasheet
Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1 Publication Order Number:
MC14585B/D
MC14585B
4-Bit Magnitude
Comparator
The MC14585B 4–Bit Magnitude Comparator is constructed with
complementary MOS (CMOS) enhancement mode devices. The
circuit has eight comparing inputs (A3, B3, A2, B2, A1, B1, A0, B0),
three cascading inputs (A < B, A = B, and A > B), and three outputs (A
< B, A = B, and A > B). This device compares two 4–bit words (A and
B) and determines whether they are “less than”, “equal to”, or “greater
than” by a high level on the appropriate output. For words greater than
4–bits, units can be cascaded by connecting outputs (A > B), (A < B),
and (A = B) to the corresponding inputs of the next significant
comparator. Inputs (A < B), (A = B), and (A > B) on the least
significant (first) comparator are connected to a low , a high, and a low ,
respectively .
Applications include logic in CPU’s, correction and/or detection of
instrumentation conditions, comparator in testers, converters, and
controls.
• Diode Protection on All Inputs
• Expandable
• Applicable to Binary or 8421–BCD Code
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load over the Rated Temperature Range
• Can be Cascaded – See Fig. 3
MAXIMUM RATINGS (Voltages Referenced to V
SS
) (Note 2.)
Symbol Parameter Value Unit
V
DD
DC Supply Voltage Range –0.5 to +18.0 V
Vin, V
out
Input or Output Voltage Range
(DC or Transient)
–0.5 to VDD + 0.5 V
Iin, I
out
Input or Output Current
(DC or Transient) per Pin
±10 mA
P
D
Power Dissipation,
per Package (Note 3.)
500 mW
T
A
Ambient Temperature Range –55 to +125 °C
T
stg
Storage Temperature Range –65 to +150 °C
T
L
Lead Temperature
(8–Second Soldering)
260 °C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C T o 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
v (Vin or V
out
) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or VDD). Unused outputs must be left open.
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A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Device Package Shipping
ORDERING INFORMATION
MC14585BCP PDIP–16 2000/Box
MC14585BD SOIC–16 48/Rail
MC14585BDR2 SOIC–16 2500/Tape & Reel
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
MARKING
DIAGRAMS
1
16
PDIP–16
P SUFFIX
CASE 648
MC14585BCP
AWLYYWW
SOIC–16
D SUFFIX
CASE 751B
1
16
14585B
AWLYWW
SOEIAJ–16
F SUFFIX
CASE 966
1
16
MC14585B
AWLYWW
MC14585BF SOEIAJ–16 See Note 1.
MC14585B
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2
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
(A t B)
out
(A u B)
out
B3
A3
V
DD
B1
A0
B0
(A u B)
in
(A = B)
out
A2
B2
V
SS
A1
(A = B)
in
(A t B)
in
BLOCK DIAGRAM
14
15
1
2
9
7
11
10
5
6
4
13
3
12
V
DD
= PIN 16
V
SS
= PIN 8
(A > B)
in
(A = B)
in
(A < B)
in
A0
B0
A1
B1
A2
B2
A3
B3
(A > B)
out
(A = B)
out
(A < B)
out
TRUTH TABLE (x = Don’t Care)
Inputs
Comparing Cascading
Outputs
A3, B3 A2, B2 A1, B1 A0, B0 A < B A = B A > B A < B A = B A > B
A3 > B3 x x x x x x 0 0 1
A3 = B3 A2 > B2 x x x x x 0 0 1
A3 = B3 A2 = B2 A1 > B1 x x x x 0 0 1
A3 = B3 A2 = B2 A1 = B1 A0 > B0 x x x 0 0 1
A3 = B3 A2 = B2 A1 = B1 A0 = B0 0 0 x 0 0 1
A3 = B3 A2 = B2 A1 = B1 A0 = B0 0 1 x 0 1 0
A3 = B3 A2 = B2 A1 = B1 A0 = B0 1 0 x 1 0 0
A3 = B3 A2 = B2 A1 = B1 A0 = B0 1 1 x 1 1 0
A3 = B3 A2 = B2 A1 = B1 A0 < B0 x x x 1 0 0
A3 = B3 A2 = B2 A1 < B1 x x x x 1 0 0
A3 = B3 A2 < B2 x x x x x 1 0 0
A3 < B3 x x x x x x 1 0 0
MC14585B
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3
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
SS
)
V
– 55_C 25_C 125_C
Characteristic Symbol
V
DD
Vdc
Min Max Min Typ
(4.)
Max Min Max
Unit
Output Voltage “0” Level
V
in
= VDD or 0
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
“1” Level
V
in
= 0 or V
DD
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Input Voltage “0” Level
(V
O
= 4.5 or 0.5 Vdc)
(V
O
= 9.0 or 1.0 Vdc)
(V
O
= 13.5 or 1.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
Vdc
“1” Level
(V
O
= 0.5 or 4.5 Vdc)
(V
O
= 1.0 or 9.0 Vdc)
(V
O
= 1.5 or 13.5 Vdc)
V
IH
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
Vdc
Output Drive Current
(V
OH
= 2.5 Vdc) Source
(V
OH
= 4.6 Vdc)
(V
OH
= 9.5 Vdc)
(V
OH
= 13.5 Vdc)
I
OH
5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
mAdc
(VOL = 0.4 Vdc) Sink
(V
OL
= 0.5 Vdc)
(V
OL
= 1.5 Vdc)
I
OL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
Input Current I
in
15 — ±0.1 — ±0.00001 ±0.1 — ±1.0 µAdc
Input Capacitance
(V
in
= 0)
C
in
— — — — 5.0 7.5 — — pF
Quiescent Current
(Per Package)
I
DD
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
Total Supply Current
(5.) (6.)
(Dynamic plus Quiescent,
Per Package)
(C
L
= 50 pF on all outputs, all
buffers switching)
I
T
5.0
10
15
IT = (0.6 µA/kHz) f + I
DD
IT = (1.2 µA/kHz) f + I
DD
IT = (1.8 µA/kHz) f + I
DD
µAdc
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
5. The formulas given are for the typical characteristics only at 25_C.
6. To calculate total supply current at loads other than 50 pF:
I
T(CL
) = IT(50 pF) + (CL – 50) Vfk
where: I
T
is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.
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