Motorola MC14520BCP, MC14520BDW, MC14518BCL, MC14518BCP, MC14520BCL Datasheet

MOTOROLA CMOS LOGIC DATA

409

MC14518B MC14520B

  

The MC14518B dual BCD counter and the MC14520B dual binary counter
are constructed with MOS P–channel and N–channel enhancement mode
devices in a single m onolithic structure. Each consists of two i dentical,
independent, internally synchronous 4–stage counters. The counter stages
are type D flip–flops, w ith interchangeable Clock and Enable lines f or
incrementing on either the positive–going or negative–going transition as
required when cascading multiple stages. Each counter can be cleared by
applying a high level on the Reset line. In addition, the MC14518B will count
out of all undefined states within two clock periods. These complementary
MOS up counters find primary use in multi–stage synchronous or ripple
counting applications requiring low power dissipation and/or high noise
immunity.

• Diode Protection on All Inputs

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Internally Synchronous for High Internal and External Speeds

• Logic Edge–Clocked Design — Incremented on Positive Transition of

Clock or Negative Transition on Enable

• Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range

MAXIMUM RATINGS* (Voltages Referenced to V

SS

)

Symbol

Parameter Value Unit

V

DD

DC Supply Voltage – 0.5 to + 18.0 V

Vin, V

out

Input or Output Voltage (DC or Transient) 0.5 to VDD + 0.5 V

Iin, I

out

Input or Output Current (DC or Transient),
per Pin

± 10 mA

P

D

Power Dissipation, per Package† 500 mW

T

stg

Storage Temperature – 65 to + 150

_

C

T

L

Lead Temperature (8–Second Soldering) 260

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

TRUTH TABLE

Clock Enable Reset Action

1 0 Increment Counter

0 0 Increment Counter

X 0 No Change

X 0 No Change

0 0 No Change
1 0 No Change
X X 1 Q0 thru Q3 = 0

X = Don’t Care



SEMICONDUCTOR TECHNICAL DATA

 Motorola, Inc. 1995

REV 3
1/94




L SUFFIX

CERAMIC

CASE 620

ORDERING INFORMATION

MC14XXXBCP Plastic
MC14XXXBCL Ceramic
MC14XXXBDW SOIC

TA = – 55° to 125°C for all packages.

P SUFFIX

PLASTIC

CASE 648

DW SUFFIX

SOIC

CASE 751G

This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre­cautions must be taken to avoid applications of
any voltage higher than maximum rated volt­ages to this high–impedance circuit. For proper
operation, Vin and V

out

should be constrained

to the range VSS v (Vin or V

out

) v VDD.

Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either V

SS

or VDD). Unused outputs must be left open.

BLOCK DIAGRAM

VDD = PIN 16

VSS = PIN 8

3
4
5
6

14

13

12

11

C

C

R

R

Q3

Q2

Q1

Q0

Q3

Q2

Q1

Q0

CLOCK

1
2

CLOCK

ENABLE

ENABLE

7

9

10

15

MOTOROLA CMOS LOGIC DATAMC14518B MC14520B

410

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

SS

)

V

– 55_C 25_C 125_C

Characteristic

Symbol

V

DD

Vdc

Min Max Min Typ # Max Min Max

Unit

Output Voltage

“0” Level

Vin = VDD or 0

V

OL

5.0
10
15

—
—
—

0.05

0.05

0.05

—
—
—

0
0
0

0.05

0.05

0.05

—
—
—

0.05

0.05

0.05

Vdc

“1” Level

Vin = 0 or V

DD

V

OH

5.0
10
15

4.95

9.95

14.95

—
—
—

4.95

9.95

14.95

5.0
10
15

—
—
—

4.95

9.95

14.95

—
—
—

Vdc

Input Voltage

“0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)

V

IL

5.0
10
15

—
—
—

1.5

3.0

4.0

—
—
—

2.25

4.50

6.75

1.5

3.0

4.0

—
—
—

1.5

3.0

4.0

Vdc

“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)

V

IH

5.0
10
15

3.5

7.0
11

—
—
—

3.5

7.0
11

2.75

5.50

8.25

—
—
—

3.5

7.0
11

—
—
—

Vdc

Output Drive Current

(VOH = 2.5 Vdc) Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)

I

OH

5.0

5.0
10
15

– 3.0

– 0.64

– 1.6
– 4.2

—
—
—
—

– 2.4

– 0.51

– 1.3
– 3.4

– 4.2
– 0.88
– 2.25

– 8.8

—
—
—
—

– 1.7

– 0.36

– 0.9
– 2.4

—
—
—
—

mAdc

(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)

I

OL

5.0
10
15

0.64

1.6

4.2

—
—
—

0.51

1.3

3.4

0.88

2.25

8.8

—
—
—

0.36

0.9

2.4

—
—
—

mAdc

Input Current I

in

15 — ± 0.1 — ±0.00001 ± 0.1 — ± 1.0 µAdc

Input Capacitance

(Vin = 0)

C

in

— — — — 5.0 7.5 — — pF

Quiescent Current

(Per Package)

I

DD

5.0
10
15

—
—
—

5.0
10
20

—
—
—

0.005

0.010

0.015

5.0
10
20

—
—
—

150
300
600

µAdc

Total Supply Current**†

(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)

I

T

5.0
10
15

IT = (0.6 µA/kHz) f + I

DD

IT = (1.2 µA/kHz) f + I

DD

IT = (1.7 µA/kHz) f + I

DD

µAdc

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL – 50) Vfk

where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

Q1

B

Q2

B

Q3

B

R

B

V

DD

C

B

E

B

Q0

B

Q1

A

Q0

A

E

A

C

A

V

SS

R

A

Q3

A

Q2

A

MOTOROLA CMOS LOGIC DATA

411

MC14518B MC14520B

SWITCHING CHARACTERISTICS* (C

L

= 50 pF, TA = 25_C)

All Types

Characteristic

Symbol

V

DD

Min Typ # Max

Unit

Output Rise and Fall Time

t

TLH

, t

THL

= (1.5 ns/pF) CL + 25 ns

t

TLH

, t

THL

= (0.75 ns/pF) CL + 12.5 ns

t

TLH

, t

THL

= (0.55 ns/pF) CL + 9.5 ns

t

TLH

,

t

THL

5.0
10
15

—
—
—

100

50
40

200
100

80

ns

Propagation Delay Time

Clock to Q/Enable to Q

t

PLH

, t

PHL

= (1.7 ns/pF) CL + 215 ns

t

PLH

, t

PHL

= (0.66 ns/pF) CL + 97 ns

t

PLH

, t

PHL

= (0.5 ns/pF) CL + 75 ns

t

PLH

,

t

PHL

5.0
10
15

—
—
—

280
115

80

560
230
160

ns

Reset to Q

t

PHL

= (1.7 ns/pF) CL + 265 ns

t

PHL

= (0.66 ns/pF) CL + 117 ns

t

PHL

= (0.66 ns/pF) CL + 95 ns

t

PHL

5.0
10
15

—
—
—

330
130

90

650
230
170

ns

Clock Pulse Width t

w(H)

t

w(L)

5.0
10
15

200
100

70

100

50
35

—
—
—

ns

Clock Pulse Frequency f

cl

5.0
10
15

—
—
—

2.5

6.0

8.0

1.5

3.0

4.0

MHz

Clock or Enable Rise and Fall Time t

THL

, t

TLH

5.0
10
15

—
—
—

—
—
—

15

5
4

µs

Enable Pulse Width t

WH(E)

5.0
10
15

440
200
140

220
100

70

—
—
—

ns

Reset Pulse Width t

WH(R)

5.0
10
15

280
120

90

125

55
40

—
—
—

ns

Reset Removal Time t

rem

5.0
10
15

– 5

15
20

– 45
– 15

– 5

—
—
—

ns

*The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

Figure 1. Power Dissipation Test Circuit and Waveform

PULSE

GENERATOR

VARIABLE

WIDTH

C

L

C

L

C

L

C

L

V

DD

V

SS

V

SS

500

µ

F

0.01

µ

F

CERAMIC

20 ns

50%

10%

90%

20 ns

I

D

Q3

Q2

Q1

Q0

C

E
R