The MC145202 is a low–voltage single–package synthesizer with serial
interface capable of direct usage up to 2.0 GHz.
The counters are programmed via a synchronous serial port which is SPI
compatible. The serial port is byte-oriented to facilitate control via an MCU. Due
to the innovative BitGrabber Plus registers, the MC145202 may be cascaded
with other peripherals featuring BitGrabber Plus without requiring leading
dummy bits or address bits in the serial data stream. In addition, BitGrabber
Plus peripherals may be cascaded with existing BitGrabber peripherals.
The device features a single–ended current source/sink phase detector A
output and a double–ended phase detector B output. Both phase detectors
have linear transfer functions (no dead zones). The maximum current of the
single–ended phase detector output is determined by an external resistor tied
from the Rx pin to ground. This current can be varied via the serial port.
Slew–rate control is provided by a special driver designed for the REF
This minimizes interference caused by REF
out
.
This part includes a differential RF input that may be operated in a
single–ended mode. Also featured are on–board support of an external crystal
and a programmable reference output. The R, A, and N counters are fully
programmable. The C register (configuration register) allows the part to be
configured to meet various applications. A patented feature allows the C
register to shut off unused outputs, thereby minimizing system noise and
interference.
In order to have consistent lock times and prevent erroneous data from being
loaded into the counters, on–board circuitry synchronizes the update of the A
register if the A or N counters are loading. Similarly , an update of the R register
is synchronized if the R counter is loading.
The double–buffered R register allows new divide ratios to be presented to
the three counters (R, A, and N) simultaneously .
• Maximum Operating Frequency: 2000 MHz @ – 10 dBm
• Operating Supply Current: 4 mA Nominal at 3.0 V
• Operating Supply Voltage Range (VDD and VCC Pins): 2.7 to 5.5 V
• Operating Supply Voltage Range of Phase Detectors (VPD Pin): 2.7 to 5.5 V
• Current Source/Sink Phase Detector Output Capability: 1.7 mA @ 5.0 V
1.0 mA @ 3.0 V
• Gain of Current Source/Sink Phase/Frequency Detector Controllable via
Serial Port
• Operating Temperature Range: – 40 to + 85°C
• R Counter Division Range: 1 and 5 to 8191
• Dual–Modulus Capability Provides Total Division up to 262,143
• High–Speed Serial Interface: 4 Mbps
• OUTPUT A Pin, When Configured as Data Out, Permits Cascading of Devices
• Two General–Purpose Digital Outputs — OUTPUT A: Totem–Pole (Push–Pull)
with Four Output Modes
OUTPUT B: Open–Drain
• Patented Power–Saving Standby Feature with Orderly Recovery for
Minimizing Lock Times, Standby Current: 30 µA
• Evaluation Kit Available (Part Number MC145202EVK)
• See Application Note AN1253/D for Low–Pass Filter Design, and
AN1277/D for Offset Reference PLLs for Fine Resolution or Fast Hopping
BitGrabber and BitGrabber Plus are trademarks of Motorola, Inc.
REV 3
1/98 TN98012300
out
pin.
20
1
20
1
SOG PACKAGE
CASE 751J
DT SUFFIX
CASE 948D
ORDERING INFORMATION
MC145202FSOG Package
MC145202DTTSSOP
PIN ASSIGNMENT
REF
out
LD
φ
R
φ
V
V
PD
PD
out
GND
Rx
TEST 1
f
in
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
1110
F SUFFIX
TSSOP
REF
in
D
in
CLK
ENB
OUTPUT A
OUTPUT B
V
DD
TEST 2
V
CC
f
in
Motorola, Inc. 1998
MC145202MOTOROLA
1
REF
REF
out
BLOCK DIAGRAM
DATA OUT
20
in
1
OSC OR
4–STAGE
DIVIDER
(CONFIGURABLE)
3
13–STAGE R COUNTER
13
DOUBLE–BUFFERED
BitGrabber
R REGISTER
16 BITS
f
R
PORT
f
V
LOCK DETECTOR
AND CONTROL
SELECT
LOGIC
16
OUTPUT A
2
LD
CLK
D
in
ENB
f
in
f
in
18
19
17
11
10
REGISTER
CONTROL
INTERNAL
CONTROL
INPUT
AMP
SHIFT
AND
LOGIC
8
Rx
BitGrabber
24
STANDBY
LOGIC
BitGrabber
4
6–STAGE
A COUNTER
64/65
PRESCALER
C REGISTER
8 BITS
POR
2
A REGISTER
24 BITS
612
12–STAGE
N COUNTER
MODULUS
CONTROL
LOGIC
PHASE/FREQUENCY
DETECTOR A AND CONTROL
PHASE/FREQUENCY
DETECTOR B AND CONTROL
15
13
9
6
PD
out
3
φ
R
4
φ
V
OUTPUT B
(OPEN–
DRAIN
OUTPUT)
TEST 2
TEST 1
SUPPLY CONNECTIONS:
PIN 12 = VCC (V+ TO INPUT AMP AND 64/65 PRESCALER)
PIN 5 = VPD (V+ TO PHASE/FREQUENCY DETECTORS A AND B)
PIN 14 = VDD (V+ TO BALANCE OF CIRCUIT)
PIN 7 = GND (COMMON GROUND)
MC145202MOTOROLA
2
MAXIMUM RATINGS* (Voltages Referenced to GND, unless otherwise stated)
SymbolParameterValueUnit
VCC, V
V
PD
V
in
V
out
V
out
Iin, I
I
out
I
DD
P
D
T
stg
T
L
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the limits in the Electrical Characteristics
tables or Pin Descriptions section.
DC Supply Voltage (Pins 12 and 14)– 0.5 to + 6.0V
DD
DC Supply Voltage (Pin 5)VDD – 0.5 to + 6.0V
DC Input Voltage– 0.5 to VDD + 0.5V
DC Output Voltage (except OUTPUT B,
PD
, φR, φV)
out
DC Output Voltage (OUTPUT B, PD
φR, φV)
DC Input Current, per Pin (Includes
PD
VPD)
DC Output Current, per Pin± 20mA
DC Supply Current, VDD and GND Pins± 30mA
Power Dissipation, per Package300mW
Storage Temperature– 65 to + 150°C
Lead Temperature, 1 mm from Case for
10 Seconds
– 0.5 to VDD + 0.5V
,
– 0.5 to VPD + 0.5V
out
± 10mA
260°C
This device contains protection circuitry to
guard against damage due to high static voltages or electric fields. However, precautions
must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high–impedance circuit.
ELECTRICAL CHARACTERISTICS
(VDD = VCC = 2.7 to 5.5 V , Voltages Referenced to GND, unless otherwise stated; VPD = 2.7 to 5.5 V, TA = – 40 to 85°C)
Symbol
V
IL
V
IH
V
Hys
V
OL
V
OH
I
OL
I
OL
I
OL
I
OL
I
OH
I
OH
I
OH
Maximum Low–Level Input Voltage
(Din, CLK, ENB
Minimum High–Level Input Voltage
(Din, CLK, ENB
Minimum Hysteresis Voltage (CLK, ENB)VDD = 2.7 V
Maximum Low–Level Output Voltage
(REF
out
Minimum High–Level Output Voltage
(REF
out
Minimum Low–Level Output Current
(REF
out
Minimum Low–Level Output Current
(φR, φV)
Minimum Low–Level Output Current
(OUTPUT A)
Minimum Low–Level Output Current
(OUTPUT B)
Minimum High–Level Output Current
(REF
out
Minimum High–Level Output Current
(φR, φV)
Minimum High–Level Output Current
(OUTPUT A Only)
ParameterTest Condition
)
)
VDD = 4.5 V
I
= 20 µA, Device in Reference Mode0.1V
, OUTPUT A)
, OUTPUT A)
, LD)
, LD)
out
I
= – 20 µA, Device in Reference ModeVDD – 0.1V
out
V
= 0.3 V0.36mA
out
V
= 0.3 V0.36mA
out
V
= 0.4 V
out
VDD = 4.5 V
V
= 0.4 V1.0mA
out
V
= VDD – 0.3 V– 0.36mA
out
V
= VPD – 0.3 V– 0.36mA
out
V
= VDD – 0.4 V
out
VDD = 4.5 V
Guaranteed
Limit
0.3 x V
DD
0.7 x V
DD
100
250
1.0mA
– 0.6mA
(continued)
Unit
V
V
mV
MC145202MOTOROLA
3
ELECTRICAL CHARACTERISTICS (continued)
Symbol
I
Maximum Input Leakage Current
in
I
in
I
OZ
I
STBY
I
PD
I
T
*The nominal values are:
4 mA at VDD = 3.0 V and VPD = 3.0 V
6 mA at VDD = 5.0 V and VPD = 5.0 V
These are not guaranteed limits.
(Din, CLK, ENB
Maximum Input Current
(REFin)
Maximum Output Leakage Current (PD
Maximum Standby Supply Current
(VDD + VPD Pins)
Maximum Phase Detector
Quiescent Current (VPD Pin)
Total Operating Supply Current
(VDD + VPD + VCC Pins)
ParameterTest Condition
, REFin)
(OUTPUT B) V
Guaranteed
Limit
Vin = VDD or GND, Device in XTAL Mode± 1.0µA
Vin = VDD or GND, Device in Reference Mode± 100µA
) V
out
= VPD or GND, Output in Floating State± 130nA
out
= VPD or GND, Output in High–Impedance State± 1µA
out
Vin = VDD or GND; Outputs Open; Device in Standby Mode,
Shut–Down Crystal Mode or REF
Mode; OUTPUT B Controlling VCC per Figure 21
Bit C6 = High Which Selects Phase Detector A,
PD
= Open, PD
out
not
Standby, IRx = 170 µA, VPD = 5.5 V
Bit C6 = Low Which Selects Phase Detector B, φR and
φV = Open, φR and φV = Static Low or High, Bit
C4 = Low Which is
fin = 2.0 GHz; REFin = 13 MHz @ 1 Vp–p;
OUTPUT A = Inactive and No Connect; VDD = VCC,
REF
, φV, φR, PD
out
Din, ENB
(Bit C6 = Low)
, CLK = VDD or GND, Phase Detector B Selected
= Static State, Bit C4 = Low Which is
out
not
Standby
, LD = No Connect;
out
–Static–Low Reference
out
Unit
30µA
750µA
30
*
mA
ANALOG CHARACTERISTICS — CURRENT SOURCE/SINK OUTPUT — PD
(I
≤ 1 mA @ VDD = 2.7 V and I
out
Parameter
Maximum Source Current Variation (Part–to–Part)V
Maximum Sink–vs–Source Mismatch (Note 3)V
Output Voltage Range (Note 3)I
NOTES:
1. Percentages calculated using the following formula: (Maximum Value – Minimum Value)/Maximum Value.
2. See Rx Pin Description for external resistor values.
3. This parameter is guaranteed for a given temperature within – 40 to + 85°C.
≤ 1.7mA @ VDD ≥ 4.5 V, VDD = VCC = 2.7 to 5.5 V, Voltages Referenced to GND)
out
Test ConditionV
= 0.5 x V
out
= 0.5 x V
out
PD
PD
out
Variation ≤ 15%2.70.5 to 2.2V
out
I
Variation ≤ 20%4.50.5 to 3.7
out
I
Variation ≤ 22%5.50.5 to 4.7
out
Guaranteed
PD
2.7± 15%
4.5± 15
5.5± 15
2.711%
4.511
5.511
Limit
Unit
MC145202MOTOROLA
4
AC INTERFACE CHARACTERISTICS
(VDD = VCC = 2.7 to 5.5 V, TA = – 40 to + 85°C, CL = 25 pF, Input tr = tf = 10 ns; VPD = 2.7 to 5.5 V)
Symbol
f
t
PLH
t
PLH
t
PZL
t
TLH
C
clk
, t
, t
, t
, t
Serial Data Clock Frequency (Note: Refer to Clock tw below)1dc to 4.0MHz
Maximum Propagation Delay, CLK to OUTPUT A (Selected as Data Out)1, 5100ns
PHL
Maximum Propagation Delay, ENB to OUTPUT A (Selected as Port)2, 5150ns
PHL
Maximum Propagation Delay, ENB to OUTPUT B2, 6150ns
PLZ
Maximum Output Transition Time, OUTPUT A and OUTPUT B; t
THL
Maximum Input Capacitance – Din, ENB, CLK10pF
in
Parameter
only, on OUTPUT B1, 5, 650ns
THL
TIMING REQUIREMENTS
(VDD = VCC = 2.7 to 5.5 V, TA = – 40 to + 85°C, Input tr = tf = 10 ns, unless otherwise indicated)
Symbol
tsu, t
tsu, th, t
t
w
t
w
tr, t
*The minimum limit is 3 REFin cycles or 195 fin cycles, whichever is greater.
Minimum Setup and Hold Times, Din vs CLK350ns
h
Minimum Setup, Hold and Recovery Times, ENB vs CLK4100ns
rec
Minimum Pulse Width, ENB4
Minimum Pulse Width, CLK1125ns
Maximum Input Rise and Fall Times, CLK1100µs