Motorola MC145202DT, MC145202F Datasheet

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SEMICONDUCTOR TECHNICAL DATA

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Includes On–Board 64/65 Prescaler

The MC145202 is a low–voltage single–package synthesizer with serial

interface capable of direct usage up to 2.0 GHz.

The counters are programmed via a synchronous serial port which is SPI compatible. The serial port is byte-oriented to facilitate control via an MCU. Due to the innovative BitGrabber Plus registers, the MC145202 may be cascaded with other peripherals featuring BitGrabber Plus without requiring leading dummy bits or address bits in the serial data stream. In addition, BitGrabber Plus peripherals may be cascaded with existing BitGrabber peripherals.

The device features a single–ended current source/sink phase detector A output and a double–ended phase detector B output. Both phase detectors have linear transfer functions (no dead zones). The maximum current of the single–ended phase detector output is determined by an external resistor tied from the Rx pin to ground. This current can be varied via the serial port.

Slew–rate control is provided by a special driver designed for the REF This minimizes interference caused by REF

out

.

This part includes a differential RF input that may be operated in a single–ended mode. Also featured are on–board support of an external crystal and a programmable reference output. The R, A, and N counters are fully programmable. The C register (configuration register) allows the part to be configured to meet various applications. A patented feature allows the C register to shut off unused outputs, thereby minimizing system noise and interference.

In order to have consistent lock times and prevent erroneous data from being loaded into the counters, on–board circuitry synchronizes the update of the A register if the A or N counters are loading. Similarly , an update of the R register is synchronized if the R counter is loading.

The double–buffered R register allows new divide ratios to be presented to the three counters (R, A, and N) simultaneously .

• Maximum Operating Frequency: 2000 MHz @ – 10 dBm

• Operating Supply Current: 4 mA Nominal at 3.0 V

• Operating Supply Voltage Range (VDD and VCC Pins): 2.7 to 5.5 V

• Operating Supply Voltage Range of Phase Detectors (VPD Pin): 2.7 to 5.5 V

• Current Source/Sink Phase Detector Output Capability: 1.7 mA @ 5.0 V

1.0 mA @ 3.0 V

• Gain of Current Source/Sink Phase/Frequency Detector Controllable via

Serial Port

• Operating Temperature Range: – 40 to + 85°C

• R Counter Division Range: 1 and 5 to 8191

• Dual–Modulus Capability Provides Total Division up to 262,143

• High–Speed Serial Interface: 4 Mbps

• OUTPUT A Pin, When Configured as Data Out, Permits Cascading of Devices

• Two General–Purpose Digital Outputs — OUTPUT A: Totem–Pole (Push–Pull)

with Four Output Modes

OUTPUT B: Open–Drain

• Patented Power–Saving Standby Feature with Orderly Recovery for

Minimizing Lock Times, Standby Current: 30 µA

• Evaluation Kit Available (Part Number MC145202EVK)

• See Application Note AN1253/D for Low–Pass Filter Design, and

AN1277/D for Offset Reference PLLs for Fine Resolution or Fast Hopping

BitGrabber and BitGrabber Plus are trademarks of Motorola, Inc.

REV 3 1/98 TN98012300

out

pin.

20

1

20

1

SOG PACKAGE

CASE 751J

DT SUFFIX

CASE 948D

ORDERING INFORMATION

MC145202F SOG Package MC145202DT TSSOP

PIN ASSIGNMENT

REF

out

LD

φ

R

φ

V

PD

out

GND

Rx

TEST 1

f

in

1 2 3 4 5 6 7 8 9

20 19 18 17

16 15 14

13 12

1110

F SUFFIX

TSSOP

REF

in

D

in

CLK ENB OUTPUT A OUTPUT B V

DD

TEST 2 V

CC

f

in

 Motorola, Inc. 1998

MC145202MOTOROLA

1

REF

out

BLOCK DIAGRAM

DATA OUT

20

in

1

OSC OR

4–STAGE

DIVIDER

(CONFIGURABLE)

3

13–STAGE R COUNTER

13

DOUBLE–BUFFERED

BitGrabber



R REGISTER

16 BITS

f

R

PORT

f

V

LOCK DETECTOR

AND CONTROL

SELECT

LOGIC

16

OUTPUT A

2

LD

CLK

D

in

ENB

f

in

f

in

18

19

17

11

10

REGISTER

CONTROL

INTERNAL CONTROL

INPUT AMP

SHIFT

AND

LOGIC

8

Rx



BitGrabber

24

STANDBY

LOGIC

BitGrabber

4

6–STAGE

A COUNTER

64/65

PRESCALER

C REGISTER

8 BITS

POR

2



A REGISTER

24 BITS

6 12

12–STAGE

N COUNTER

MODULUS CONTROL

LOGIC

PHASE/FREQUENCY

DETECTOR A AND CONTROL

PHASE/FREQUENCY

DETECTOR B AND CONTROL

15

13

9

6

PD

out

3

φ

R

4

φ

V

OUTPUT B (OPEN– DRAIN OUTPUT)

TEST 2

TEST 1

SUPPLY CONNECTIONS:

PIN 12 = VCC (V+ TO INPUT AMP AND 64/65 PRESCALER) PIN 5 = VPD (V+ TO PHASE/FREQUENCY DETECTORS A AND B) PIN 14 = VDD (V+ TO BALANCE OF CIRCUIT) PIN 7 = GND (COMMON GROUND)

MC145202 MOTOROLA 2

MAXIMUM RATINGS* (Voltages Referenced to GND, unless otherwise stated)

Symbol Parameter Value Unit

VCC, V

V

PD

V

in

V

out

V

out

Iin, I

I

out

I

DD P

D

T

stg

T

L

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Descriptions section.

DC Supply Voltage (Pins 12 and 14) – 0.5 to + 6.0 V

DD

DC Supply Voltage (Pin 5) VDD – 0.5 to + 6.0 V DC Input Voltage – 0.5 to VDD + 0.5 V DC Output Voltage (except OUTPUT B,

PD

, φR, φV)

out

DC Output Voltage (OUTPUT B, PD

φR, φV)

DC Input Current, per Pin (Includes

PD

VPD) DC Output Current, per Pin ± 20 mA DC Supply Current, VDD and GND Pins ± 30 mA Power Dissipation, per Package 300 mW Storage Temperature – 65 to + 150 °C Lead Temperature, 1 mm from Case for

10 Seconds

– 0.5 to VDD + 0.5 V

,

– 0.5 to VPD + 0.5 V

out

± 10 mA

260 °C

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit.

ELECTRICAL CHARACTERISTICS

(VDD = VCC = 2.7 to 5.5 V , Voltages Referenced to GND, unless otherwise stated; VPD = 2.7 to 5.5 V, TA = – 40 to 85°C)

Symbol

V

IL

V

IH

V

Hys

V

OL

V

OH

I

OL

I

OL

I

OL

I

OL

I

OH

I

OH

I

OH

Maximum Low–Level Input Voltage

(Din, CLK, ENB

Minimum High–Level Input Voltage

(Din, CLK, ENB

Minimum Hysteresis Voltage (CLK, ENB) VDD = 2.7 V

Maximum Low–Level Output Voltage

(REF

out

Minimum High–Level Output Voltage

(REF

out

Minimum Low–Level Output Current

(REF

out

Minimum Low–Level Output Current

(φR, φV)

Minimum Low–Level Output Current

(OUTPUT A)

Minimum Low–Level Output Current

(OUTPUT B)

Minimum High–Level Output Current

(REF

out

Minimum High–Level Output Current

(φR, φV)

Minimum High–Level Output Current

(OUTPUT A Only)

Parameter Test Condition

)

VDD = 4.5 V I

= 20 µA, Device in Reference Mode 0.1 V

, OUTPUT A)

, LD)

out

I

= – 20 µA, Device in Reference Mode VDD – 0.1 V

out

V

= 0.3 V 0.36 mA

out

V

= 0.3 V 0.36 mA

out

V

= 0.4 V

out

VDD = 4.5 V V

= 0.4 V 1.0 mA

out

V

= VDD – 0.3 V – 0.36 mA

out

V

= VPD – 0.3 V – 0.36 mA

out

V

= VDD – 0.4 V

out

VDD = 4.5 V

Guaranteed

Limit

0.3 x V

DD

0.7 x V

DD

100 250

1.0 mA

– 0.6 mA

(continued)

Unit

V

mV

MC145202MOTOROLA

3

ELECTRICAL CHARACTERISTICS (continued)

Symbol

I

Maximum Input Leakage Current

in

I

in

I

OZ

I

STBY

I

PD

I

T

*The nominal values are:

4 mA at VDD = 3.0 V and VPD = 3.0 V 6 mA at VDD = 5.0 V and VPD = 5.0 V

These are not guaranteed limits.

(Din, CLK, ENB

Maximum Input Current

(REFin)

Maximum Output Leakage Current (PD

Maximum Standby Supply Current

(VDD + VPD Pins)

Maximum Phase Detector

Quiescent Current (VPD Pin)

Total Operating Supply Current

(VDD + VPD + VCC Pins)

Parameter Test Condition

, REFin)

(OUTPUT B) V

Guaranteed

Limit

Vin = VDD or GND, Device in XTAL Mode ± 1.0 µA

Vin = VDD or GND, Device in Reference Mode ± 100 µA

) V

out

= VPD or GND, Output in Floating State ± 130 nA

out

= VPD or GND, Output in High–Impedance State ± 1 µA

out

Vin = VDD or GND; Outputs Open; Device in Standby Mode, Shut–Down Crystal Mode or REF Mode; OUTPUT B Controlling VCC per Figure 21

Bit C6 = High Which Selects Phase Detector A, PD

= Open, PD

out

not

Standby, IRx = 170 µA, VPD = 5.5 V

Bit C6 = Low Which Selects Phase Detector B, φR and

φV = Open, φR and φV = Static Low or High, Bit

C4 = Low Which is fin = 2.0 GHz; REFin = 13 MHz @ 1 Vp–p;

OUTPUT A = Inactive and No Connect; VDD = VCC, REF

, φV, φR, PD

out

Din, ENB (Bit C6 = Low)

, CLK = VDD or GND, Phase Detector B Selected

= Static State, Bit C4 = Low Which is

out

not

Standby

, LD = No Connect;

out

–Static–Low Reference

out

Unit

30 µA

750 µA

30

*

mA

ANALOG CHARACTERISTICS — CURRENT SOURCE/SINK OUTPUT — PD

(I

≤ 1 mA @ VDD = 2.7 V and I

out

Parameter

Maximum Source Current Variation (Part–to–Part) V

Maximum Sink–vs–Source Mismatch (Note 3) V

Output Voltage Range (Note 3) I

NOTES:

1. Percentages calculated using the following formula: (Maximum Value – Minimum Value)/Maximum Value.

2. See Rx Pin Description for external resistor values.

3. This parameter is guaranteed for a given temperature within – 40 to + 85°C.

≤ 1.7mA @ VDD ≥ 4.5 V, VDD = VCC = 2.7 to 5.5 V, Voltages Referenced to GND)

out

Test Condition V

= 0.5 x V

out

= 0.5 x V

out

PD

out

Variation ≤ 15% 2.7 0.5 to 2.2 V

out

I

Variation ≤ 20% 4.5 0.5 to 3.7

out

I

Variation ≤ 22% 5.5 0.5 to 4.7

out

Guaranteed

PD

2.7 ± 15 %

4.5 ± 15

5.5 ± 15

2.7 11 %

4.5 11

5.5 11

Limit

Unit

MC145202 MOTOROLA 4

AC INTERFACE CHARACTERISTICS

(VDD = VCC = 2.7 to 5.5 V, TA = – 40 to + 85°C, CL = 25 pF, Input tr = tf = 10 ns; VPD = 2.7 to 5.5 V)

Symbol

f

t

PLH

t

PLH

t

PZL

t

TLH

C

clk

, t , t , t , t

Serial Data Clock Frequency (Note: Refer to Clock tw below) 1 dc to 4.0 MHz Maximum Propagation Delay, CLK to OUTPUT A (Selected as Data Out) 1, 5 100 ns

PHL

Maximum Propagation Delay, ENB to OUTPUT A (Selected as Port) 2, 5 150 ns

PHL

Maximum Propagation Delay, ENB to OUTPUT B 2, 6 150 ns

PLZ

Maximum Output Transition Time, OUTPUT A and OUTPUT B; t

THL

Maximum Input Capacitance – Din, ENB, CLK 10 pF

in

Parameter

only, on OUTPUT B 1, 5, 6 50 ns

THL

TIMING REQUIREMENTS

(VDD = VCC = 2.7 to 5.5 V, TA = – 40 to + 85°C, Input tr = tf = 10 ns, unless otherwise indicated)

Symbol

tsu, t

tsu, th, t

t

w

t

w

tr, t

*The minimum limit is 3 REFin cycles or 195 fin cycles, whichever is greater.

Minimum Setup and Hold Times, Din vs CLK 3 50 ns

h

Minimum Setup, Hold and Recovery Times, ENB vs CLK 4 100 ns

rec

Minimum Pulse Width, ENB 4 Minimum Pulse Width, CLK 1 125 ns Maximum Input Rise and Fall Times, CLK 1 100 µs

f

Parameter

Figure

No.

Figure

No.

Guaranteed

Limit

Guaranteed

Limit

*

Unit

cycles

MC145202MOTOROLA

5

SWITCHING WAVEFORMS

CLK

OUTPUT A

(DATA OUT)

D

in

CLK

90%

50%

10%

50%

10%

90%

t

f

t

w

t

PLH

t

TLH

1/f

clk

t

r

t

w

t

PHL

t

THL

V

DD

GND

ENB

OUTPUT A

OUTPUT B

50%

Figure 1. Figure 2.

50%

VALID

V

DD

GND

t

su

50%

t

h

V

DD

GND

ENB

CLK

50%

t

su

50%

FIRST

CLK

t

w

10%

t

PLHtPHL

50%

t

PLZ

LAST

CLK

t

PZL

t

h

V

DD

GND

50%

t

w

t

rec

V

DD

GND

V

DD

GND

Figure 3. Figure 4.

TEST POINT

DEVICE

UNDER

TEST

*Includes all probe and fixture capacitance.

*

C

L

Figure 5. Figure 6.

7.5 k

C

+V

Ω

*

L

TEST POINT

DEVICE UNDER

TEST

*Includes all probe and fixture capacitance.

PD

MC145202 MOTOROLA 6

LOOP SPECIFICATIONS (V

Fig

Symbol Parameter Test Condition

P

Input Sensitivity Range, f

in

f

Input Frequency, REFin Externally Driven in

ref

Reference Mode

f

XTAL

f

t

TLH

t

THL

*Power level at the input to the dc block.

**When PD

Crystal Frequency, Crystal Mode C1 ≤ 30 pF, C2 ≤ 30 pF, Includes Stray

Output Frequency, REF

out

f Operating Frequency of the Phase Detectors dc 2 MHz

t

Output Pulse Width (φR, φV, and LD) fR in Phase with fV, CL = 20 pF, φR and φ

w

,

Output Transition Times (LD, φV, and φR) CL = 20 pF, VPD = 2.7 V,

C

Input Capacitance, REF

in

is active, LD minimum pulse width is approximately 5 ns.

out

= VCC = 2.7 to 5.5 V unless otherwise indicated, TA = – 40 to + 85°C)

DD

in

out

in

500 MHz ≤ fin ≤ 2000 MHz 7 – 10 4 dBm* Vin ≥ 400 mV p–p 2.7 ≤ VDD < 4.5 V

Capacitance CL = 20 pF, V

active for LD measurement, ** VPD = 2.7 to 5.5 V VDD = 2.7 V

VDD = VCC = 2.7 V

≥ 1 V p–p 10, 12 dc 10 MHz

out

4.5 ≤ VDD ≤ 5.5 V

VDD = 4.5 V VDD = 5.5 V

Guaranteed

Operating

.

No.

8 1.5

9 2 15 MHz

11, 12

V

11, 12 — 80 ns

Range

Min Max

1.5

40 18 14

— 7 pF

20 30

120

60 50

Unit

MHz

ns

SINE WAVE

GENERATOR

50

NOTE: Alternately, the 50 Ω pad may be a T network.

50

Ω

PAD

Ω

DC

BLOCK

f

in

f

in

V

CC

OUTPUT A

DEVICE UNDER

TEST

GND

Figure 7. T est Circuit

TEST

POINT

(fR)

V+

C1

C2

REF

OUTPUT A

in

DEVICE UNDER

TEST

REF

out

V

CC

GND

V

DD

Figure 9. T est Circuit — Crystal Mode

TEST

POINT

(fV)

V

DD

V+

SINE WAVE

GENERATOR

50

0.01

µ

F

REF

OUTPUT A

in

DEVICE

V

CC

UNDER

TEST

REF

GND

out

V

DD

V

in

Ω

(fR)

TEST

POINT

TEST

POINT

V+

Figure 8. T est Circuit — Reference Mode

1/f REF

out

REF

out

50%

Figure 10. Switching Waveform

TEST POINT

OUTPUT

t

w

90%

50%

10%

t

THL

Figure 11. Switching Waveform

t

TLH

DEVICE

UNDER

TEST

CL*

*Includes all probe and

fixture capacitance.

Figure 12. T est Circuit

MC145202MOTOROLA

7

fin (PIN 11) SOG PACKAGE

4

1

3

1

3

2

Figure 13. Normalized Input Impedance at fin — Series Format (R + jx)

T able 1. Input Impedence at fin — Series Format (R + jx), VCC = 3 V

Frequency

Marker

1 0.5 11.4 – 168 1.9 pF 2 1 12.4 – 59.4 2.68 pF 3 1.5 19.8 – 34.9 3.04 pF 4 2 18.1 9.43 751 pH

(GHz)

Resistance

(Ω)

Reactance

(Ω)

Capacitance/

Inductance

T able 2. Input Impedence at fin — Series Format (R + jx), VCC = 5 V

Frequency

Marker

1 0.5 11.8 –175 1.82 pF 2 1 11.5 – 64.4 2.47 pF 3 1.5 22.2 – 36.5 2.91 pF 4 2 18.4 1.14 90.4 pH

(GHz)

Resistance

(Ω)

Reactance

(Ω)

Capacitance/

Inductance

3 V 5 V

MC145202 MOTOROLA 8