MOTOROLA CMOS LOGIC DATAMC14500B
306
The M C14500B I ndustrial C ontrol Unit (ICU) i s a single–bit C MOS
processor. The ICU is designed for use in systems requiring decisions based
on successive single–bit information. An external ROM stores the control
program. With a program counter (and output latches and input multiplexers,
if required) the ICU in a system forms a stored–program controller that
replaces combinatorial logic. Applications include relay logic processing,
serial data manipulation and control. The ICU also may control an MPU or be
controlled by an MPU.
• 16 Instructions
• DC to 1.0 MHz Operation at VDD = 5 V
• On–Chip Clock (Oscillator)
• Executes One Instruction per Clock Cycle
• 3 to 18 V Operation
• Low Quiescent Current Characteristic of CMOS Devices
• Capable of Driving One Low–Power Schottky Load or Two Low–Power
TTL Loads over Full Temperature Range
BLOCK DIAGRAM
DATA
X1
X2
I0
I1
I2
I3
RST
3
14
13
7
6
5
4
1
INST
REG
OSC
D
C
IEN
LU
D
C
RESULT
REG. (RR)
MUX
D
C
16
2
8
WRITE
V
DD
V
SS
15
12
11
10
9
RR
JMP
RTN
FLAG O
FLAG F
+V
OEN
STOC
STO
X1 — OSCILLATOR OUTPUT
X2 — OSCILLATOR INPUT
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
REV 3
1/94
L SUFFIX
CERAMIC
CASE 620
ORDERING INFORMATION
TA = – 55° to 125°C for all packages.
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G
PIN ASSIGNMENT
MC14XXXBCP Plastic
MC14XXXBCL Ceramic
MC14XXXBDW SOIC
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
JMP
X2
X1
V
DD
FLAG F
FLAG O
RTN
I3
DATA
WRITE
RST
V
SS
I0
I1
I2
RR
MOTOROLA CMOS LOGIC DATA
307
MC14500B
MAXIMUM RATINGS* (Voltages Referenced to V
SS
)
Input or Output Voltage (DC or Transient)
Input or Output Current (DC or Transient),
per Pin
Power Dissipation, per Package†
Lead Temperature (8–Second Soldering)
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
SS
)
“1” Level
Vin = 0 or V
DD
“0” Level
RST, D, X2
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
“0” Level
I0, I1, I2, I3
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
Output Drive Current Source
Data, Write
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Output Drive Current Source
Other Outputs
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
– 4.2
– 0.88
– 2.25
– 8.8
(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
mAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, precautions must be taken to avoid applications of
any voltage higher than maximum rated voltages to this high–impedance circuit. For proper
operation, Vin and V
out
should be constrained
to the range VSS v (Vin or V
out
) v VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either V
SS
or VDD). Unused outputs must be left open.
MOTOROLA CMOS LOGIC DATAMC14500B
308
ELECTRICAL CHARACTERISTICS — continued (Voltages Referenced to V
SS
)
Input Capacitance (All Other Inputs)
Quiescent Current
(Per Package) I
out
= 0 µA,
Vin = 0 or V
DD
**Total Supply Current at an
External Load Capacitance (CL)
on All Outputs
IT = (1.5 µA/kHz) f + I
DD
IT = (3.0 µA/kHz) f + I
DD
IT = (4.5 µA/kHz) f + I
DD
µAdc
**The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
SWITCHING CHARACTERISTICS* (T
A
= 25_C; tr = tf = 20 ns for X and I inputs; CL = 50 pF for JMP, X1, RR, Flag O, Flag F;
CL = 130 pF + 1 TTL load for Data and Write.)
ОООООООООО
ОООООООООО
ОООООООООО
Propagation Delay Time, X1 to RR
X1 to Flag F, Flag O, RTN, JMP
RST to Flag F, Flag O, RTN, JMP
NOTE 1. Maximum Reset Delay may extend to one–half clock period.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.