Motorola MC14415VP, MC14415FP, MC14415DW, MC14415FL, MC14415VL Datasheet

MOTOROLA CMOS LOGIC DATAMC14415

290

  

MC14415 quad t imer/driver is constructed w ith complementary MOS
enhancement mode devices. The output pulse width of each digital timer is
a function of the input clock frequency. Once the proper input sequence is
detected the output buffer is set (turned on), and after 100 clock pulses are
counted, the output buffer is reset (turned off).

The MC14415 was designed specifically for application in high speed line
printers to provide the critical timing of the hammer drivers, but may be used
in many applications requiring precision pulse widths.

• Four Precision Digital Time Delays

• Schmitt Trigger Clock Conditioning

• NPN Bipolar Output Drivers

• Timing Disable Capability Using Inhibit Output

• Positive or Negative Edge Strobing on the Inputs

• Synchronous Polynomial Counters Used for Delay Counting

MAXIMUM RATINGS* (Voltages Referenced to V

SS

)

Rating

Symbol

Value

Unit

DC Supply Voltage MC14415FL, FP,DW

MC14415VL, VP

V

DD

– 0.5 to + 18.0

– 0.5 to + 6.0

V

Input or Output Voltage (DC or Transient)

Vin, V

out

– 0.5 to VDD + 0.5

V

Input Current (DC or Transient), per Pin

I

in

± 10

mA

Output Current (DC or Transient), per Pin

I

out

± 20

mA

Power Dissipation, per Package†

P

D

500

mW

Storage Temperature

T

stg

– 65 to + 150

_

C

Lead Temperature (8–Second Soldering)

T

L

260

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

BLOCK DIAGRAM

OUTPUT INHIBIT 15

11 OUTPUT D

CLOCK 1

OUTPUT SET

2

INPUT DISABLE 10

STROBE 1 7

STROBE 2 9

SET D 6

SET C 5

SET B 4

SET A 3

12 OUTPUT C

13 OUTPUT B

14 OUTPUT A

VDD = PIN 16

VSS = PIN 8

INPUT
LOGIC

DIVIDE–BY–

100

COUNTERS

OUTPUT

BUFFERS

COMMON

LOGIC

CLOCK

CONDITIONING

CIRCUIT



SEMICONDUCTOR TECHNICAL DATA

 Motorola, Inc. 1995

REV 3
1/94



L SUFFIX

CERAMIC

CASE 620

ORDERING INFORMATION

MC14415FP (3.0 V–18 V) Plastic
MC14415VP (3.0 V–6.0 V) Plastic
MC14415FL (3.0 V–18 V) Ceramic
MC14415VL (3.0 V–6.0 V) Ceramic
MC14415DW (3.0 V–18 V) SOIC

TA = – 55° to 125°C for all packages.

P SUFFIX

PLASTIC

CASE 648

DW SUFFIX

SOIC

CASE 751G

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

OUT C

OUT B

OUT A

V

DD

ST2

DIS

OUT D

SET B

SET A

SET

CLOCK

V

SS

ST

1

SET D

SET C

INH

MOTOROLA CMOS LOGIC DATA

291

MC14415

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

SS

)

V

– 55_C

25_C

125_C

Characteristic

Symbol

V

DD

Vdc

Min

Max

Min

Typ #

Max

Min

ÎÎÎ

ÎÎÎ

ÎÎÎ

Max

Unit

Output Voltage

“0” Level

(No Load)

V

OL

5.0
10
15

—
—
—

0.01

0.01
—

—
—
—

0
0

—

0.01

0.01
—

—
—
—

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

0.05

0.05
—

Vdc

“1” Level

V

OH

5.0
10
15

—
—
—

—
—
—

3.0

8.0
—

4.14

9.09

14.12

—
—
—

—
—
—

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

—
—
—

Vdc

Noise Immunity

(∆V

out

v

1.5 Vdc)

(∆V

out

v 3.0 Vdc)

(∆V

out

v 4.5 Vdc)

V

NL

5.0
10
15

1.5

3.0
—

—
—
—

1.5

3.0
—

2.25

4.50

6.75

—
—
—

1.4

2.9
—

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

—
—
—

Vdc

v

1.5 Vdc)

(∆V

out

v 3.0 Vdc)

(∆V

out

v 4.5 Vdc)

(∆V

out

v 1.5 Vdc)

(∆V

out

v 3.0 Vdc)

(∆V

out

v 4.5 Vdc)

V

NH

5.0
10
15

1.4

2.9
—

—
—
—

1.5

3.0
—

2.25

4.50

6.75

—
—
—

1.5

3.0
—

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

—
—
—

Vdc

Output Drive Voltage (NPN Driver)

(IOH = 0 mA) Source
(IOH = 5.0 mA)
(IOH = 10 mA)
(IOH = 15 mA)

V

OH

5.0

—
—
—
—

—
—
—
—

3.0

2.7

2.5

2.2

4.14

3.44

3.30

3.08

—
—
—
—

—
—
—
—

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

—
—
—
—

Vdc

(IOH = 0 mA)
(IOH = 5.0 mA)
(IOH = 10 mA)
(IOH = 15 mA)

10

—
—
—
—

—
—
—
—

8.0

7.7

7.5

7.1

9.09

8.45

8.30

8.14

—
—
—
—

—
—
—
—

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

—
—
—
—

Vdc

(IOH = 0 mA)
(IOH = 5.0 mA)
(IOH = 10 mA)
(IOH = 15 mA)

15

—
—
—
—

—
—
—
—

—
—
—
—

14.12

13.81

13.70

13.61

—
—
—
—

—
—
—
—

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

—
—
—
—

Vdc

Output Drive Current

(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)

I

OL

5.0
10
15

0.23

0.60
—

—
—
—

0.2

0.5
—

0.78

2.0

7.8

—
—
—

0.16

0.40
—

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

—
—
—

mAdc

Input Leakage Current

I

in

15

—

± 0.3

—

±0.00001

± 0.3

—

ÎÎÎ

ÎÎÎ

ÎÎÎ

± 1.0

µAdc

Input Capacitance

(Vin = 0)

C

in

—

—

—

—

5.0

—

—

ÎÎÎ

ÎÎÎ

ÎÎÎ

—

pF

Quiescent Dissipation

P

Q

5.0
10
15

—
—
—

0.25

1.0
—

—
—
—

0.00005

0.00022

0.00050

0.25

1.0
—

—
—
—

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

ÎÎÎ

3.5
14
—

mW

Power Dissipation**

(Dynamic plus Quiescent)
(CL = 15 pF)

P

D

5.0
10
15

PD (56 mW/MHz) f + P

Q

PD (225 mW/MHz) f + P

Q

PD (510 mW/MHz) f + P

Q

mW

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and V

out

should be constrained to the range VSS ≤ (Vin or V

out

) ≤ VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.

MOTOROLA CMOS LOGIC DATAMC14415

292

SWITCHING CHARACTERISTICS* (C

L

= 15 pF, TA = 25_C)

Characteristic

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

Symbol

V

DD

Vdc

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

Min

Typ #

Max

Unit

Output Rise Time

t

TLH

= (2.0 ns/pF) CL + 10 ns

t

TLH

= (1.25 ns/pF) CL + 6 ns

t

TLH

= (1.10 ns/pF) CL + 3 ns

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

t

TLH

5.0
10
15

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

—
—
—

40
25
20

85
60
—

ns

Output Fall Time

t

THL

= (1.5 ns/pF) CL + 47 ns

t

THL

= (0.75 ns/pF) CL + 24 ns

t

THL

= (0.55 ns/pF) CL + 17 ns

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

t

THL

5.0
10
15

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

—
—
—

70
35
25

150

80
—

ns

Turn–Off Delay Time

t

PLH

= (2.7 ns/pF) CL + 560 ns

t

PLH

= (1.2 ns/pF) CL + 282 ns

t

PLH

= (0.91 ns/pF) CL + 286 ns

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

t

PLH

5.0
10
15

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

—
—
—

600
300
150

1200

600

—

ns

Turn–On Delay Time

t

PHL

= (2.4 ns/pF) CL + 564 ns

t

PHL

= (1.0 ns/pF) CL + 285 ns

t

PHL

= (0.75 ns/pF) CL + 289 ns

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

t

PHL

5.0
10
15

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

—
—
—

600
300
150

1200

600

—

ns

Turn–On Delay Time (Inhibit to Output)

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

t

PHL

5.0
10
15

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

—
—
—

300
225

110

550
425

—

ns

Turn–Off Delay Time (Inhibit to Output)

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

t

PLH

5.0
10
15

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

—
—
—

300
225

110

550
425

—

ns

Input Pulse Coincidence (Figure 3)

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

PC

min

5.0
10
15

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

500
450

—

450
350

—

—
—
—

ns

Input Pulse Width (Figure 1)

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

t

WH

5.0
10
15

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

500
450

—

450
350

—

—
—
—

ns

Input Clock Frequency

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

f

cl

5.0
10
15

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

—
—
—

0.7

1.0

1.5

—
—
—

MHz

Clock Input Rise and Fall Times (Figure 1)

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

t

TLH

, t

THL

5.0
10
15

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

ÎÎÎÎ

—
—
—

—
—
—

15

5.0

4.0

µs

*The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

Figure 1. Switching Characteristics — Waveform Relationships

20 ns 20 ns

V

SS

V

DD

V

OH

V

OL

V

DD

V

SS

V

OH

V

OL

INPUT

OUTPUT

CLOCK

OUTPUT

1 2

50%

90%

10%

t

WH

t

PLH

t

TLH

t

THL

t

PHL

100

50%

10%

90%

50%