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MOTOROLA CMOS LOGIC DATA
1
MC14051B MC14052B MC14053B
Analog
Multiplexers/Demultiplexers
The MC14051B, MC14052B, and MC14053B analog multiplexers are
digitally–controlled analog switches. The MC14051B effectively implements
an SP8T solid state switch, the MC14052B a DP4T, and the MC14053B a
Triple SPDT. All three devices feature low ON impedance and very low OFF
leakage current. Control of analog signals up to the complete supply voltage
range can be achieved.
• Triple Diode Protection on Control Inputs
• Switch Function is Break Before Make
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Analog Voltage Range (VDD – VEE) = 3.0 to 18 V
Note: VEE must be v V
SS
• Linearized Transfer Characteristics
• Low–noise – 12 nV/√Cycle
, f ≥ 1.0 kHz Typical
• Pin–for–Pin Replacement for CD4051, CD4052, and CD4053
• For 4PDT Switch, See MC14551B
• For Lower RON, Use the HC4051, HC4052, or HC4053 High–Speed
CMOS Devices
DC Supply Voltage (Referenced to VEE,
VSS ≥ VEE)
Input or Output Voltage (DC or Transient)
(Referenced to VSS for Control Inputs and
VEE for Switch I/O)
Input Current (DC or Transient),
per Control Pin
Power Dissipation. per Package†
Lead Temperature (8–Second Soldering)
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:“P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
MC14051B
8–Channel Analog
Multiplexer/Demultiplexer
MC14052B
Dual 4–Channel Analog
Multiplexer/Demultiplexer
MC14053B
Triple 2–Channel Analog
Multiplexer/Demultiplexer
VDD = PIN 16
VSS = PIN 8
VEE = PIN 7
Note: Control Inputs referenced to VSS, Analog Inputs and Outputs reference to VEE. VEE must be ≤ VSS.
INHIBIT
A
B
C
X0
X1
X2
X3
X4
X5
X6
X7
X
4
2
5
1
12
15
14
13
9
10
11
6
CONTROLS
SWITCHES
IN/OUT
COMMON
OUT/IN
3
4
2
5
1
11
15
14
12
9
10
6
CONTROLS
SWITCHES
IN/OUT
13
3
COMMONS
OUT/IN
X
Y
VDD = PIN 16
VSS = PIN 8
VEE = PIN 7
3
5
1
2
13
12
9
10
11
6
CONTROLS
SWITCHES
IN/OUT
14
15
4
X
Y
Z
COMMONS
OUT/IN
VDD = PIN 16
VSS = PIN 8
VEE = PIN 7
INHIBIT
A
B
X0
X1
X2
X3
Y0
Y1
Y2
Y3
INHIBIT
A
B
C
X0
Y0
Y1
Z0
Z1
X1
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
REV 3
1/94
MC14051B
MC14052B
MC14053B
L SUFFIX
CERAMIC
CASE 620
ORDERING INFORMATION
MC14XXXBCP Plastic
MC14XXXBCL Ceramic
MC14XXXBD SOIC
TA = – 55° to 125°C for all packages.
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
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MOTOROLA CMOS LOGIC DATAMC14051B MC14052B MC14053B
2
ELECTRICAL CHARACTERISTICS
SUPPLY REQUIREMENTS (Voltages Referenced to VEE)
Power Supply Voltage
Range
Quiescent Current Per
Package
Control Inputs:
Vin = VSS or VDD,
Switch I/O: VEE v V
I/O
v
VDD, and
∆V
switch
v 500 mV**
Total Supply Current
(Dynamic Plus
Quiescent, Per Package
TA = 25_C only (The
channel component,
(Vin – V
out
)/Ron, is
not included.)
(0.07 µA/kHz) f + I
DD
Typical (0.20 µA/kHz) f + I
DD
(0.36 µA/kHz) f + I
DD
CONTROL INPUTS — INHIBIT, A, B, C (Voltages Referenced to VSS)
Ron = per spec,
I
off
= per spec
Ron = per spec,
I
off
= per spec
SWITCHES IN/OUT AND COMMONS OUT/IN — X, Y, Z (Voltages Referenced to VEE)
Recommended
Peak–to–Peak Voltage
Into or Out of the Switch
Recommended Static or
Dynamic Voltage Across
the Switch** (Figure 5)
∆V
switch
v 500 mV**,
Vin = VIL or V
IH
(Control), and Vin =
0 to VDD (Switch)
∆ON Resistance Between
Any Two Channels in the
Same Package
Off–Channel Leakage
Current (Figure 10)
Vin = VIL or V
IH
(Control) Channel to
Channel or Any One
Channel
Inhibit = V
DD
(MC14051B)
(MC14052B)
(MC14053B)
Capacitance, Feedthrough
(Channel Off)
#Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance.
*For voltage drops across the switch (∆V
switch
) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn, i.e. the
current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the Maximum
Ratings are exceeded. (See first page of this data sheet.)
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MOTOROLA CMOS LOGIC DATA
3
MC14051B MC14052B MC14053B
ELECTRICAL CHARACTERISTICS* (C
L
= 50 pF, TA = 25_C) (VEE v VSS unless otherwise indicated)
Propagation Delay Times (Figure 6)
Switch Input to Switch Output (RL = 10 kΩ)
MC14051
t
PLH
, t
PHL
= (0.17 ns/pF) CL + 26.5 ns
t
PLH
, t
PHL
= (0.08 ns/pF) CL + 11 ns
t
PLH
, t
PHL
= (0.06 ns/pF) CL + 9.0 ns
MC14052
t
PLH
, t
PHL
= (0.17 ns/pF) CL + 21.5 ns
t
PLH
, t
PHL
= (0.08 ns/pF) CL + 8.0 ns
t
PLH
, t
PHL
= (0.06 ns/pF) CL + 7.0 ns
MC14053
t
PLH
, t
PHL
= (0.17 ns/pF) CL + 16.5 ns
t
PLH
, t
PHL
= (0.08 ns/pF) CL + 4.0 ns
t
PLH
, t
PHL
= (0.06 ns/pF) CL + 3.0 ns
Inhibit to Output (RL = 10 kΩ, VEE = VSS)
Output “1” or “0” to High Impedance, or
High Impedance to “1” or “0” Level
MC14051B
t
PHZ
, t
PLZ
,
t
PZH
, t
PZL
Control Input to Output (RL = 10 kΩ, VEE = VSS)
MC14051B
Second Harmonic Distortion
(RL = 10KΩ, f = 1 kHz) Vin = 5 V
PP
Bandwidth (Figure 7)
(RL = 1 kΩ, Vin = 1/2 (VDD–VEE) p–p, CL = 50pF
20 Log (V
out/Vin
) = – 3 dB)
Off Channel Feedthrough Attenuation (Figure 7)
RL = 1KΩ, Vin = 1/2 (VDD – VEE) p–p
fin = 4.5 MHz — MC14051B
fin = 30 MHz — MC14052B
fin = 55 MHz — MC14053B
Channel Separation (Figure 8)
(RL = 1 kΩ, Vin = 1/2 (VDD–VEE) p–p,
fin = 3.0 MHz
Crosstalk, Control Input to Common O/I (Figure 9)
(R1 = 1 kΩ, RL = 10 kΩ
Control t
TLH
= t
THL
= 20 ns, Inhibit = VSS)
mV
*The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not lo be used for design purposes but In intended as an indication of the IC’s potential performance.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and V
out
should be constrained to the range VSS ≤ (Vin or V
out
) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS, VEE, or VDD). Unused outputs
must be left open.