MOTOROLA CMOS LOGIC DATAMC14043B MC14044B
162
Quad R–S Latches
The MC14043B and MC14044B quad R–S latches are constructed with
MOS P–channel and N–channel enhancement mode devices in a single
monolithic structure. Each latch has an independent Q output and set and
reset inputs. The Q outputs are gated through three–state buffers having a
common enable input. The outputs are enabled with a logical “1” or high on
the enable input; a logical “0” or low d isconnects the latch from the Q
outputs, resulting in an open circuit at the Q outputs.
• Double Diode Input Protection
• Three–State Outputs with Common Enable
• Outputs Capable of Driving Two Low–power TTL Loads or One Low–
Power Schottky TTL Load Over the Rated Temperature Range
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
MC14043B
TRUTH TABLE
X = Don’t Care
MC14044B
S R E Q
High
Impedance
X X 0
No Change
0
1
1
0
0
1
1
0
1
0
1
1
1
1
1
TRUTH TABLE
X = Don’t Care
S R E Q
High
Impedance
X X 0
0
1
0
No Change
0
0
1
1
0
1
0
1
1
1
1
1
ENABLE
R3
S3
R2
S2
R1
S1
R0
S0
4
3
6
7
12
11
14
15
5
Q3
Q2
Q1
Q0
2
9
10
1
ENABLE
S3
R3
S2
R2
S1
R1
S0
R0
4
3
6
7
12
11
14
15
5
Q3
Q2
Q1
Q0
13
9
10
1
VDD = PIN 16
VSS = PIN 8
NC = PIN 2
VDD = PIN 16
VSS = PIN 8
NC = PIN 13
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
REV 3
1/94
L SUFFIX
CERAMIC
CASE 620
ORDERING INFORMATION
MC14XXXBCP Plastic
MC14XXXBCL Ceramic
MC14XXXBD SOIC
TA = – 55° to 125°C for all packages.
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
MOTOROLA CMOS LOGIC DATA
163
MC14043B MC14044B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
SS
)
V
– 55_C
25_C
125_C
Characteristic
Symbol
V
DD
Vdc
Min
Max
Min
Typ #
Max
Min
ÎÎÎ
ÎÎÎ
ÎÎÎ
Max
Unit
Output Voltage
“0” Level
Vin = VDD or 0
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
0.05
0.05
0.05
Vdc
“1” Level
Vin = 0 or V
DD
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
—
—
Vdc
Input Voltage
“0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
1.5
3.0
4.0
Vdc
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
V
IH
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
—
—
Vdc
Output Drive Current
(VOH = 2.5 Vdc) Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
I
OH
5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
—
—
—
mAdc
(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
I
OL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
—
—
mAdc
Input Current
I
in
15
—
± 0.1
—
±0.00001
± 0.1
—
ÎÎÎ
ÎÎÎ
ÎÎÎ
± 1.0
µAdc
Input Capacitance
(Vin = 0)
C
in
—
—
—
—
5.0
7.5
—
ÎÎÎ
ÎÎÎ
ÎÎÎ
—
pF
Quiescent Current
(Per Package)
I
DD
5.0
10
15
—
—
—
1.0
2.0
4.0
—
—
—
0.002
0.004
0.006
1.0
2.0
4.0
—
—
—
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
30
60
120
µAdc
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs all
buffers switching)
I
T
5.0
10
15
IT = (0.58 µA/kHz) f + I
DD
IT = (1.15 µA/kHz) f + I
DD
IT = (1.73 µA/kHz) f + I
DD
µAdc
Three–State Output Leakage
Current
I
TL
15
—
± 0.1
—
± 0.0001
± 0.1
—
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
± 3.0
µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.
*Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages – 12 mW/_C From 100_C To 125_C
MOTOROLA CMOS LOGIC DATAMC14043B MC14044B
164
MAXIMUM RATINGS* (Voltages Referenced to V
SS
)
Symbol
Parameter
Value
Unit
V
DD
DC Supply Voltage
– 0.5 to + 18.0
V
Vin, V
out
Input or Output Voltage (DC or Transient)
– 0.5 to VDD + 0.5
V
lin, l
out
Input or Output Current (DC or Transient),
per Pin
± 10
mA
P
D
Power Dissipation, per Package†
500
mW
T
stg
Storage Temperature
– 65 to + 150
_
C
T
L
Lead Temperature (8–Second Soldering)
260
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
SWITCHING CHARACTERISTICS* (C
L
= 50 pF, TA = 25_C)
Characteristic
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
Symbol
V
DD
Vdc
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
Min
Typ #
Max
Unit
Output Rise Time
t
TLH
= (1.35 ns/pF) CL + 32.5 ns
t
TLH
= (0.60 ns/pF) CL + 20 ns
t
TLH
= (0.40 ns/pF) CL + 20 ns
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
t
TLH
5.0
10
15
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
—
—
—
100
50
40
200
100
80
ns
Output Fall Time
t
THL
= (1.35 ns/pF) CL + 32.5 ns
t
THL
= (0.60 ns/pF) CL + 20 ns
t
THL
= (0.40 ns/pF) CL + 20 ns
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
t
THL
5.0
10
15
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
—
—
—
100
50
40
200
100
80
ns
Propagation Delay Time
t
PLH
= (0.90 ns/pF) CL + 130 ns
t
PLH
= (0.36 ns/pF) CL + 57 ns
t
PLH
= (0.26 ns/pF) CL + 47 ns
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
t
PLH
5.0
10
15
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
—
—
—
175
75
60
350
175
120
ns
t
PHL
= (0.90 ns/pF) CL + 130 ns
t
PHL
= (0.90 ns/pF) CL + 57 ns
t
PHL
= (0.26 ns/pF) CL + 47 ns
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
t
PHL
5.0
10
15
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
—
—
—
175
75
60
350
175
120
ns
Set, Set Pulse Width
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
t
W
5.0
10
15
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
200
100
70
80
40
30
—
—
—
ns
Reset, Reset Pulse Width
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
t
W
5.0
10
15
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
200
100
70
80
40
30
—
—
—
ns
Three–State Enable/Disable Delay
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
t
PLZ
,
t
PHZ
,
t
PZL
,
t
PZH
5.0
10
15
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
—
—
—
150
80
55
300
160
110
ns
*The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
AC WAVEFORMS
MC14043B MC14044B
20 ns 20 ns
90%
10%
RESET
SET
Q
t
PHL
t
PLH
20 ns 20 ns
50%
90%
50%
10%
t
THL
t
TLH
90%
50%
10%
V
DD
V
SS
V
DD
V
SS
V
OH
V
OL
RESET
SET
Q
20 ns 20 ns
90%
10%
50%
20 ns 20 ns
90%
10%
50%
t
TLH
t
THL
50%
10%
90%
t
PLH
t
PHL
V
DD
V
SS
V
DD
V
SS
V
OH
V
OL
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, precautions must be taken to avoid applications of
any voltage higher than maximum rated voltages to this high–impedance circuit. For proper
operation, Vin and V
out
should be constrained
to the range VSS v (Vin or V
out
) v VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either V
SS
or VDD). Unused outputs must be left open.
MOTOROLA CMOS LOGIC DATA
165
MC14043B MC14044B
THREE–STATE ENABLE/DISABLE DELAYS
Set, Reset, Enable, and Switch Conditions for 3–State Tests
MC14043B MC14044B
Test
EnableS1S2
Q
S R S R
t
PZH
Open Closed A V
DDVSSVSSVDD
t
PZL
Closed Open B V
SSVDDVDDVSS
t
PHZ
Open Closed A V
DDVSSVSSVDD
t
PLZ
Closed Open B V
SSVDDVDDVSS
ENABLE
Q
A
Q
B
50%
t
PZH
10%
t
PZL
t
PHZ
t
PLZ
10%
90%
V
DD
V
SS
V
DD
V
OL
V
OH
V
SS
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
S2
NC
S3
R3
V
DD
Q1
Q2
R2
S0
R0
Q0
Q3
V
SS
R1
S1
E
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
R2
Q0
R3
S3
V
DD
Q1
Q2
S2
R0
S0
NC
Q3
V
SS
S1
R1
E
NC = NO CONNECTION
MC14043B MC14044B
TO
OUTPUT
UNDER
TEST
V
DD
S1
S2
1 k
C
L
50 pF
V
SS
MOTOROLA CMOS LOGIC DATAMC14043B MC14044B
166
OUTLINE DIMENSIONS
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
B
F
C
S
H
G
D
J
L
M
16 PL
SEATING
1 8
916
K
PLANE
–T–
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01
____
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
–A–
–B–
–T–
F
E
G
N
K
C
SEATING
PLANE
16 PLD
S
A
M
0.25 (0.010) T
16 PLJ
S
B
M
0.25 (0.010) T
M
L
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.750 0.785 19.05 19.93
B 0.240 0.295 6.10 7.49
C ––– 0.200 ––– 5.08
D 0.015 0.020 0.39 0.50
E 0.050 BSC 1.27 BSC
F 0.055 0.065 1.40 1.65
G 0.100 BSC 2.54 BSC
H 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31
L 0.300 BSC 7.62 BSC
M 0 15 0 15
N 0.020 0.040 0.51 1.01
_ _ _ _
16 9
1 8
MOTOROLA CMOS LOGIC DATA
167
MC14043B MC14044B
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1 8
16 9
SEATING
PLANE
F
J
M
R
X 45
_
G
8 PLP
–B–
–A–
M
0.25 (0.010) B
S
–T–
D
K
C
16 PL
S
B
M
0.25 (0.010) A
S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019
_ _ _ _
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MC14043B/D
*MC14043B/D*
◊
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