SEMICONDUCTOR TECHNICAL DATA
1
REV 6
Motorola, Inc. 1995
10/95
"
" !
High–Performance Silicon–Gate CMOS
The MC54/74HC4351, and MC54/74HC4353 utilize silicon–gate CMOS
technology to achieve fast propagation delays, low ON resistances, and low
OFF leakage currents. These analog multiplexers/demultiplexers control
analog voltages that may vary across the complete power supply range
(from VCC to VEE).
The Channel–Select inputs determine which one of the Analog Inputs/
Outputs is to be connected, by means of an analog switch, to the Common
Output/Input. The d ata at the Channel–Select inputs may be l atched by
using the active–low Latch Enable pin. When Latch Enable is high, the latch
is transparent. When either Enable 1 (active low) or Enable 2 (active high) is
inactive, all analog switches are turned off.
The Channel–Select and Enable inputs are compatible with standard
CMOS outputs; with pullup resistors, they are compatible with L STTL
outputs.
These devices have been designed so that the ON resistance (Ron) is
more linear over input voltage than Ron of metal–gate CMOS analog
switches.
For multiplexers/demultiplexers without latches, see the HC4051,
HC4052, and HC4053.
• Fast Switching and Propagation Speeds
• Low Crosstalk Between Switches
• Diode Protection on All Inputs/Outputs
• Analog Power Supply Range (VCC – VEE) = 2.0 to 12.0 V
• Digital (Control) Power Supply Range (VCC – GND) = 2.0 to 6.0 V
• Improved Linearity and Lower ON Resistance than Metal–Gate Types
• Low Noise
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: HC4351 — 222 FETs or 55.5 Equivalent Gates
HC4353 — 186 FETs or 46.5 Equivalent Gates
PIN ASSIGNMENT
MC54/74HC4351
X5
X
NC
X6
X4
GND
V
EE
ENABLE 2
ENABLE 1
X7 5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
X3
X0
X1
X2
V
CC
LATCH
ENABLE
C
B
NC
A
NC = NO CONNECTION
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ORDERING INFORMATION
MC54HCXXXXJ
MC74HCXXXXN
MC74HCXXXXDW
Ceramic
Plastic
SOIC
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
1
20
1
20
1
20
MC54/74HC4351 MC54/74HC4353
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
2
LOGIC DIAGRAM
MC54/74HC4351
Single–Pole, 8–Position Plus Common Off and Address Latch
FUNCTION TABLE
MC54/74HC4351
Control Inputs
Enable Select
ON
Channel
1 2 C B A
Channel
(LE = H)*
L
H
L
L
L
X0
LLHHLLLLLHX0
X1
LLHHLLLHHLX1X2LLHHLLHHLHX2
X3
LLHHLHHLHLX3
X4
LLHHHHLLLHX4
X5
LLHHHHLHHLX5
X6
LLHHHHHHLHX6
X7
LHHXHXHXHXX7
None
HXXLXXXXXXNone
None
X = don’t care
*When Latch Enable is low, the Channel
Selection is latched and the Channel
Address Latch does not change states.
BLOCK DIAGRAM
MC54/74HC4353
Triple Single–Pole, Double–Position Plus Common Off and Address Latch
FUNCTION TABLE
Control Inputs
Enable Select
On
Channel
1 2 C B A
Channel
(LE = H)*
L
H
L
L
L
Z0
Y0
X0
LLHHLLLLLHZ0Z0Y0Y0X0
X1
LLHHLLLHHLZ0Z0Y0Y1X1X0LLHHLLHHLHZ0Z0Y1Y1X0
X1
LLHHLHHLHLZ0Z1Y1Y0X1
X0
LLHHHHLLLHZ1Z1Y0Y0X0
X1
LLHHHHLHHLZ1Z1Y0Y1X1
X0
LLHHHHHHLHZ1Z1Y1Y1X0
X1
LHHXHXHXH
X
None
X L X X X
None
X = Don’t Care
*When Latch Enable is low, the Channel Selection
is latched and the Channel Address Latch does not
change states.
MULTIPLEXER/
DEMULTIPLEXER
17
X0
18
X1
19
X2
16
X3
1
X4
6
X5
2
X6
5
X7
ANALOG
INPUTS/OUTPUTS
4
X
COMMON
OUTPUT/INPUT
CHANNEL
ADDRESS
LATCH
13
B
15
A
12
C
11
LATCH ENABLE
7
ENABLE 1
8
ENABLE 2
SWITCH
ENABLES
PIN 20 = V
CC
PIN 9 = V
EE
PIN 10 = GND
PINS 3, 14 = NC
CHANNEL–SELECT
INPUTS
Z0
Z1
NC
Y0
Y1
GND
V
EE
ENABLE 2
ENABLE 1
Z
5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
X0
X1
X
Y
V
CC
LATCH
ENABLE
C
B
NC
A
PIN ASSIGNMENT
NC = NO CONNECTION
16
X0
18
X
CHANNEL
ADDRESS
LATCH
13
B
15
A
12
C
11
LATCH ENABLE
7
ENABLE 1
8
ENABLE 2
SWITCH
ENABLES
PIN 20 = V
CC
PIN 9 = V
EE
PIN 10 = GND
PINS 3, 14 = NC
CHANNEL–SELECT
INPUTS
17
X1
2
Y0
1
Y1
6
Z0
4
Z1
X SWITCH
Y SWITCH
Z SWITCH
19
Y
5
Z
COMMON
OUTPUT/INPUT
NOTE:
This device allows independent control of each switch. Channel–Select
Input A controls the X Switch, Input B controls the Y Switch, and Input C
controls the Z Switch.
MC54/74HC4351 MC54/74HC4353
High–Speed CMOS Logic Data
DL129 — Rev 6
3 MOTOROLA
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
CC
Positive DC Supply Voltage (Ref. to GND)
(Ref. to VEE)
– 0.5 to + 7.0
– 0.5 to 14.0
V
V
EE
Negative DC Supply Voltage (Ref. to GND)
– 7.0 to + 0.5
V
V
IS
Analog Input Voltage
VEE – 0.5
to VCC + 0.5
V
V
in
DC Input Voltage (Ref. to GND)
– 1.5 to VCC + 1.5
V
I
DC Current Into or Out of Any Pin
± 25
mA
P
D
Power Dissipation in Still Air,Plastic or Ceramic DIP†
SOIC Package†
750
500
mW
T
stg
Storage Temperature
– 65 to + 150
_
C
T
L
Lead Temperature, 1 mm from Case for
10 Seconds (Plastic DIP or SOIC Package)
(Ceramic DIP)
260
300
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
Positive DC Supply Voltage (Ref. to GND)
(Ref. to VEE)
2.0
2.0
6.0
12.0
V
V
EE
Negative DC Supply Voltage (Ref. to GND)
– 6.0
GND
V
V
IS
Analog Input Voltage
V
EEVCC
V
V
in
Digital Input Voltage (Ref. to GND)
GND
V
CC
V
VIO*
Static or Dynamic Voltage Across Switch
—
1.2
V
T
A
Operating Temperature, All Package Types
– 55
+ 125
_
C
tr, t
f
Input Rise and Fall Time, VCC = 2.0 V
Channel Select or Enable VCC = 4.5 V
Inputs (Figure 9a) VCC = 6.0 V
0
0
0
1000
500
400
ns
*For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may
be drawn; i.e., the current out of the switch may contain both VCC and switch input components.
The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
DC ELECTRICAL CHARACTERISTICS Digital Section (Voltages Referenced to GND) V
EE
= GND, Except Where Noted
Guaranteed Limit
Symbol
Parameter
Test Conditions
V
CC
V
– 55 to
25_C
v
85_Cv 125_C
Unit
V
IH
Minimum High–Level Input
Voltage, Channel–Select or
Enable Inputs
Ron = Per Spec
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
IL
Maximum Low–Level Input
Voltage, Channel–Select or
Enable Inputs
Ron = Per Spec
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
I
in
Maximum Input Leakage
Current, Channel–Select or
Enable Inputs
Vin = VCC or GND,
VEE = – 6.0 V
6.0
± 0.1
± 1.0
± 1.0
µA
I
CC
Maximum Quiescent Supply
Current (per Package)
Channel Select = VCC or GND
Enables = VCC or GND
VIS = VCC or GND VEE = GND
VIO = 0 V VEE = – 6.0
6.0
6.0
2
8
20
80
40
160
µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
V
out
should be constrained to the
ranges indicated in the Recommended Operating Conditions.
Unused digital input pins must be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused Analog I/O pins may be left
open or terminated. See Applications Information.
MC54/74HC4351 MC54/74HC4353
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
4
DC ELECTRICAL CHARACTERISTICS Analog Section
Guaranteed Limit
Symbol
Parameter
Test Conditions
V
CC
V
V
EE
V
– 55 to
25_C
v
85_Cv 125_C
Unit
R
on
Maximum “ON” Resistance
Vin = VIL or V
IH
VIS = VCC to V
EE
IS v 2.0 mA (Figures 1, 2)
4.5
4.5
6.0
0.0
– 4.5
– 6.0
190
120
100
240
150
125
280
170
140
Ω
Vin = VIL or V
IH
VIS = VCC or VEE (Endpoints)
IS v 2.0 mA (Figures 1, 2)
4.5
4.5
6.0
0.0
– 4.5
– 6.0
150
100
80
190
125
100
230
140
115
∆R
on
Maximum Difference in “ON”
Resistance Between Any Two
Channels in the Same Package
Vin = VIL or V
IH
VIS = 1/2 (VCC – VEE)
IS v 2.0 mA
4.5
4.5
6.0
0.0
– 4.5
– 6.0
30
12
10
35
15
12
40
18
14
Ω
I
off
Maximum Off–Channel Leakage
Current, Any One Channel
Vin = VIL or V
IH
VIO = VCC – V
EE
Switch Off (Figure 3)
6.0
– 6.0
0.1
0.5
1.0
µA
Maximum Off–Channel Leakage
Current, Common Channel
HC4351
Vin = VIL or V
IH
VIO = VCC – V
EE
Switch Off (Figure 4)
6.0
– 6.0
0.2
2.0
4.0
HC4353
6.0
– 6.0
0.1
1.0
2.0
I
on
Maximum On–Channel Leakage
Current, Channel to Channel
HC4351
Vin = VIL or V
IH
Switch to Switch = VCC – V
EE
(Figure 5)
6.0
– 6.0
0.2
2.0
4.0
µA
HC4353
6.0
– 6.0
0.1
1.0
2.0
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Symbol
Parameter
V
CC
V
– 55 to
25_C
v
85_Cv 125_C
Unit
t
PLH
,
t
PHL
Maximum Propagation Delay, Channel–Select to Analog Output
(Figure 9)
2.0
4.5
6.0
370
74
63
465
93
79
550
110
94
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Analog Input to Analog Output
(Figure 10)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Latch Enable to Analog Output
(Figure 12)
2.0
4.5
6.0
325
65
55
410
82
70
485
97
82
ns
t
PLZ
,
t
PHZ
Maximum Propagation Delay, Enable 1 or 2 to Analog Output
(Figure 11)
2.0
4.5
6.0
290
58
49
365
73
62
435
87
74
ns
t
PZL
,
t
PZH
Maximum Propagation Delay, Enable 1 or 2 to Analog Output
(Figure 11)
2.0
4.5
6.0
345
69
59
435
87
74
515
103
87
ns
C
in
Maximum Input Capacitance
—
10
10
10
pF
C
l/O
Maximum Capacitance Analog I/O
ОООООООО
ОООООООО
ОООООООО
Enable 1 = VIH, Enable 2 = V
IL
—
35
35
35
pF
l/O
Common O/I: HC4351
HC4353
ОООООООО
ОООООООО
ОООООООО
IH
, Enable 2 = V
IL
—
130
50
130
50
130
50
Feedthrough
ОООООООО
ОООООООО
ОООООООО
—
1.0
1.0
1.0
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
C
PD
Power Dissipation Capacitance (Per Package) (Figure 14)*
45 (HC4351)
45 (HC4353)
pF
*Used to determine the no–load dynamic power consumption: PD = CPD V
CC
2
f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
MC54/74HC4351 MC54/74HC4353
High–Speed CMOS Logic Data
DL129 — Rev 6
5 MOTOROLA
TIMING REQUIREMENTS (Input t
r
= tf = 6 ns)
Guaranteed Limit
Symbol
Parameter
V
CC
V
– 55 to
25_C
v
85_Cv 125_C
Unit
t
su
Minimum Setup Time, Channel–Select to Latch Enable
(Figure 12)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
t
h
Minimum Hold Time, Latch Enable to Channel Select
(Figure 12)
2.0
4.5
6.0
0
0
0
0
0
0
0
0
0
ns
t
w
Minimum Pulse Width, Latch Enable
(Figure 12)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
tr, t
f
Maximum Input Rise and Fall Times, Channel–Select, Latch Enable,
and Enables 1 and 2
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0.0 V)
Limit*
Symbol
Parameter
Test Condition
V
CC
V
V
EE
V
25_C
54/74HC
Unit
BW
Maximum On–Channel Bandwidth or
fin = 1 MHz Sine Wave
51 52 53
MHz
Minimum Frequency Response
(Figure 6)
Adjust fin Voltage to Obtain 0 dBm at V
OS
Increase fin Frequency Until dB Meter
Reads – 3 dB
RL = 50 Ω, CL = 10 pF
2.25
4.50
6.00
– 2.25
– 4.50
– 6.00
80 95 120
80 95 120
80 95 120
—
Off–Channel Feedthrough Isolation
(Figure 7)
fin Sine Wave
Adjust fin Voltage to Obtain 0 dBm at V
IS
fin = 10 kHz, RL = 600 Ω, CL = 50 pF
2.25
4.50
6.00
– 2.25
– 4.50
– 6.00
– 50
– 50
– 50
dB
fin = 1.0 MHz, RL = 50 Ω, CL = 10 pF
2.25
4.50
6.00
– 2.25
– 4.50
– 6.00
– 40
– 40
– 40
—
Feedthrough Noise, Channel Select
Input to Common O/I
(Figure 8)
Vin v 1 MHz Square Wave
(tr = tf = 6 ns)
Adjust RL at Setup so that IS = 0 A
Enable = GND
RL = 600 Ω, CL = 50 pF
2.25
4.50
6.00
– 2.25
– 4.50
– 6.00
25
105
135
mV
PP
RL = 10 kΩ, CL = 10 pF
2.25
4.50
6.00
– 2.25
– 4.50
– 6.00
35
145
190
—
Crosstalk Between Any Two Switches
(Figure 13)
(Test does not apply to HC4351)
fin Sine Wave
Adjust fin Voltage to Obtain 0 dBm at V
IS
fin = 10 kHz, RL = 600 Ω, CL = 50 pF
2.25
4.50
6.00
– 2.25
– 4.50
– 6.00
– 50
– 50
– 50
dB
fin = 1 MHz, RL = 50 Ω, CL = 10 pF
2.25
4.50
6.00
– 2.25
– 4.50
– 6.00
– 60
– 60
– 60
THD
Total Harmonic Distortion
(Figure 15)
fin = 1 kHz, RL = 10 kΩ, CL = 50 pF
THD = THD
Measured
– THD
Source
VIS = 4.0 VPP sine wave
VIS = 8.0 VPP sine wave
VIS = 11.0 VPP sine wave
2.25
4.50
6.00
– 2.25
– 4.50
– 6.00
0.10
0.08
0.05
%
*Limits not tested. Determined by design and verified by qualification.
MC54/74HC4351 MC54/74HC4353
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
6
Figure 1a. Typical On Resistance, V
CC
– VEE = 2.0 V Figure 1b. Typical On Resistance, VCC – VEE = 4.5 V
250
200
150
100
50
0 0.25 0.50 0.75 1.0 1.25 1.5 1.75 2.0 2.25
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO V
EE
R
on
, ON RESISTANCE (OHMS)
100
80
60
40
20
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.5
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO V
EE
R
on
, ON RESISTANCE (OHMS)
25°C
–55°C
125°C
25°C
–55°C
125°C
4.0
Figure 1c. Typical On Resistance, V
CC
– VEE = 6.0 V Figure 1d. Typical On Resistance, VCC – VEE = 9.0 V
105
90
75
60
45
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO V
EE
R
on
, ON RESISTANCE (OHMS)
75
60
45
30
15
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO V
EE
R
on
, ON RESISTANCE (OHMS)
30
15
5.0 5.5 6.0
25°C
–55°C
125°C
25°C
–55°C
125°C
Figure 1e. Typical On Resistance, VCC – VEE = 12.0 V Figure 2. On Resistance Test Set–Up
1.0 2.0
70
60
50
40
30
0
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO V
EE
R
on
, ON RESISTANCE (OHMS)
20
10
3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0
25°C
–55°C
125°C
PLOTTER
MINI COMPUTER
PROGRAMMABLE
POWER
SUPPLY
DC ANALYZER
V
CC
DEVICE
UNDER TEST
+–
V
EE
ANALOG IN COMMON OUT
GND
MC54/74HC4351 MC54/74HC4353
High–Speed CMOS Logic Data
DL129 — Rev 6
7 MOTOROLA
Figure 3. Maximum Off Channel Leakage Current,
Any One Channel, Test Set–Up
Figure 4. Maximum Off Channel Leakage Current,
Common Channel, Test Set–Up
OFF
OFF
8
20
V
CC
V
EE
NC
A
V
CC
V
EE
V
CC
OFF
OFF
20
V
CC
ANALOG I/O
COMMON O/I
V
CC
V
EE
V
CC
COMMON O/I
ANALOG I/O
7
V
IH
9
10
8
V
EE
7
V
IH
9
10
A
Figure 5. Maximum On Channel Leakage Current,
Channel to Channel, Test Set–Up
Figure 6. Maximum On Channel Bandwidth,
Test Set–Up
ON
OFF
20
V
CC
N/C
A
ANALOG I/O
ON
20
V
CC
0.1µF
CL*
f
in
R
L
dB
METER
*Includes all probe and jig capacitance.
V
OS
V
CC
V
EE
V
CC
COMMON O/I
8
V
EE
7
V
IL
9
10
V
IH
8
V
EE
7
V
CC
9
10
Figure 7. Off Channel Feedthrough Isolation,
Test Set–Up
Figure 8. Feedthrough Noise, Channel Select to
Common Out, Test Set–Up
OFF
20
V
CC
0.1 µF
CL*
f
in
R
L
dB
METER
*Includes all probe and jig capacitance.
V
OS
R
L
V
IS
ON/OFF
20
V
CC
CL*
R
L
*Includes all probe and jig capacitance.
CHANNEL SELECT
TEST
POINT
11
V
CC
OFF/ON
R
L
R
L
V
CC
GND
Vin
≤
1 MHz
tr = tf = 6 ns
ANALOG I/O
COMMON O/I
8
V
EE
7
9
10
8
V
EE
7
V
CC
9
10
MC54/74HC4351 MC54/74HC4353
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
8
Figure 9a. Propagation Delays, Channel Select
to Analog Out
Figure 9b. Propagation Delay, T
est Set–Up Channel
Select to Analog Out
ON/OFF
20
V
CC
CL*
*Includes all probe and jig capacitance.
CHANNEL SELECT
TEST
POINT
OFF/ON
V
CC
ANALOG I/O
COMMON O/I
CHANNEL SELECT
ANALOG OUT
t
r
t
f
90%
50%
10%
V
CC
GND
t
PHL
t
PLH
50%
8
7
V
CC
9
10
V
CC
GND
ANALOG
IN
ANALOG
OUT
50%
t
PLH
t
PHL
50%
Figure 10a. Propagation Delays, Analog In to
Analog Out
Figure 10b. Propagation Delay, Test Set–Up
Analog In to Analog Out
ON
20
V
CC
*Includes all probe and jig capacitance.
TEST
POINT
COMMON O/I
ANALOG I/O
CL*
8
7
V
CC
9
10
ON/OFF
V
CC
TEST
POINT
20
V
CC
1 k
Ω
CL*
1
2
1
2
ANALOG I/O
8
7
9
10
ENABLE
Figure 11a. Propagation Delay, Enable 1 or 2
to Analog Out
50%
50%
90%
10%
t
PZL
t
PLZ
t
PZHtPHZ
HIGH
IMPEDANCE
V
OL
V
OH
HIGH
IMPEDANCE
V
CC
GND
50%
ANALOG
OUT
ENABLE
Figure 11b. Propagation Delay, Test Set–Up
Enable to Analog Out
ANALOG
OUT
POSITION WHEN TESTING t
PLZ
AND t
PZL
POSITION WHEN TESTING t
PHZ
AND t
PZH
1
2
MC54/74HC4351 MC54/74HC4353
High–Speed CMOS Logic Data
DL129 — Rev 6
9 MOTOROLA
Figure 12a. Propagation Delay, Latch Enable to
Analog Out
ON/OFF
20
V
CC
CL*
*Includes all probe and jig capacitance.
LATCH ENABLE
TEST
POINT
OFF/ON
V
CC
ANALOG I/O
COMMON O/I
Figure 12b. Propagation Delay, Test Set–Up
Latch Enable to Analog Out
CHANNEL
SELECT
LATCH
ENABLE 2
COMMON O/I
GND
V
CC
GND
V
CC
50%
50%
50%
90%
10%
t
su
t
h
t
f
t
r
t
w
t
PLH
,
t
PHL
8
7
V
CC
9
10
CHANNEL SELECT
11
Figure 13. Crosstalk Between Any Two
Switches, Test Set–Up
R
L
ON
20
CL*
*Includes all probe and jig capacitance.
OFF
R
L
V
IS
R
L
CL*
V
OS
f
in
0.1
µ
F
V
CC
dB
METER
8
7
9
10
R
L
VCCV
EE
Figure 14. Power Dissipation Capacitance,
Test Set-Up
ON/OFF
20
V
CC
CHANNEL SELECT
NC
OFF/ON
V
CC
11
V
CC
ANALOG I/O
COMMON O/I
A
8
7
V
CC
9
10
V
EE
Figure 15a. Total Harmonic Distortion, Test Set-Up
ON
20
V
CC
0.1 µF
CL*
f
in
R
L
TO
DISTORTION
METER
*Includes all probe and jig capacitance.
V
OS
V
IS
8
7
V
CC
9
10
V
EE
Figure 15b. Plot, Harmonic Distortion
0
–10
–20
–30
–40
–50
1.0 2.0 3.125
FREQUENCY (kHz)
dB
–60
–70
–80
–90
FUNDAMENTAL FREQUENCY
DEVICE
SOURCE
MC54/74HC4351 MC54/74HC4353
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
10
APPLICATIONS INFORMATION
The Channel Select and Enable control pins should be at
VCC or GND logic levels. VCC being recognized as a logic
high a nd GND b eing recognized as a l ogic low. In t his
example:
VCC = + 5 V = logic high
GND = 0 V = logic low
The maximum analog voltage swings are determined by
the supply voltages VCC and VEE. The positive peak analog
voltage should not exceed VCC. Similarly, the negative peak
analog voltage should not go below VEE. In this example, the
difference between VCC and VEE is ten volts. Therefore, using the configuration in Figure 16, a maximum analog signal
of ten volts peak–to–peak can be controlled. Unused analog
inputs/outputs may be left floating (i.e., not connected). How-
ever, tying unused analog inputs and outputs to VCC or GND
through a low value resistor helps minimize crosstalk and
feedthrough noise that may b e picked up by an u nused
switch.
Although used here, balanced supplies are not a require-
ment. The only constraints on the power supplies are that:
VCC – GND = 2 to 6 volts
VEE – GND = 0 to – 6 volts
VCC – VEE = 2 to 12 volts
and VEE v GND
When voltage transients above VCC and/or below VEE are
anticipated on the analog channels, external Germanium or
Schottky d iodes ( Dx) are r ecommended a s shown i n
Figure 17. These diodes should be able to absorb the maximum anticipated current surges during clipping.
Figure 16. Application Example Figure 17. External Germanium or
Schottky Clipping Diodes
ANALOG
SIGNAL
ON
20
+5 V
ANALOG
SIGNAL
+ 5 V
– 5 V
+ 5 V
– 5 V
TO EXTERNAL CMOS
CIRCUITRY
0 TO 5 V DIGITAL
SIGNALS
ON/OFF
9
20
V
CC
V
EE
D
x
V
EE
D
x
V
CC
D
x
8
7
9
10
–5 V
+5 V
15
13
12
11
10
V
EE
V
CC
D
x
Figure 18. Interfacing LSTTL/NMOS to CMOS Inputs
a. Using Pull–Up Resistors b. Using HCT Interface
ANALOG
SIGNAL
ON/OFF
20
+ 5 V
ANALOG
SIGNAL
+ 5 V
V
EE
+ 5 V
V
EE
R
*
LSTTL/NMOS
CIRCUITRY
+ 5 V
* 2 k
≤
R ≤ 10 k
ANALOG
SIGNAL
ON/OFF
20
+ 5 V
ANALOG
SIGNAL
+ 5 V
V
EE
+ 5 V
V
EE
LSTTL/NMOS
CIRCUITRY
+ 5 V
HCT
BUFFER
8
7
9
10
V
EE
V
CC
15
13
12
11
R
R R
8
7
9
10
V
EE
V
CC
15
13
12
11
MC54/74HC4351 MC54/74HC4353
High–Speed CMOS Logic Data
DL129 — Rev 6
11 MOTOROLA
FUNCTION DIAGRAM HC4351
X0
17
X1
X2
X3
X4
X5
X6
X7
6
2
5
X
4
A
15
LATCH &
LEVEL SHIFTER
LATCH &
LEVEL SHIFTER
LATCH &
LEVEL SHIFTER
B
13
C
12
LATCH
ENABLE
11
LEVEL SHIFTER
ENABLE 1
7
8
ENABLE 2
FUNCTION DIAGRAM HC4353
X1
17
X0
Y1
Y0
Z1
Z0
6
A
15
LATCH &
LEVEL SHIFTER
LATCH &
LEVEL SHIFTER
LATCH &
LEVEL SHIFTER
B
13
C
12
LATCH
ENABLE
11
LEVEL SHIFTER
ENABLE 1
7
8
ENABLE 2
16
1
2
4
18
19
5
X
Y
Z
MC54/74HC4351 MC54/74HC4353
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
12
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
ISSUE E
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ISSUE E
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D–04
ISSUE E
NOTES:
1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE
POSITION AT SEATING PLANE, AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSIONS A AND B INCLUDE MENISCUS.
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 23.88 25.15 0.940 0.990
B 6.60 7.49 0.260 0.295
C 3.81 5.08 0.150 0.200
D 0.38 0.56 0.015 0.022
F 1.40 1.65 0.055 0.065
G 2.54 BSC 0.100 BSC
H 0.51 1.27 0.020 0.050
J 0.20 0.30 0.008 0.012
K 3.18 4.06 0.125 0.160
L 7.62 BSC 0.300 BSC
M 0 15 0 15
N 0.25 1.02 0.010 0.040
_ _ _ _
A
20
1 10
11
B
F
C
SEATING
PLANE
D
H
G
K
N
J
M
L
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
M
L
J
20 PL
M
B
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 25.66 27.171.010 1.070
B 6.10 6.600.240 0.260
C 3.81 4.570.150 0.180
D 0.39 0.550.015 0.022
G 2.54 BSC0.100 BSC
J 0.21 0.380.008 0.015
K 2.80 3.550.110 0.140
L 7.62 BSC0.300 BSC
M 0 15 0 15
N 0.51 1.010.020 0.040
_ __ _
E
1.27 1.770.050 0.070
1
11
10
20
–A–
SEATING
PLANE
K
N
FG
D
20 PL
–T–
M
A
M
0.25 (0.010) T
E
B
C
F
1.27 BSC0.050 BSC
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
–A–
–B–
20
1
11
10
S
A
M
0.010 (0.25) B
S
T
D20X
M
B
M
0.010 (0.25)
P10X
J
F
G
18X
K
C
–T–
SEATING
PLANE
M
R
X 45
_
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 12.65 12.95 0.499 0.510
B 7.40 7.60 0.292 0.299
C 2.35 2.65 0.093 0.104
D 0.35 0.49 0.014 0.019
F 0.50 0.90 0.020 0.035
G 1.27 BSC 0.050 BSC
J 0.25 0.32 0.010 0.012
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 10.05 10.55 0.395 0.415
R 0.25 0.75 0.010 0.029
_ _
_ _
MC54/74HC4351 MC54/74HC4353
High–Speed CMOS Logic Data
DL129 — Rev 6
13 MOTOROLA
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*MC54/74HC4351/D*
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