Motorola MC12053AD, MC12053ASD Datasheet

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Order this document by MC12053A/D

SEMICONDUCTOR

TECHNICAL DATA

MECL PLL COMPONENTS

÷64/65, ÷128/129 LOW POWER
DUAL MODULUS PRESCALER

WITH STAND–BY MODE

SD SUFFIX

PLASTIC PACKAGE

CASE 940
(SSOP–8)

PIN CONNECTIONS

D SUFFIX

PLASTIC PACKAGE

CASE 751

(SO–8)

8

1

1

8

IN

(Top View)

8

IN

V

CC

SW

OUT

SB
MC

Gnd

7
6
5

1
2
3
4

Device

Operating

Temp Range

Package

ORDERING INFORMATION

MC12053AD
MC12053ASD

TA =

–40° to +85°C

SO–8

SSOP–8

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The MC12053A is a super low power ÷64/65, ÷128/129 dual modulus
prescaler. Motorola’ s advanced Bipolar MOSAIC V technology is utilized to
achieve low power dissipation of 4.3 mW at a minimum supply voltage of

2.7 V.

The Divide Ratio Control input, SW, permits selection of divide ratio as
desired. A HIGH on SW selects

÷64/65; an OPEN on SW selects ÷128/129.

The Modulus Control input, MC, selects the proper divide number after SW
has been biased to select the desired divide ratio.

Stand–by mode is featured to reduce current drain to 50 µA typical at

2.7 V when the stand–by pin, SB, is switched LOW, disabling the prescaler.
On–chip output termination provides 500 µA (typical) output current, which is
sufficient to drive a CMOS synthesizer input high impedance load (8.0 pF
typical).

• 1.1 GHz Toggle Frequency

• Supply Voltage of 2.7 to 5.5 V

• Low Power 1.5 mA Typical at V

CC

= 2.7 V

• Operating Temperature Range of –40 to 85°C

• On–Chip Output Termination

• The MC12053A Is Pin and Functionally Compatible With the MC12036

• Modulus Control Input Level Is Compatible With Standard CMOS and

TTL

MOSAIC V is a trademark of Motorola

FUNCTIONAL TABLE

SW MC Divide Ratio

H H 64
H L 65
L H 128
L L 129

NOTES: 1.SW: H = VCC – 0.5 to VCC, L = Open. A logic L can also be applied by grounding

this pin, but this is not recommended due to increased power consumption.

2.MC & SB: H = 2.0 V to VCC, L = Gnd to 0.8 V.

MAXIMUM RATINGS

Characteristic Symbol Range Unit

Power Supply Voltage, Pin 2 V

CC

–0.5 to 7.0 Vdc

Operating Temperature Range T

A

–40 to 85 °C

Storage Temperature Range T

stg

–65 to 150 °C

Modulus Control Input, Pin 6 MC –0.5 to V

CC

Vdc

Maximum Output Current, Pin 4 I

O

4.0 mA

NOTE: ESD data available upon request.

 Motorola, Inc. 1997 Rev 4

MC12053A

2

MOTOROLA RF/IF DEVICE DATA

ELECTRICAL CHARACTERISTICS (VCC = 2.7 to 5.5 V; TA = –40 to 85°C, unless otherwise notex.)

Characteristic Symbol Min Typ Max Unit

Toggle Frequency (Sine Wave Input) f

t

0.1 1.4 1.1 GHz

Supply Current Output (Pin 2) VCC = 2.7 V

VCC = 5.0 V

I

CC

–
–

1.60

1.75

2.5

2.5

mA

Stand–By Current VCC = 2.7 V

VCC = 5.0 V

I

SB

–
–

50

100

250
250

µA

Modulus Control & Stand–By Input HIGH (MC & SB) V

IH1

2.0 – VCC + 0.5 V

Modulus Control & Stand–By Input LOW (MC & SB) V

IL1

Gnd – 0.8 V

Divide Ratio Control Input HIGH (SW) V

IH2

VCC – 0.5 V

CC

VCC + 0.5 V

Divide Ratio Control Input LOW (SW) V

IH2

Open Open Open

Output Voltage Swing (Note 1) V

out

0.8 1.1 – V

pp

Modulus Setup Time MC to OUT at 1100 MHz t

set

– 11 16 ns

Input Voltage Sensitivity 250–1 100 MHz

100–250 MHz

V

in

100
400

–
–

1000
1000

mVpp

NOTE: Assumes 8.0 pF high impedance load.

Figure 1. Logic Diagram (MC12053A)

A

HGFED

In

MC

In

SW

Out

Q

S

Q

C

QBD

QC

QBD

QBC

QD

C

QBD

QBC

QD

QBC

QD

B

QBC

QD

C

QB

C

QD

M

Figure 2. Modulus Setup Time

Modulus setup time MC to out is the MC
setup or MC release plus the prop delay.

Prop. Delay

In

Out

MC

MC Setup

MC Release

SB

Figure 3. AC Test Circuit

EXTERNAL COMPONENTS
C1 = C2 = 1000 pF
C3 = 0.1

µ

F
CL = 8.0 pF (Including Scope
and jig capacitance)

C

L

MC Input

C2

C1

C3

VCC = 2.7 to 5.5 V

50

Ω

Sine Wave Generator

SWV

CC

OUT

GND

MC

IN

IN

SB

MC12053A

3

MOTOROLA RF/IF DEVICE DATA

Figure 4. Input Signal Amplitude versus Input Frequency

+15.0
+10.0

+5.0

0

–5.0
–10.0
–15.0
–20.0
–25.0
–30.0
–35.0
–40.0
–45.0
–50.0

+1257.40

+0.71

+1.26

+2.24

+3.98

+7.07

+12.57

+22.36

+39.76

+70.71

+125.74

+223.61

+397.64

+707.11

0 200 400 600 800 1000 1200 1400 1600 1800

FREQUENCY (MHz)

AMPLITUDE (dBm)

mVrms

0

FREQUENCY (MHz)

0

400

800

1200

1600

2000

mVpp

Figure 5. Output Amplitude versus Input Frequency

200 400 600 800 1000 1200 1400 1600 1800

OPERATING

WINDOW

Divide Ratio = 64; VCC = 2.7 V; TA = 25°C