SEMICONDUCTOR TECHNICAL DATA
2–293
REV 5
Motorola, Inc. 1996
3/93
The MC10H210 is designed to drive up to six transmission lines simultan–
eously. The multiple outputs of this device also allow the wire “OR”–ing of
several levels of gating for minimization of gate and package count.
The ability to control three parallel lines with minimum propagation delay
from a single point makes the MC10H210 particularly useful in clock distribution
applications where minimum clock skew is desired.
• Propagation Delay Average, 1.0 ns Typical
• Power Dissipation, 160 mW Typical
• Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
• Voltage Compensated
• MECL 10K–Compatible
MAXIMUM RATINGS
Characteristic Symbol Rating Unit
Power Supply (VCC = 0) V
EE
–8.0 to 0 Vdc
Input Voltage (VCC = 0) V
I
0 to V
EE
Vdc
Output Current— Continuous
— Surge
I
out
50
100
mA
Operating Temperature Range T
A
0 to +75 °C
Storage Temperature Range— Plastic
— Ceramic
T
stg
–55 to +150
–55 to +165
°C
°C
ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note)
0° 25° 75°
Characteristic Symbol Min Max Min Max Min Max Unit
Power Supply Current I
E
— 42 — 38 — 42 mA
Input Current High I
inH
— 720 — 450 — 450 µA
Input Current Low I
inL
0.5 — 0.5 — 0.3 — µA
High Output Voltage V
OH
–1.02 –0.84 –0.98 –0.81 –0.92 –0.735 Vdc
Low Output Voltage V
OL
–1.95 –1.63 –1.95 –1.63 –1.95 –1.60 Vdc
High Input Voltage V
IH
–1.17 –0.84 –1.13 –0.81 –1.07 –0.735 Vdc
Low Input Voltage V
IL
–1.95 –1.48 –1.95 –1.48 –1.95 –1.45 Vdc
AC PARAMETERS
Propagation Delay t
pd
0.5 1.55 0.55 1.55 0.6 1.7 ns
Rise Time t
r
0.75 1.8 0.75 1.9 0.8 2.0 ns
Fall Time t
f
0.75 1.8 0.75 1.9 0.8 2.0 ns
NOTE:
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,
after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed
circuit board and transverse air flow greater than 500 Iinear fpm is maintained. Outputs are terminated
through a 50–ohm resistor to –2.0 volts.
Note: If crosstalk is present, double bypass capacitor to 0.2 µF.
LOGIC DIAGRAM
DIP
PIN ASSIGNMENT
V
CC1
A
OUT
A
OUT
A
OUT
A
IN
A
IN
A
IN
V
EE
V
CC2
V
CC1
B
OUT
B
OUT
B
OUT
B
IN
B
IN
B
IN
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
12
11
10
9
13
14
2
7
6
5
3
4
V
CC1
= PINS 1, 15
V
CC2
= PIN 16
VEE = PIN 8
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
T ables on page 6–11 of the Motorola MECL Data
Book (DL122/D).