Motorola MC10H208FN, MC10H208L, MC10H208P Datasheet



SEMICONDUCTOR TECHNICAL DATA

1

REV 8

 Motorola, Inc. 1997

4/97

!   
"  !

High–Performance Silicon–Gate CMOS

The MC74HC125A and MC74HC126A are identical in pinout to the LS125
and LS126. The device inputs are compatible with standard CMOS outputs;
with pullup resistors, they are compatible with LSTTL outputs.

The HC125A and HC126A noninverting buffers are designed to be used
with 3–state memory address drivers, clock drivers, and other bus–oriented
systems. The devices have four separate output enables that are active–low
(HC125A) or active–high (HC126A).

• Output Drive Capability: 15 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 72 FETs or 18 Equivalent Gates

LOGIC DIAGRAM

HC125A

Active–Low Output Enables

HC126A

Active–High Output Enables

Y1

Y2

Y4

3

6

8

11

13

12

10

9

4

5

1

2

A1

OE1

A2

OE2

A3

OE3

A4

OE4

PIN 14 = V

CC

PIN 7 = GND

A1

OE1

A2

OE2

A3

OE3

A4

OE4

Y3

Y1

Y2

Y4

Y3

13

12

10

9

4

5

1

23

6

8

11

FUNCTION TABLE

HC125A

Inputs Output

AOE Y

HL H
LL L
XH Z

HC126A

Inputs Output

AOE Y

HH H
LH L
XL Z




PIN ASSIGNMENT

11

12

13

14

8

9

105

4

3

2

1

7

6

OE3

Y4

A4

OE4

V

CC

Y3

A3

OE2

Y1

A1

OE1

GND

Y2

A2

N SUFFIX

14–LEAD PLASTIC DIP PACKAGE

CASE 646–06

ORDERING INFORMATION

MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT

Plastic
SOIC
TSSOP

D SUFFIX

14–LEAD PLASTIC SOIC PACKAGE

CASE 751A–03

DT SUFFIX

14–LEAD PLASTIC TSSOP PACKAGE

CASE 948G–01

MC74HC125A MC74HC126A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

2

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

V

CC

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

V

V

in

DC Input Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

V

out

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

I

in

DC Input Current, per Pin

± 20

mA

I

out

DC Output Current, per Pin

± 35

mA

I

CC

DC Supply Current, VCC and GND Pins

± 75

mA

Î

Î

P

D

ОООООООООООО

Î

Power Dissipation in Still Air Plastic DIP†

SOIC Package†

TSSOP Package†

ÎÎÎÎ

Î

750
500
450

Î

Î

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

T

L

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP, SOIC or TSSOP Package)

260

_

C

*Maximum Ratings are those values beyond which damage to the device may occur .

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

Max

Unit

V

CC

DC Supply Voltage (Referenced to GND)

2.0

6.0

V

Vin, V

out

DC Input Voltage, Output Voltage
(Referenced to GND)

0

V

CC

V

T

A

Operating Temperature, All Package Types

– 55

+ 125

_

C

ÎÎ

Î

tr, t

f

ОООООООООООО

Î

Input Rise and Fall Time VCC = 2.0 V

(Figure 1) VCC = 4.5 V

VCC = 6.0 V

Î

Î

0
0
0

Î

Î

1000

500
400

Î

Î

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

Symbol

Parameter

Test Conditions

V

CC

V

– 55 to

25_C

v

85_Cv 125_C

Unit

ÎÎ

Î

ÎÎ

Î

V

IH

ООООООО

Î

ООООООО

Î

Minimum High–Level Input
Voltage

ООООООО

Î

ООООООО

Î

V

out

= VCC – 0.1 V

|I

out

| v 20 µA

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

ÎÎ

1.5

2.1

3.15

4.2

ÎÎ

Î

ÎÎ

Î

1.5

2.1

3.15

4.2

ÎÎ

Î

ÎÎ

Î

1.5

2.1

3.15

4.2

Î

Î

Î

Î

V

ÎÎ

Î

ÎÎ

Î

V

IL

ООООООО

Î

ООООООО

Î

Maximum Low–Level Input
Voltage

ООООООО

Î

ООООООО

Î

V

out

= 0.1 V

|I

out

| v 20 µA

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

ÎÎ

0.5

0.9

1.35

1.8

ÎÎ

Î

ÎÎ

Î

0.5

0.9

1.35

1.8

ÎÎ

Î

ÎÎ

Î

0.5

0.9

1.35

1.8

Î

Î

Î

Î

V

ÎÎ

Î

V

OH

ООООООО

Î

Minimum High–Level Output
Voltage

ООООООО

Î

Vin = V

IH

|I

out

| v 20 µA

ÎÎ

Î

2.0

4.5

6.0

ÎÎ

1.9

4.4

5.9

ÎÎ

Î

1.9

4.4

5.9

ÎÎ

Î

1.9

4.4

5.9

Î

Î

V

ÎÎÎОООООООÎООООООО

Î

Vin = V

IH

|I

out

| v 3.6 mA

|I

out

| v 6.0 mA

|I

out

| v 7.8 mA

ÎÎ

Î

3.0

4.5

6.0

ÎÎ

2.48

3.98

5.48

ÎÎ

Î

2.34

3.84

5.34

ÎÎ

Î

2.2

3.7

5.2

Î

Î

ÎÎ

Î

ÎÎ

Î

V

OL

ООООООО

Î

ООООООО

Î

Maximum Low–Level Output
Voltage

ООООООО

Î

ООООООО

Î

Vin = V

IL

|I

out

| v 20 µA

ÎÎ

Î

ÎÎ

Î

2.0

4.5

6.0

ÎÎ

ÎÎ

0.1

0.1

0.1

ÎÎ

Î

ÎÎ

Î

0.1

0.1

0.1

ÎÎ

Î

ÎÎ

Î

0.1

0.1

0.1

Î

Î

Î

Î

V

ÎÎ

Î

ÎÎ

Î

ООООООО

Î

ООООООО

Î

ООООООО

Î

ООООООО

Î

Vin = V

IL

|I

out

| v 3.6 mA

|I

out

| v 6.0 mA

|I

out

| v 7.8 mA

ÎÎ

Î

ÎÎ

Î

3.0

4.5

6.0

ÎÎ

ÎÎ

0.26

0.26

0.26

ÎÎ

Î

ÎÎ

Î

0.33

0.33

0.33

ÎÎ

Î

ÎÎ

Î

0.4

0.4

0.4

Î

Î

Î

Î

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir­cuit. For proper operation, Vin and
V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

MC74HC125A MC74HC126A

High–Speed CMOS Logic Data
DL129 — Rev 6

3 MOTOROLA

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

Unit

v

125_C

v

85_C

– 55 to

25_C

V

CC

V

Test Conditions

Parameter

Symbol

I

in

Maximum Input Leakage Current

Vin = VCC or GND

6.0

± 0.1

± 1.0

± 1.0

µA

ÎÎ

Î

ÎÎ

Î

I

OZ

ООООООО

Î

ООООООО

Î

Maximum Three–State Leakage
Current

ООООООО

Î

ООООООО

Î

Output in High–Impedance State
Vin = VIL or V

IH

V

out

= VCC or GND

ÎÎ

Î

ÎÎ

Î

6.0

ÎÎ

ÎÎ

± 0.5

ÎÎ

Î

ÎÎ

Î

± 5.0

ÎÎ

Î

ÎÎ

Î

± 10

Î

Î

Î

Î

µA

I

CC

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
I

out

= 0 µA

6.0

4.0

40

160

µA

NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

AC ELECTRICAL CHARACTERISTICS (C

L

= 50 pF, Input tr = tf = 6.0 ns)

Guaranteed Limit

Symbol

Parameter

V

CC

V

– 55 to

25_C

v

85_Cv 125_C

Unit

ÎÎ

Î

ÎÎ

Î

t

PLH

,

t

PHL

ООООООООООООООО

Î

ООООООООООООООО

Î

Maximum Propagation Delay, Input A to Output Y

(Figures 1 and 3)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

ÎÎ

90
36
18
15

ÎÎ

Î

ÎÎ

Î

115

45
23
20

ÎÎ

Î

ÎÎ

Î

135

60
27
23

Î

Î

Î

Î

ns

ÎÎ

Î

ÎÎ

Î

t

PLZ

,

t

PHZ

ООООООООООООООО

Î

ООООООООООООООО

Î

Maximum Propagation Delay, Output Enable to Y

(Figures 2 and 4)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

ÎÎ

120

45
24
20

ÎÎ

Î

ÎÎ

Î

150

60
30
26

ÎÎ

Î

ÎÎ

Î

180

80
36
31

Î

Î

Î

Î

ns

ÎÎ

Î

ÎÎ

Î

t

PZL

,

t

PZH

ООООООООООООООО

Î

ООООООООООООООО

Î

Maximum Propagation Delay, Output Enable to Y

(Figures 2 and 4)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

ÎÎ

90
36
18
15

ÎÎ

Î

ÎÎ

Î

115

45
23
20

ÎÎ

Î

ÎÎ

Î

135

60
27
23

Î

Î

Î

Î

ns

ÎÎ

Î

ÎÎ

Î

t

TLH

,

t

THL

ООООООООООООООО

Î

ООООООООООООООО

Î

Maximum Output Transition Time, Any Output

(Figures 1 and 3)

ÎÎ

Î

ÎÎ

Î

2.0

3.0

4.5

6.0

ÎÎ

ÎÎ

60
22
12
10

ÎÎ

Î

ÎÎ

Î

75
28
15
13

ÎÎ

Î

ÎÎ

Î

90
34
18
15

Î

Î

Î

Î

ns

C

in

Maximum Input Capacitance

—

10

10

10

pF

ÎÎ

Î

C

out

ООООООООООООООО

Î

Maximum Three–State Output Capacitance
(Output in High–Impedance State)

ÎÎ

Î

—

ÎÎ15ÎÎ

Î

15

ÎÎ

Î

15

Î

Î

pF

NOTE:For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–

Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

C

PD

Power Dissipation Capacitance (Per Buffer)*

30

pF

*Used to determine the no–load dynamic power consumption: PD = CPD V

CC

2

f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).

MC74HC125A MC74HC126A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

4

SWITCHING W AVEFORMS

Figure 1.

Figure 2.

OUTPUT Y

50%

50%

50%

50%

90%

10%

V

CC

V

CC

GND

GND
HIGH

IMPEDANCE
V

OL

V

OH

OUTPUT Y

OUTPUT Y

OE (HC125A)

OE (HC126A)

t

PZLtPLZ

t

PZHtPHZ

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

Figure 3. Test Circuit

*Includes all probe and jig capacitance

Figure 4. Test Circuit

OUTPUT

TEST POINT

CL *

1 k

Ω

CONNECT TO VCC WHEN
TESTING t

PLZ

AND t

PZL.

CONNECT TO GND WHEN
TESTING t

PHZ

and t

PZH.

DEVICE
UNDER

TEST

HIGH
IMPEDANCE

90%

10%

50%

90%

50%

10%

V

CC

GND

t

f

t

r

t

PLH

t

PHL

t

TLH

t

THL

INPUT A

HC125A

(1/4 OF THE DEVICE)

HC126A

(1/4 OF THE DEVICE)

OE

A

V

CC

Y

OE

A

V

CC

Y

MC74HC125A MC74HC126A

High–Speed CMOS Logic Data
DL129 — Rev 6

5 MOTOROLA

OUTLINE DIMENSIONS

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751A–03

ISSUE F

MIN MINMAX MAX

MILLIMETERS INCHES

DIM

A
B
C
D
F
G
J
K
M
P
R

8.55

3.80

1.35

0.35

0.40

0.19

0.10
0

°

5.80

0.25

8.75

4.00

1.75

0.49

1.25

0.25

0.25
7

°

6.20

0.50

0.337

0.150

0.054

0.014

0.016

0.008

0.004
0

°

0.228

0.010

0.344

0.157

0.068

0.019

0.049

0.009

0.009
7

°

0.244

0.019

1.27 BSC 0.050 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

–A–

–B–

P 7 PL

G

C

K

SEATING
PLANE

D 14 PL

M

J

R

X 45°

1

7

814

0.25 (0.010) T B A

M

S S

B0.25 (0.010)

M M

F

N SUFFIX

PLASTIC DIP PACKAGE

CASE 646–06

ISSUE L

NOTES:

1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.

2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.

4. ROUNDED CORNERS OPTIONAL.

17

14 8

B

A
F

HG D

K

C

N

L

J

M

SEATING
PLANE

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.715 0.770 18.16 19.56
B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78

G 0.100 BSC 2.54 BSC

H 0.052 0.095 1.32 2.41
J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
L 0.300 BSC 7.62 BSC

M 0 10 0 10

N 0.015 0.039 0.39 1.01

____

MC74HC125A MC74HC126A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

6

OUTLINE DIMENSIONS

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948G–01

ISSUE O

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C ––– 1.20 ––– 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K 0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L 6.40 BSC 0.252 BSC

M 0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.

____

S

U0.15 (0.006) T

2X L/2

S

U

M

0.10 (0.004) V

S

T

L

–U–

SEATING
PLANE

0.10 (0.004)

–T–

SECTION N–N

DETAIL E

J

J1

K

K1

DETAIL E

F

M

–W–

0.25 (0.010)

8

14

7

1

PIN 1
IDENT.

H

G

A

D

C

B

S

U0.15 (0.006) T

–V–

14X REFK

N

N

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MC74HC125A/D

◊