Motorola MC10H208FN, MC10H208L, MC10H208P Datasheet
SEMICONDUCTOR TECHNICAL DATA
1
REV 8
Motorola, Inc. 1997
4/97
!
" !
High–Performance Silicon–Gate CMOS
The MC74HC125A and MC74HC126A are identical in pinout to the LS125
and LS126. The device inputs are compatible with standard CMOS outputs;
with pullup resistors, they are compatible with LSTTL outputs.
The HC125A and HC126A noninverting buffers are designed to be used
with 3–state memory address drivers, clock drivers, and other bus–oriented
systems. The devices have four separate output enables that are active–low
(HC125A) or active–high (HC126A).
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 72 FETs or 18 Equivalent Gates
LOGIC DIAGRAM
HC125A
Active–Low Output Enables
HC126A
Active–High Output Enables
Y1
Y2
Y4
3
6
8
11
13
12
10
9
4
5
1
2
A1
OE1
A2
OE2
A3
OE3
A4
OE4
PIN 14 = V
CC
PIN 7 = GND
A1
OE1
A2
OE2
A3
OE3
A4
OE4
Y3
Y1
Y2
Y4
Y3
13
12
10
9
4
5
1
23
6
8
11
FUNCTION TABLE
HC125A
Inputs Output
AOE Y
HL H
LL L
XH Z
HC126A
Inputs Output
AOE Y
HH H
LH L
XL Z
PIN ASSIGNMENT
11
12
13
14
8
9
105
4
3
2
1
7
6
OE3
Y4
A4
OE4
V
CC
Y3
A3
OE2
Y1
A1
OE1
GND
Y2
A2
N SUFFIX
14–LEAD PLASTIC DIP PACKAGE
CASE 646–06
ORDERING INFORMATION
MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT
Plastic
SOIC
TSSOP
D SUFFIX
14–LEAD PLASTIC SOIC PACKAGE
CASE 751A–03
DT SUFFIX
14–LEAD PLASTIC TSSOP PACKAGE
CASE 948G–01
MC74HC125A MC74HC126A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
2
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
V
in
DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
V
out
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
I
in
DC Input Current, per Pin
± 20
mA
I
out
DC Output Current, per Pin
± 35
mA
I
CC
DC Supply Current, VCC and GND Pins
± 75
mA
Î
Î
P
D
ОООООООООООО
Î
Power Dissipation in Still Air Plastic DIP†
SOIC Package†
TSSOP Package†
ÎÎÎÎ
Î
750
500
450
Î
Î
mW
T
stg
Storage Temperature
– 65 to + 150
_
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
260
_
C
*Maximum Ratings are those values beyond which damage to the device may occur .
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
Vin, V
out
DC Input Voltage, Output Voltage
(Referenced to GND)
0
V
CC
V
T
A
Operating Temperature, All Package Types
– 55
+ 125
_
C
ÎÎ
Î
tr, t
f
ОООООООООООО
Î
Input Rise and Fall Time VCC = 2.0 V
(Figure 1) VCC = 4.5 V
VCC = 6.0 V
Î
Î
0
0
0
Î
Î
1000
500
400
Î
Î
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
V
CC
V
– 55 to
25_C
v
85_Cv 125_C
Unit
ÎÎ
Î
ÎÎ
Î
V
IH
ООООООО
Î
ООООООО
Î
Minimum High–Level Input
Voltage
ООООООО
Î
ООООООО
Î
V
out
= VCC – 0.1 V
|I
out
| v 20 µA
ÎÎ
Î
ÎÎ
Î
2.0
3.0
4.5
6.0
ÎÎ
ÎÎ
1.5
2.1
3.15
4.2
ÎÎ
Î
ÎÎ
Î
1.5
2.1
3.15
4.2
ÎÎ
Î
ÎÎ
Î
1.5
2.1
3.15
4.2
Î
Î
Î
Î
V
ÎÎ
Î
ÎÎ
Î
V
IL
ООООООО
Î
ООООООО
Î
Maximum Low–Level Input
Voltage
ООООООО
Î
ООООООО
Î
V
out
= 0.1 V
|I
out
| v 20 µA
ÎÎ
Î
ÎÎ
Î
2.0
3.0
4.5
6.0
ÎÎ
ÎÎ
0.5
0.9
1.35
1.8
ÎÎ
Î
ÎÎ
Î
0.5
0.9
1.35
1.8
ÎÎ
Î
ÎÎ
Î
0.5
0.9
1.35
1.8
Î
Î
Î
Î
V
ÎÎ
Î
V
OH
ООООООО
Î
Minimum High–Level Output
Voltage
ООООООО
Î
Vin = V
IH
|I
out
| v 20 µA
ÎÎ
Î
2.0
4.5
6.0
ÎÎ
1.9
4.4
5.9
ÎÎ
Î
1.9
4.4
5.9
ÎÎ
Î
1.9
4.4
5.9
Î
Î
V
ÎÎÎОООООООÎООООООО
Î
Vin = V
IH
|I
out
| v 3.6 mA
|I
out
| v 6.0 mA
|I
out
| v 7.8 mA
ÎÎ
Î
3.0
4.5
6.0
ÎÎ
2.48
3.98
5.48
ÎÎ
Î
2.34
3.84
5.34
ÎÎ
Î
2.2
3.7
5.2
Î
Î
ÎÎ
Î
ÎÎ
Î
V
OL
ООООООО
Î
ООООООО
Î
Maximum Low–Level Output
Voltage
ООООООО
Î
ООООООО
Î
Vin = V
IL
|I
out
| v 20 µA
ÎÎ
Î
ÎÎ
Î
2.0
4.5
6.0
ÎÎ
ÎÎ
0.1
0.1
0.1
ÎÎ
Î
ÎÎ
Î
0.1
0.1
0.1
ÎÎ
Î
ÎÎ
Î
0.1
0.1
0.1
Î
Î
Î
Î
V
ÎÎ
Î
ÎÎ
Î
ООООООО
Î
ООООООО
Î
ООООООО
Î
ООООООО
Î
Vin = V
IL
|I
out
| v 3.6 mA
|I
out
| v 6.0 mA
|I
out
| v 7.8 mA
ÎÎ
Î
ÎÎ
Î
3.0
4.5
6.0
ÎÎ
ÎÎ
0.26
0.26
0.26
ÎÎ
Î
ÎÎ
Î
0.33
0.33
0.33
ÎÎ
Î
ÎÎ
Î
0.4
0.4
0.4
Î
Î
Î
Î
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
V
out
should be constrained to the
range GND v (Vin or V
out
) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
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