SEMICONDUCTOR TECHNICAL DATA
2–284
REV 5
Motorola, Inc. 1996
3/93
The MC10H188 is a high–speed Hex Buffer with a common Enable input.
When Enable is in the high–state, all outputs are in the low–state. When Enable
is in the low–state, the outputs take the same state as the inputs.
This MECL 10H part is a functional/pinout duplication of the standard MECL
10K family part, with 100% improvement in propagation delay and no increase
in power–supply current.
• Propagation Delay, 1.3 ns Typical Data–to–Output
• Power Dissipation 180 mW Typ/Pkg (No Load)
• Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
• Voltage Compensated
• MECL 10K–Compatible
MAXIMUM RATINGS
Characteristic Symbol Rating Unit
Power Supply (VCC = 0) V
EE
–8.0 to 0 Vdc
Input Voltage (VCC = 0) V
I
0 to V
EE
Vdc
Output Current— Continuous
— Surge
I
out
50
100
mA
Operating Temperature Range T
A
0 to +75 °C
Storage Temperature Range— Plastic
— Ceramic
T
stg
–55 to +150
–55 to +165
°C
°C
ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note)
0° 25° 75°
Characteristic Symbol Min Max Min Max Min Max Unit
Power Supply Current I
E
— 46 — 42 — 46 mA
Input Current High I
inH
— 495 — 310 — 310 µA
Input Current Low I
inL
0.5 — 0.5 — 0.3 — µA
High Output Voltage V
OH
–1.02 –0.84 –0.98 –0.81 –0.92 –0.735 Vdc
Low Output Voltage V
OL
–1.95 –1.63 –1.95 –1.63 –1.95 –1.60 Vdc
High Input Voltage V
IH
–1.17 –0.84 –1.13 –0.81 –1.07 –0.735 Vdc
Low Input Voltage V
IL
–1.95 –1.48 –1.95 –1.48 –1.95 –1.45 Vdc
AC PARAMETERS
Propagation Delay
Enable
Data
t
pd
0.7
0.7
2.2
1.9
0.7
0.7
2.2
1.9
0.7
0.7
2.2
1.9
ns
Rise Time t
r
0.7 2.4 0.7 2.4 0.7 2.4 ns
Fall Time t
f
0.7 2.4 0.7 2.4 0.7 2.4 ns
NOTE:
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,
after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit
board and transverse air flow greater than 500 Ifpm is maintained. Outputs are terminated through a
50–ohm resistor to –2.0 volts.
X Y OUT
Inputs Output
LOGIC DIAGRAM
DIP
PIN ASSIGNMENT
V
CC1
A
OUT
B
OUT
C
OUT
A
IN
B
IN
C
IN
V
EE
V
CC2
F
OUT
E
OUT
D
OUT
F
IN
E
IN
D
IN
COMMON
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
V
CC1
= Pin 1
V
CC2
= Pin 16
VEE = Pin 8
TRUTH TABLE
12
15
11
14
10
13
7
4
6
3
5
2
9
X
Y
OUT
L
L
H
H
L
H
L
H
L
H
L
L
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
T ables on page 6–11 of the Motorola MECL Data
Book (DL122/D).