Motorola MC10H145FN, MC10H145L, MC10H145P Datasheet


SEMICONDUCTOR TECHNICAL DATA
2–233
REV 5
Motorola, Inc. 1996
3/93
    
The MC10H145 is a 16 x 4 bit register file. The active-low chip select allows
The operating mode of the register file is controlled by the WE
input. When
WE
is “low” the device is in the write mode, the outputs are “low” and the data
present at Dn input is stored at the selected address, when WE
is “high,” the device is in the read mode — the data state at the selected location is present at the Qn outputs.
Address Access Time, 4.5 ns Typical
Power Dissipation, 700 mW Typical
Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
Voltage Compensated
MECL 10K-Compatible
MAXIMUM RATINGS
Characteristic Symbol Rating Unit
Power Supply (VCC = 0) V
EE
–8.0 to 0 Vdc
Input Voltage (VCC = 0) V
I
0 to V
EE
Vdc
Output Current— Continuous
— Surge
I
out
50
100
mA
Operating Temperature Range T
A
0 to +75 °C
Storage Temperature Range— Plastic
— Ceramic
T
stg
–55 to +150 –55 to +165
°C
ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note)
0° 25° 75°
Ch
aracteristic
Symbol
Min Max Min Max Min Max
Unit
Power Supply Current I
E
160 163 165 mA
Input Current High I
inH
375 220 220 µA
Input Current Low I
inL
0.5 0.5 0.3 µA
High Output Voltage V
OH
–1.02 –0.84 –0.98 –0.81 –0.92 –0.735 Vdc
Low Output Voltage V
OL
–1.95 –1.63 –1.95 –1.63 –1.95 –1.60 Vdc
High Input Voltage V
IH
–1.17 –0.84 –1.13 –0.81 –1.07 –0.735 Vdc
Low Input Voltage V
IL
–1.95 –1.48 –1.95 –1.48 –1.95 –1.45 Vdc
NOTE:
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 Ifpm is maintained. Outputs are terminated through a 50-ohm resistor to –2.0 volts.

DIP
PIN ASSIGNMENT
Q1 Q0 CS D1 D0 A3 A2
V
EE
V
CC
Q2 Q3 WE D3 D2 A0 A1
16 15 14 13 12 11 10
9
1 2 3 4 5 6 7 8
TRUTH TABLE
MODE INPUT OUTPUT
CS
WE D
n
Write “0” L
X
Q
n
Write “1” Read Disabled
L L H
LLL
H
X X
L LH
L
Q
Q-State of Addressed Cell
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
T ables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
MC10H145
MOTOROLA MECL Data
DL122 — Rev 6
2–234
AC PARAMETERS
MC10H145
TA = 0 to +75°C,
VEE = –5.2 Vdc ±5%
Characteristics Symbol Min Max Unit Conditions
Read Mode
Chip Select Access Time Chip Select Recovery Time Address Access Time
t
ACS
t
RCS t
AA
0 0 0
4.0
4.0
6.0
ns Measured from 50% of input to 50%
of output. See Note 2.
Write Mode
Write Pulse Width Data Setup Time Prior to Write Data Hold Time After Write Address Setup Time Prior to Write Address Hold Time After Write Chip Select Setup Time Prior to Write Chip Select Hold Time After Write Write Disable Time Write Recovery Time
t
W
t
WSD
t
WHD
t
WSA
t
WHA
t
WSCS
t
WHCS
t
WS
t
WR
6.0 0
1.5
3.5
1.5 0
1.5
1.0
1.0
— — — — — — —
4.0
4.0
ns t
WSA
= 3.5 ns Measured at 50% of input to 50% of output. tW = 6.0 ns.
Chip Enable Strobe Mode
Data Setup Prior to Chip Select Write Enable Setup Prior to Chip Select Address Setup Prior to Chip Select Data Hold Time After Chip Select Write Enable Hold Time After Chip Select Address Hold Time After Chip Select Chip Select Minimum Pulse Width
t
CSD
t
CSW
t
CSA
t
CHD
t
CHW
t
CHA t
CS
0 0 0
1.0 0
2.0
4.0
— — — — — — —
ns Guaranteed but not tested on
standard product. See Figure 1.
Rise and Fall Time
Address to Output CS to Output
tr, t
f
0.6
0.6
2.5
2.5
ns Measured between 20% and 80%
points.
Capacitance
Input Capacitance Output Capacitance
C
in
C
out
— —
6.0
8.0
pF Measured with a pulse technique.
NOTES: 1. T est circuit characteristics: RT = 50 , MC10H145. CL p 5.0 pF (including jig and Stray Capacitance). Delay should be derated 30 ps/pF for
capacitive loads up to 50 pF.
2. The maximum Address Access Time is guaranteed to be the worst-case bit in the memory .
3. For proper use of MECL in a system environment, consult MECL System Design Handbook.
FIGURE 1 — CHIP ENABLE STROBE MODE
A
D
IN
WE
CS
T
CSA
T
CSW
T
CSD
T
CS
T
CHA
T
CHD
T
CHW
MC10H145
2–235 MOTOROLAMECL Data
DL122 — Rev 6
CSQ2Q1
BLOCK DIAGRAM
DATA
OUT
BUFFER
SENSE
16 X 4 MEMORY
CELL ARRAY
WRITE AND
DATA IN BUFFER
Address Buffer/
1/16 Decoder
2
Q0
5
D1
13
WE
10
9
7
6
A1
Q3
11514 3
DATA
OUT
BUFFER
DATA
OUT
BUFFER
DATA
OUT
BUFFER
SENSE SENSE SENSE
41112
D2 D3D0
A2
A3
A0
CHIP SELECT BUFFER
MC10H145
MOTOROLA MECL Data
DL122 — Rev 6
2–236
OUTLINE DIMENSIONS
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 775–02
ISSUE C
NOTES:
1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM –T–, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
–M–
–N–
–L–
Y BRK
W
V
D
D
S
L–M
M
0.007 (0.180) N
S
T
S
L–M
M
0.007 (0.180) N
S
T
S
L–M
S
0.010 (0.250) N
S
T
X
G1
B
U
Z
VIEW D–D
20 1
S
L–M
M
0.007 (0.180) N
S
T
S
L–M
M
0.007 (0.180) N
S
T
S
L–M
S
0.010 (0.250) N
S
T
C
G
VIEW S
E
J
R
Z
A
0.004 (0.100)
–T–
SEATING PLANE
S
L–M
M
0.007 (0.180) N
S
T
S
L–M
M
0.007 (0.180) N
S
T
H
VIEW S
K
K1
F
G1
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.385 0.395 9.78 10.03 B 0.385 0.395 9.78 10.03 C 0.165 0.180 4.20 4.57 E 0.090 0.110 2.29 2.79 F 0.013 0.019 0.33 0.48 G 0.050 BSC 1.27 BSC H 0.026 0.032 0.66 0.81 J 0.020 ––– 0.51 ––– K 0.025 ––– 0.64 ––– R 0.350 0.356 8.89 9.04 U 0.350 0.356 8.89 9.04
V 0.042 0.048 1.07 1.21 W 0.042 0.048 1.07 1.21 X 0.042 0.056 1.07 1.42 Y ––– 0.020 ––– 0.50
Z 2 10 2 10
G1 0.310 0.330 7.88 8.38 K1 0.040 ––– 1.02 –––
____
MC10H145
2–237 MOTOROLAMECL Data
DL122 — Rev 6
OUTLINE DIMENSIONS
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
B
F
C
S
H
G
D
J
L
M
16 PL
SEATING
18
916
K
PLANE
–T–
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.740 0.770 18.80 19.55 B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77 G 0.100 BSC 2.54 BSC H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7.74 M 0 10 0 10 S 0.020 0.040 0.51 1.01
____
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY.
–A–
–B–
–T–
F
E
G
N
K
C
SEATING PLANE
16 PLD
S
A
M
0.25 (0.010) T
16 PLJ
S
B
M
0.25 (0.010) T
M
L
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.750 0.785 19.05 19.93 B 0.240 0.295 6.10 7.49 C ––– 0.200 ––– 5.08 D 0.015 0.020 0.39 0.50 E 0.050 BSC 1.27 BSC F 0.055 0.065 1.40 1.65 G 0.100 BSC 2.54 BSC H 0.008 0.015 0.21 0.38 K 0.125 0.170 3.18 4.31 L 0.300 BSC 7.62 BSC M 0 15 0 15 N 0.020 0.040 0.51 1.01
____
16 9
18
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MC10H145/D
*MC10H145/D*
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