SEMICONDUCTOR TECHNICAL DATA
The MC10H136 is a high speed synchronous hexadecimal counter. This
10H part is a functional/pinout duplication of the standard MECL 10K family
part, with 100% improvement in counting frequency and no increase in
power-supply current.
• Counting Frequency , 250 MHz Minimum • Voltage Compensated
• Power Dissipation, 625 mW Typical • MECL 10K-Compatible
• Improved Noise Margin 150 mV
(Over Operating Voltage and Temperature Range)
MAXIMUM RATINGS
Characteristic Symbol Rating Unit
Power Supply (VCC = 0) V
Input Voltage (VCC = 0) V
Output Current — Continuous
— Surge
Operating T emperature Range T
Storage T emperature Range — Plastic
— Ceramic
EE
I
I
out
A
T
stg
ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note)
0° 25° 75°
Characteristic Symbol Min Max Min Max Min Max Unit
Power Supply Current I
Input Current High
Pins 5, 6, 11, 12, 13
Pin 9
Pin 7
Pin 10
Input Current Low I
High Output Voltage V
Low Output Voltage V
High Input Voltage V
Low Input Voltage V
I
E
inH
inL
OH
OL
IH
— 165 — 150 — 165 mA
—
430
—
670
—
535
—
380
—
—
—
—
0.5 — 0.5 — 0.3 — µA
–1.02 –0.84 –0.98 –0.81 –0.92 –0.735 Vdc
–1.95 –1.63 –1.95 –1.63 –1.95 –1.60 Vdc
–1.17 –0.84 –1.13 –0.81 –1.07 –0.735 Vdc
–1.95 –1.48 –1.95 –1.48 –1.95 –1.45 Vdc
IL
AC PARAMETERS
Propagation Delay
Clock to Q
Clock to Carry Out
Carry in to Carry
Out
Set-up Time
Data (D0 to C)
Select (S to C)
Carry In (Cin to C)
(C to Cin)
Hold Time
Data (C to D0)
Select (C to S)
Carry In (C to Cin)
(Cin to C)
Counting Frequency f
Rise Time t
Fall Time t
NOTE:
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table, after thermal
equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse
air flow greater than 500 Iinear fpm is maintained. Outputs are terminated through a 50-ohm resistor to –2.0 volts.
t
pd
t
set
t
hold
count
r
f
0.7
2.3
4.8
2.5
0.7
1.0
0.7
—
2.0
—
3.5
—
2.0
—
0
—
0
—
–0.5
—
0
—
2.2
1.0
0.7
2.0
3.5
2.0
0
0
–0.5
0
2.2
250 — 250 — 250 — MHz
0.5 2.3 0.5 2.4 0.5 2.5 ns
0.5 2.3 0.5 2.4 0.5 2.5 ns
–8.0 to 0 Vdc
0 to V
EE
50
100
0 to +75 °C
–55 to +150
–55 to +165
275
420
335
240
2.4
4.9
2.6
—
—
—
—
0.7
1.0
0.7
—
2.0
—
3.5
—
2.0
—
0
—
0
—
–0.5
—
0
—
2.2
Vdc
mA
°C
°C
275
420
335
240
2.5
5.0
2.7
—
—
—
—
—
—
—
—
µA
ns
ns
ns
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
FUNCTION SELECT TABLE
CIN
S1 S2 Operating Mode
X
L
LH
H
L
L
H
H
H
X
H
SEQUENTIAL TRUTH TABLE *
INPUTS OUTPUTS
LLLHH H HHLL LX
L
X
X
H
L
X
X
H
L
X
X
H
L
X
L
L
H
L
H
H
H
H
* Truth table shows logic states assuming inputs vary in
** A clock H is defined as a clock input transition from a
X
H
X
X
H
X
X
H
L
HH L L
L
X
X
L
X
X
L
X
X
L
X
X
sequence shown from top to bottom.
low to a high logic level.
DIP PIN ASSIGNMENT
V
CC1
Q2
Q3
C
OUT
D3
D2
S2
V
EE
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
T ables on page 6–11 of the Motorola MECL Data
Preset (Program)
LL
Increment (Count Up)
Hold Count
H
Decrement (Count Down)
L
Hold Count
L
Hold (Stop Count)
H
CarryInClock
D3S1 S2 D0 D1 D2
X
X
L
X
X
L
X
X
L
X
X
H
X
X
H
X
X
X
X
L
X
X
L
X
X
L
X
X
L
X
X
1
2
3
4
5
6
7
8
Book (DL122/D).
* *
H
H
H
L
H
H
H
H
H
H
H
16
15
14
13
12
11
10
Q0
9
Q1 Q2 Q3
H
HHL
LH H
HH L
H
H
H
H
LLL
H
LL LL L
HHH H H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
LLL
V
CC2
Q1
Q0
CLOCK
D0
D1
C
IN
S1
Carry
Out
H
H
H
L
H
H
9/96
Motorola, Inc. 1996
2–1
REV 6
MC10H136
LOGIC DIAGRAM
S1 9
S2 7
Carry In
10
Q0
T
Q0
T T
C
Clock
13
12
D0
NOTE: FLIP-FLOPS WILL TOGGLE WHEN ALL T INPUTS ARE LOW.
14
Q0
Q1T
T
Q1
C
11
D1
15
Q1
APPLICATION INFORMATION
The MC10H136 is a high speed synchronous counter
that operates at 250 MHz. Counter operating modes
include count up, count down, pre-set and hold count.
This device allows the designer to use one basic counter
for many applications.
Q2T
T
T
Q2
T
C
6
D2
2
Q25D3
T
Q3
T
T
Q3
T
T
C
3
Q34 Carry Out
V
= Pin 1
CC1
V
= Pin 16
CC2
VEE= Pin 8
The S1, S2, control lines determine the operating
modes of the counter. In the pre-set mode, a clock pulse
is necessary to load the counter with the information
present on the data inputs (D0, D1, D2, and D3). Carry out
goes low on the terminal count or when the counter is
being pre-set.
MOTOROLA MECL Data
2–2
DL122 — Rev 6