MOTOROLA MC10H131MEL, MC10H131ML1, MC10H131ML2, MC10H131MR1, MC10H131MR2 Datasheet
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SEMICONDUCTOR TECHNICAL DATA
2–69
REV 5
Motorola, Inc. 1996
3/93
The MC10H131 is a MECL 10H part which is a functional/pinout duplication
of the standard MECL 10K family part, with 100% improvement in clock speed
and propagation delay and no increase in power–supply current.
• Propagation Delay, 1.0 ns Typical
• Power Dissipation, 235 mW Typical
• Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
• Voltage Compensated
• MECL 10K–Compatible
MAXIMUM RATINGS
Characteristic Symbol Rating Unit
Power Supply (VCC = 0) V
EE
–8.0 to 0 Vdc
Input Voltage (VCC = 0) V
I
0 to V
EE
Vdc
Output Current — Continuous
— Surge
I
out
50
100
mA
Operating T emperature Range T
A
0 to +75 °C
Storage T emperature Range — Plastic
— Ceramic
T
stg
–55 to +150
–55 to +165
°C
°C
ELECTRICAL CHARACTERISTICS (VEE = –5.2 V ±5%) (See Note)
0° 25° 75°
Characteristic Symbol Min Max Min Max Min Max Unit
Power Supply Current I
E
— 62 — 56 — 62 mA
Input Current High
Pins 6, 11
Pin 9
Pins 7, 10
Pins 4, 5, 12, 13
I
inH
—
—
—
—
530
660
485
790
—
—
—
—
310
390
285
465
—
—
—
—
310
390
285
465
µA
Input Current Low I
inL
0.5 — 0.5 — 0.3 — µA
High Output Voltage V
OH
–1.02 –0.84 –0.98 –0.81 –0.92 –0.735 Vdc
Low Output Voltage V
OL
–1.95 –1.63 –1.95 –1.63 –1.95 –1.60 Vdc
High Input Voltage V
IH
–1.17 –0.84 –1.13 –0.81 –1.07 –0.735 Vdc
Low Input Voltage V
IL
–1.95 –1.48 –1.95 –1.48 –1.95 –1.45 Vdc
AC PARAMETERS
Propagation Delay
Clock, CE
Set, Reset
t
pd
0.8
0.6
1.6
1.6
0.8
0.7
1.7
1.7
0.8
0.7
1.8
1.8
ns
Rise Time t
r
0.6 2.0 0.6 2.0 0.6 2.2 ns
Fall Time t
f
0.6 2.0 0.6 2.0 0.6 2.2 ns
Set–up Time t
set
0.7 — 0.7 — 0.7 — ns
Hold Time t
hold
0.8 — 0.8 — 0.8 — ns
T oggle Frequency f
tog
250 — 250 — 250 — MHz
NOTE:
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test table,
after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit
board and transverse air flow greater than 500 Iinear fpm is maintained. Outputs are terminated through
a 50–ohm resistor to –2.0 volts.
LOGIC DIAGRAM
DIP
PIN ASSIGNMENT
V
CC1
Q1
Q1
R1
S1
C
E1
D1
V
EE
V
CC2
Q2
Q2
R2
S2
C
E2
D2
C
C
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
V
CC1
= PIN 1
V
CC2
= PIN 16
VEE = PIN 8
S1 5
D1 7
CE1 6
R1 4
CC 9
R2 13
CE
2 11
D2 10
S2 12
Q1
Q
1
Q
2
Q2
2
3
14
15
CLOCKED TRUTH TABLE
N.D. = Not Defined
C = C
E + C
C
A clock H is a clock transition
from a low to a high state.
RS TRUTH TABLE
RSQ
n+1
L
L
L
H
L
H
Q
n
H
L
N.D.
H
H
CDQ
n+1
L
H
X
L
H
Q
n
L
HH
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
T ables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
MC10H131
MOTOROLA MECL Data
DL122 — Rev 6
2–70
APPLICATION INFORMATION
The MC10H131 is a dual master–slave type D flip–flop.
Asynchronous Set (S) and Reset (R) override Clock (CC)
and Clock Enable (CE
) inputs. Each flip–flop may be
clocked separately by holding the common clock in the
new low state and using the enable inputs for the clocking
function. If the common clock is to be used to clock the
flip–flop, the Clock Enable inputs must be in the low state.
In this case, the enable inputs perform the function of
controlling the common clock.
The output states of the flip–flop change on the positive
transition of the clock. A change in the information
present at the data (D) input will not affect the output
information at any other time due to master slave
construction.
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