SEMICONDUCTOR TECHNICAL DATA
The MC10161 is designed to decode a three bit input word to a one of eight
line output. The selected output will be low while all other outputs will be high. The
enable inputs, when either or both are high, force all outputs high.
The MC10161 is a true parallel decoder. No series gating is used internally,
eliminating unequal delay times found in other decoders. This design provides
the identical 4 ns delay from any address or enable input to any output.
A complete mux/demux operation on 16 bits for data distribution is illustrated
in Figure 1. This system, using the MC10136 control counters, has the
capability of incrementing, decrementing or holding data channels. When both
S0 and S1 are low, the index counters reset, thus initializing both the mux and
demux units. The four binary outputs of the counter are buffered by the
MC10101s to send twisted–pair select data to the multiplexer/demultiplexer to
units.
PD= 315 mW typ/pkg (No Load)
tpd= 4.0 ns typ
tr, tf= 2.0 ns typ (20%–80%)
LOGIC DIAGRAM
E0 2
E1
A7
B9
C14
15
6Q0
5Q1
4Q2
3Q3
13 Q4
12 Q5
11 Q6
10 Q7
V
= PIN 1
CC1
V
= PIN 16
CC2
VEE= PIN 8
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
CASE 775–02
DIP
PIN ASSIGNMENT
1
V
CC1
E0
Q3
Q2
Q1
Q0
V
EE
A
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
PLCC
V
E1
C
Q4
Q5
Q6
Q7
B
CC2
ENABLE
INPUTS
E1 E0 C B A Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
L L L L L L H H H H H H H
L L L L H H L H H H H H H
L L L H L H H L H H H H H
L L L H H H H H L H H H H
L L H L L H H H H L H H H
L L H L H H H H H H L H H
L L H H L H H H H H H L H
L L H H H H H H H H H H L
H X X X X H H H H H H H H
X H X X X H H H H H H H H
3/93
Motorola, Inc. 1996
TRUTH TABLE
INPUTS OUTPUTS
3–73
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
T ables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
REV 5
MC10161
Under
Und
(VCC)
ELECTRICAL CHARACTERISTICS
Test Limits
Pin
Characteristic Symbol
Power Supply Drain Current I
Input Current I
Output Voltage Logic 1 V
Output Voltage Logic 0 V
Threshold Voltage Logic 1 V
Threshold Voltage Logic 0 V
Switching Times (50Ω Load) ns
Propagation Delay t
Rise Time (20 to 80%) t
Fall Time (20 to 80%) t
E
inH
I
inL
OH
OL
OHA
OLA
14+13–
t
14–13+
13+
13–
Under
Test
8 84 61 76 84 mAdc
14 350 220 220 µAdc
14 0.5 0.5 0.3 µAdc
13
13
13 –1.890 –1.675 –1.850 –1.650 –1.825 –1.615 Vdc
13
13
13 –1.655 –1.630 –1.595 Vdc
13
13
13 1.0 3.3 1.1 2.0 3.3 1.1 3.5
13 1.0 3.3 1.1 2.0 3.3 1.1 3.5
–30°C +25°C +85°C
Min Max Min Typ Max Min Max
–1.060
–1.060
–1.080
–1.080
1.5
1.5
–0.890
–0.890
6.2
6.2
–0.960
–0.960
–0.980
–0.980
1.5
1.5
4.0
4.0
–0.810
–0.810
6.0
6.0
–0.890
–0.890
–0.910
–0.910
1.5
1.5
–0.700
–0.700
6.4
6.4
Unit
Vdc
Vdc
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@ Test Temperature V
–30°C –0.890 –1.890 –1.205 –1.500 –5.2
+25°C –0.810 –1.850 –1.105 –1.475 –5.2
+85°C –0.700 –1.825 –1.035 –1.440 –5.2
Pin
Characteristic Symbol
Power Supply Drain Current I
Input Current I
Output Voltage Logic 1 V
Output Voltage Logic 0 V
Threshold Voltage Logic 1 V
Threshold Voltage Logic 0 V
Switching Times (50Ω Load) Pulse In Pulse Out –3.2 V +2.0 V
Propagation Delay t
Rise Time (20 to 80%) t
Fall Time (20 to 80%) t
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
E
inH
I
inL
OH
OL
OHA
OLA
14+13–
t
14–13+
13+
13–
er
Test
8 2,7,9,14,15 8 1,16
14 14 8 1,16
14 14 8 1,16
13
13
13 14 8 1,16
13
13
13 14 8 1,16
13
13
13 14 13 8 1,16
13 14 13 8 1,16
IHmax
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
V
IHmax
2
15
V
ILmin
V
ILmin
V
IHAminVILAmax
V
IHAminVILAmax
2
15
14
14
13
13
V
EE
V
EE
8
8
8
8
8
8
Gnd
1,16
1,16
1,16
1,16
1,16
1,16
MOTOROLA MECL Data
3–74
DL122 — Rev 6
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