MOTOROLA MC10159FNR2 Datasheet
LOGIC DIAGRAM
VCC= PIN 16
VEE= PIN 8
SELECT
9
D01 5
D00 6
D11 3
D10 4
D21 12
D20 13
D31 10
D30 11
1 Q0
2 Q1
15 Q2
14 Q3
ENABLE
7
SEMICONDUCTOR TECHNICAL DATA
3–65
REV 5
Motorola, Inc. 1996
3/93
The MC10159 is a quad two channel multiplexer with enable. It incorporates
common enable and common data select inputs. The select input determines
which data inputs are enabled. A high (H) level enables data inputs D00, D10,
D20, and D30. A low (L) level enables data inputs D01, D11, D21, and D31. Any
change on the data inputs will be reflected at the outputs while the enable is low.
Input levels are inverted at the output.
PD= 218 mW typ/pkg (No Load)
tpd= 2.5 ns typ (Data to Q)
3.2 ns typ (Select to Q)
tr, tf= 2.5 ns typ (20%–80%)
TRUTH TABLE
Enable Select D0 D1 Q
L L X L H
L L X H L
L H L X H
L H H X L
H X X X L
DIP
PIN ASSIGNMENT
Q0
Q1
D11
D10
D01
D00
ENABLE
V
EE
V
CC
Q2
Q3
D20
D21
D30
D31
SELECT
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
T ables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
MC10159
MOTOROLA MECL Data
DL122 — Rev 6
3–66
ELECTRICAL CHARACTERISTICS
Test Limits
Pin
Under
–30°C +25°C +85°C
Characteristic Symbol
Under
Test
Min Max Min Typ Max Min Max
Unit
Power Supply Drain Current I
E
8 58 42 53 58 mAdc
Input Current I
inH
9
5
360
400
225
250
225
250
µAdc
I
inL
5 0.5 0.5 0.3 µAdc
Output Voltage Logic 1 V
OH
1 –1.060 –0.890 –0.960 –0.810 –0.890 –0.700 Vdc
Output Voltage Logic 0 V
OL
1 –1.890 –1.675 –1.850 –1.650 –1.825 –1.615 Vdc
Threshold Voltage Logic 1 V
OHA
1 –1.080 –0.980 –0.910 Vdc
Threshold Voltage Logic 0 V
OLA
1 –1.655 –1.630 –1.595 Vdc
Switching Times (50Ω Load) ns
Propagation Data Input
Delay Select Input
Enable Input
t
5+1–
t
9+1–
t
7+1–
1
1
1
1.1
1.5
1.4
3.8
5.3
5.3
1.2
1.5
1.5
2.5
3.2
2.5
3.3
5.0
5.0
1.1
1.5
1.4
3.8
5.3
5.3
Rise Time (20 to 80%) t
1+
1 1.0 3.7 1.1 2.5 3.5 1.0 3.7
Fall Time (20 to 80%) t
1–
1 1.0 3.7 1.1 2.5 3.5 1.0 3.7
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@ Test Temperature V
IHmax
V
ILmin
V
IHAminVILAmax
V
EE
–30°C –0.890 –1.890 –1.205 –1.500 –5.2
+25°C –0.810 –1.850 –1.105 –1.475 –5.2
+85°C –0.700 –1.825 –1.035 –1.440 –5.2
Pin
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
Characteristic Symbol
Und
er
Test
V
IHmax
V
ILmin
V
IHAminVILAmax
V
EE
(VCC)
Gnd
Power Supply Drain Current I
E
8 8 16
Input Current I
inH
9
5
9
5
8
8
16
16
I
inL
5 5 8 16
Output Voltage Logic 1 V
OH
1 8 16
Output Voltage Logic 0 V
OL
1 5 8 16
Threshold Voltage Logic 1 V
OHA
1 9 6 8 16
Threshold Voltage Logic 0 V
OLA
1 9 6 8 16
Switching Times (50Ω Load) +1.11V +0.31V Pulse In Pulse Out –3.2 V +2.0 V
Propagation Delay Data Input
Select Input
Enable Input
t
5+1–
t
9+1–
t
7+1–
1
1
1
6
3, 12
5
9
7
1
1
1
8
8
16
16
Rise Time (20 to 80%) t
1+
1 9 5 1 8 16
Fall Time (20 to 80%) t
1–
1 9 5 1 8 16
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
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