SEMICONDUCTOR TECHNICAL DATA
3–44
REV 6
Motorola, Inc. 1996
9/96
The MC10111 is designed to drive up to three transmission lines simul–
taneously. The multiple outputs of this device also allow the wire “OR”–ing of
several levels of gating for minimization of gate and package count.
The ability to control three parallel lines from a single point makes the
MC10111 particularly useful in clock distribution applications where minimum
clock skew is desired. Three VCC pins are provided and each one should be
used.
PD= 80 mW typ/gate (No Load)
tpd= 2.4 ns typ (All Outputs Loaded)
tr, tf= 2.2 ns typ (20%–80%)
LOGIC DIAGRAM
V
CC1
= PIN 1,15
V
CC2
= PIN 16
VEE= PIN 8
12
11
10
9
13
14
2
7
6
5
3
4
DIP
PIN ASSIGNMENT
V
CC1
A
OUT
A
OUT
A
OUT
A
IN
A
IN
A
IN
V
EE
V
CC2
V
CC1
B
OUT
B
OUT
B
OUT
B
IN
B
IN
B
IN
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
T ables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
MC10111
3–45 MOTOROLAMECL Data
DL122 — Rev 6
ELECTRICAL CHARACTERISTICS
Test Limits
Pin
Under
–30°C +25°C +85°C
Characteristic Symbol
Test
Min Max Min Typ Max Min Max
Unit
Power Supply Drain Current I
E
8 42 30 38 42 mAdc
Input Current I
inH
5, 6, 7 680 425 425 µAdc
I
inL
5, 6, 7 0.5 0.5 0.3 µAdc
Output Voltage Logic 1 V
OH
2
3
4
–1.060
–1.060
–1.060
–0.890
–0.890
–0.890
–0.960
–0.960
–0.960
–0.810
–0.810
–0.810
–0.890
–0.890
–0.890
–0.700
–0.700
–0.700
Vdc
Output Voltage Logic 0 V
OL
2
3
4
–1.890
–1.890
–1.890
–1.675
–1.675
–1.675
–1.850
–1.850
–1.850
–1.650
–1.650
–1.650
–1.825
–1.825
–1.825
–1.615
–1.615
–1.615
Vdc
Threshold Voltage Logic 1 V
OHA
2
3
4
–1.080
–1.080
–1.080
–0.980
–0.980
–0.980
–0.910
–0.910
–0.910
Vdc
Threshold Voltage Logic 0 V
OLA
2
3
4
–1.655
–1.655
–1.655
–1.630
–1.630
–1.630
–1.595
–1.595
–1.595
Vdc
Switching Times (50Ω Load) ns
Propagation Delay t
5+2–
t
5–2+
t
5+3–
t
5–3+
t
5+4–
t
5–4+
2
2
3
3
4
4
1.4
1.4
1.4
1.4
1.4
1.4
3.5
3.5
3.5
3.5
3.5
3.5
1.4
1.4
1.4
1.4
1.4
1.4
2.4
2.4
2.4
2.4
2.4
2.4
3.5
3.5
3.5
3.5
3.5
3.5
1.5
1.5
1.5
1.5
1.5
1.5
3.8
3.8
3.8
3.8
3.8
3.8
Rise Time (20 to 80%) t
2+
t
3+
t
4+
2
3
4
1.0
1.0
1.0
3.5
3.5
3.5
1.1
1.1
1.1
2.2
2.2
2.2
3.5
3.5
3.5
1.2
1.2
1.2
3.8
3.8
3.8
Fall Time (20 to 80%) t
2–
t
3–
t
4–
2
3
4
1.0
1.0
1.0
3.5
3.5
3.5
1.1
1.1
1.1
2.2
2.2
2.2
3.5
3.5
3.5
1.2
1.2
1.2
3.8
3.8
3.8