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SEMICONDUCTOR TECHNICAL DATA
The MC10/100H605 is a 6–bit, registered, dual supply ECL to TTL
translator. The device features differential ECL inputs for both data and
clock. The TTL outputs feature balanced 24mA sink/source capabilities for
driving transmission lines.
With its differential ECL inputs and TTL outputs the H605 device is ideally
suited for the receive function of a HPPI bus type board–to–board interface
application. The on chip registers simplify the task of synchronizing the data
between the two boards.
A VBB reference voltage is supplied for use with single–ended data or
clock. For single–ended applications the VBB output should be connected to
the “bar” inputs (Dn
To minimize the skew of the device differential clocks should be used.
The ECL level Master Reset pin is asynchronous and common to all
flip–flops. A “HIGH” on the Master Reset forces the Q outputs “LOW”.
The device is available in either ECL standard: the 10H device is
compatible with MECL 10H logic levels while the 100H device is
compatible with 100K logic levels.
• Differential ECL Data and Clock Inputs
• 24mA Sink, 24mA Source TTL Outputs
• Dual Power Supply
• Multiple Power and Ground Pins to Minimize Noise
• 2.0ns Part–to–Part Skew
or CLK) and bypassed to ground via a 0.01µF capacitor.
LOGIC SYMBOL
FN SUFFIX
PLASTIC PACKAGE
CASE 776–02
PIN NAMES
PIN FUNCTION
D0–D5
D0–D5
CLK, CLK
MR
Q0–Q5
V
CCE
V
CCT
GND
V
EE
True ECL Data Inputs
Inverted ECL Data Inputs
Differential ECL Clock Input
ECL Master Reset Input
TTL Outputs
ECL V
CC
TTL V
CC
TTL Ground
ECL V
EE
CLK
CLK
MR
V
BB
1 OF 6 BITS
D
n
D
n
D
Q
Q
n
CLK
R
TRUTH TABLE
Dn
Z = LOW to HIGH Transition
MR
L
H
X
L
L
H
TCLK/CLK
Z
Z
X
Pinout: 28–Lead PLCC (Top View)
V
CCT
Q2
Q1
Q0
GND
CLK
CLK
V
BB
Q3 V
26
27
28
2
3
4
D0 D0
Q4 GND Q5 MR
CCT
25 24 23 22 21 20 19
567891011
VEED1 D1 D2 D2
Qn+1
L
H
L
18
17
16
15
14
13
12
D5
D5
D4
D4
V
D3
D3
CCE
MECL 10H is a trademark of Motorola, Inc.
9/96
Motorola, Inc. 1996
2–306
REV 3
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MC10H605 MC100H605
10H ECL DC CHARACTERISTICS (V
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit Condition
I
EE
I
IH
I
IL
V
IH
V
IL
V
BB
V
Diff
V
max
CMRR
V
min
CMRR
Supply Current 63 75 63 75 61 75 mA
Input HIgh Current 225 145 145 µA
Input Low Current 0.5 0.5 0.5 µA
Input High Voltage –1170 –840 –1130 –810 –1060 –720 mV
Input Low Voltage –1950 –1480 –1950 –1480 –1950 –1480 mV
Output Bias Voltage –1400 –1280 –1370 –1270 –1330 –1210 mV
Input Differential Voltage 150 150 150 mV
Input Common Mode
Reject Range
Input Common Mode
Reject Range
100H ECL DC CHARACTERISTICS (V
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit Condition
I
EE
I
IH
I
IL
V
IH
V
IL
V
BB
V
Diff
V
max
CMRR
V
min
CMRR
Supply Current 65 75 65 75 70 85 mA
Input HIgh Current 225 145 145 µA
Input Low Current 0.5 0.5 0.5 µA
Input High Voltage –1165 –880 –1165 –880 –1165 –880 mV
Input Low Voltage –1810 –1475 –1810 –1475 –1810 –1475 mV
Output Bias Voltage –1400 –1280 –1400 –1280 –1400 –1200 mV
Input Differential Voltage 150 150 150 mV
Input Common Mode
Reject Range
Input Common Mode
Reject Range
= +5.0V ±5%; VEE = –5.20V ±5%)
CCT
0°C 25°C 85°C
0 0 0 mV
–2800
–3000
–3300
–2000
–2200
–2400
= +5.0V ±5%; VEE = –4.5V ±0.3V)
CCT
0°C 25°C 85°C
–2800
–3000
–3300
0 0 0 mV
–2000
–2200
–2400
–2800
–3000
–3300
–2000
–2200
–2400
mV VEE = –4.94
VEE = –5.20
VEE = –5.46
mV VEE = –4.20
VEE = –4.50
VEE = –4.80
* NOTE: DO NOT short the ECL inputs to the TTL VCC.
DL122 — Rev 6
2–307 MOTOROLAMECL Data