Motorola M68EZ328ADS User Manual

Motorola, Inc.

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M68EZ328ADS v2.0

Application Development System

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User’s Manual

Revision 1.0

JAN 19, 2000

Preliminary

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Motorola reserves the right to make changes without further notice to any product herein to improve reliability, function, or design. Motorola does not assume any liability arising out of the application or use of any product, circuit, or software described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such intended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiari es, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and the are registered trademarks of Motorola Ltd.

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TABLE OF CONTENTS

Section 1 General Information

1.1 Introduction...................................................................................................1-6

1.2 Features........................................................................................................1-6

1.3 Related Documentation ................................................................................1-7

1.4 Technical Support.........................................................................................1-7

1.4.1 M68EZ328ADS v2.0...................................................................................1-7

1.4.2 Debugger....................................................................................................1-7

Section 2 Quick Installation Guide

2.1 Overview.......................................................................................................2-8

2.2 Equipments Required ...................................................................................2-8

2.3 Installation Procedure ...................................................................................2-8

2.3.1 Prepare the M68EZ328ADS v2.0 board.....................................................2-8

2.3.2 Connecting M68EZ328ADS v2.0 to PC....................................................2-11

2.3.3 Installing software debugger.....................................................................2-11

Section 3 Hardware Description and Board Operation

3.1 Overview.....................................................................................................3-16

3.2 Control Switches.........................................................................................3-17

3.3 DIP Switches...............................................................................................3-17

3.4 Operation Modes ........................................................................................3-18

3.5 LED Indicators ............................................................................................3-18

3.6 Memory.......................................................................................................3-19

3.6.1 Memory Map.............................................................................................3-19

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3.6.2 FLASH Memory ........................................................................................3-19

3.6.3 EMU ROM ...............................................................................................3-20

3.6.4 EDO DRAM ..............................................................................................3-21

3.7 UART and IRDA..........................................................................................3 -22

3.8 Debug Port..................................................................................................3-23

3.9 LCD and Touch Panel Interface..................................................................3-23

3.9.1 LCD Interface............................................................................................3-23

3.9.2 Touch Panel Interface...............................................................................3-24

3.10 Single Tone Generator................................................................................3-25

3.11 Logic Analyzer Interface .............................................................................3-25

3.12 ExPANSION Connectors ............................................................................3-25

3.13 Power Supply..............................................................................................3-26

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Comparison of M68EZ328ADS Version 1.x and 2.0

A.1 Hardware ....................................................................................................A-28

A.2 Software......................................................................................................A-28

B.1 General Concepts of Resistive Panels .......................................................B-30

Programming On-board Flash Memory

C.1 Overview.................................................................................................... C-32

C.2 Elements for programming the flash..........................................................C-32

C.3 Method....................................................................................................... C-33

C.4 Offset Address of ROM Image...................................................................C-33

C.5 Executing ProgRam Command Sequence................................................ C-34

Table of Contents

Appendix A

Appendix B

Resistive Touch Panel Operation

Appendix C

Appendix D

Monitor Initialization Code

D.1 Initialization Code of Metrowerks Monitor (Reset.S)..................................D-40

D.2 Initialization Code of SDS Monitor (Monitor.H)..........................................D-44

Appendix E Schematics

E.1 M68EZ328ADS v2.0 ...................................................................................E-54

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Table of Contents

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iii M68EZ328ADS v2.0 USER’S MANUAL MOTOROLA

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LIST OF ILLUSTRATIONS

2-1 M68EZ328ADS v2.0 Key Component Layout....................................................2-9

2-2 Default DIP Switch Options for Metrowerks monitor ........................................2-10

2-3 DIP Switch Options for SDS monitor................................................................2-10

2-4 Connecting PC to Debug Port of M68EZ328ADS v2.0....................................2-11

2-5 Debug Pop-Up Window of SDS v7.4................................................................2-14

2-6 Connection Setting inside Debug Pop-up Window of SDS v7.4 ......................2-15

3-1 M68EZ328ADS v2.0 Functional Block Diagram...............................................3-16

3-2 Interface of Flash Memories.............................................................................3-19

3-3 Interface of EMU ROM.....................................................................................3-20

3-4 Interface of EDO DRAMs .................................................................................3-21

3-5 UART and IRDA Interface................................................................................3-22

3-6 Serial Port Pin Assignment...............................................................................3-22

3-7 Debug Port Interface........................................................................................3-23

3-8 LCD and Touch Panel Connector Pin Assignment ..........................................3-23

3-9 Touch Panel Controller Interface......................................................................3 -24

3-10 Single Tone Generator.....................................................................................3-25

3-11 Logic Analyzer Connectors ..............................................................................3-25

3-12 Power Connectors............................................................................................3-27

2-1 Resistive Touch Panel......................................................................................B-30

2-2 Determination of X,Y Position ..........................................................................B-31

C-1 Method of programming on-board Flash memory...........................................C-33

C-2 Flash Program Algorithm.................................................................................C-38

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LIST OF TABLES

3-1 DIP Switch pack S1 Setting..............................................................................3-17

3-2 DIP Switch pack S2 Setting..............................................................................3-17

3-3 Operation Mode Setting ...................................................................................3-18

3-4 Function of LED Indicators...............................................................................3-18

3-5 M68VZ328ADS v2.0 Default Memory Map ......................................................3-19

3-6 Signal Assignment for Touch Panel Controller.................................................3-24

3-7 Pin Assignments of P4.....................................................................................3-26

A-1 Comparison of M68EZ328ADS v1.x and v2.0..................................................A-28

A-2 Software Change for using M68EZ328ADS v2.0.............................................A-28

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SECTION 1 GENERAL INFORMATION

1.1 INTRODUCTION

The DragonBallTM-EZ (MC68EZ328) Application Development System (M68EZ328ADS) is designed to supply users with an environment to develop MC68EZ328 based application software. Moreover, this board can be used as a reference for real-life product design. M68EZ328ADS provides several interface ports for application software and target board debug purpose.

DragonBallTM-EZ ADS altogether has two versions released for customers. This is the second version.Theboard design and layout insecondversion has beenchangeda great deal. It includes simplifying the design for enhancing production quality and the easiness to use. However, most of the interfaces to external peripherals remain unchanged in order to provide high degree of compatibility with previous version. For more details on the changes, Please refer to Appendix A .

This document will discuss the usage and system details of the M68EZ328ADS v2.0.

1.2 FEATURES

• MC68EZ328 CPU

• Memory Subsystem —2 MB FLASH (Expandable to 4MB)

—8 MB EDO DRAM

• Debug ports —One RS232 serial port interface to MC68EZ328 internal UART

—One External RS232 serial port connecting to on-board UART chip —Direct logic analyzer interface to system bus

• LCD and Touch Panel Interface —MC68EZ328 LCD interface

—Burr-Brown 12-bit touch panel controller ADS7843E available for pen input

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•LEDIndicators —Red LED for power

—Green LED for system heart beat —Yellow LED for status of MC68EZ328 pin PD0 —Yellow LED for status of MC68EZ328 pin PD1

• Board operation mode support —MC68EZ328 EMU mode

—MC68EZ328 normal mode —MC68EZ328 bootstrap mode

• Debug Monitor —MetroWerks Codewarrior Target Monitor using serial port

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General Information

—SDS source-leveldebuggermonitor by Software DevelopmentSystemInc.usingse-

rial port

• Clock Source —32.768KHz for MC68EZ328 internal PLL

• Power Supply —3.0V - 3.3V main power supply

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1.3 RELATED DOCUMENTATION

The following documents can be used as references when using M68EZ328ADS.

• MC68EZ328 User’s Manual

• MC68EZ328 Product Information

1.4 TECHNICAL SUPPORT

1.4.1 M68EZ328ADS v2.0

For getting the latest information, please visit our web page:

http://www.mot.com/SPS/WIRELESS/products/DragonBall.html

http://www.apspg.com/products/dragonballez/mc68ez328.html

1.4.2 Debugger

There are three source-level debuggers for DragonBallTM-EZ. The contact information is listed below.

1. Metrowerks

http://www.metrowerks.com

2. Single Step Development

http://www.sdsi.com

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3. Microtek SLD

http://www.microtekintl.com

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SECTION 2 QUICK INSTALLATION GUIDE

2.1 OVERVIEW

This section provides a description of the evaluation module, requirements, quick installation and test information. Detailed information on the M68EZ328ADS v2.0 design and operation is provided in the remaining sections of this manual.

2.2 EQUIPMENTS REQUIRED

The following equipments are required to use with the M68EZ328ADS Application Development System, some of them are already bundled with the ADS package.

• Power supply − 3.0V-3.3V, 1500mA, with 2 mm female (inside positive) power connector

• RS-232cable(DB9maletoDB9female)

• IBM PC compatible computer (486 class or higher) running Windows3.1and DOS 6.0 (or higher), or Windows 95, with an RS-232 serial port capable of 9600-115200 bit per second operation

2.3 INSTALLATION PROCEDURE

Please follow the procedure below to set up M68EZ328ADS.

1. Prepare the M68EZ328ADS v2.0 board

2. Connect the M68EZ328ADS v2.0 board to PC and power supply

3. Install software debugger

2.3.1 Prepare the M68EZ328ADS v2.0 board

Locate the DIP switches on the M68EZ328ADS v2.0 board and select appropriate monitor and debug port for your debugger.

Figure2-2shows the factorydefaultDIP switchessettings.This settingselectstouse Metroworks monitor. Figure 2-3 shows the DIP switches setting of using SDS monitor.

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For detail description of each switch. Pls. refer to Table 3-1 and Table 3-2. For additional informationon the M68EZ328ADS v2.0 and its components. Pls refer to Sec-

tion 3 .

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Quick Installation Guide

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Figure 2-1. M68EZ328ADS v2.0 Key Component Layout

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Quick Installation Guide

Monitor and Debug port selection

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S2

ON

12345678

Figure 2-2. Default DIP Switch Options for Metrowerks monitor

S1

ON

12345678

Figure 2-3. DIP Switch Options for SDS monitor

S1

ON

12345678

S2

ON

12345678

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Quick Installation Guide

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2.3.2 Connecting M68EZ328ADS v2.0 to PC

Figure 2-4 shows connections among the PC, the external power supply and the M68E Z328ADS v2.0 board. Use the following steps to complete cable connections:

Host Computer

COM1

/COM2

RS232 Cable

Debug Port

EZ UART

3.0-3.3V

Power Supply

M68VZ328ADS

Figure 2-4. Connecting PC to Debug Port of M68EZ328ADS v2.0

For m ost evaluation platforms, serial communication is the primary channel to link up PC with the target board. Both Metrowerks Codewarrior and Software Development System (SDS) debug monitor support serial communication through UART port. The procedure are as follows.

1. Connect a RS232 cable from COM port (COM1 or COM2) to connector P2 of M68EZ328ADS v2.0.

2. Connect the power supply +3V or power adaptor to the P1 of M68EZ328ADS v2.0

3. Turn on the power supply. The RED LED will flash and the GREEN LED will illuminate when power is correctly applied.

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2.3.3 Installing software debugger

The following software debugger supports M68EZ328ADS v2.0:

• Metrowerks Codewarrior

• Single Step Development System

•SLD

Metrowerks Codewarrior

A simple procedure for using Metrowerks Codewarrior Target Monitor:

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Quick Installation Guide

1. Install the Metrowerks Codewarrior IDE

2. Run Codewarrior IDE program.

3. Open a new project file with Embedded 68k Stationery.

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4. Select ADS_68EZ328 Stationery for new project.

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Quick Installation Guide

5. Choose "Enable Debugger" from the "Project" pull-down menu.

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6. Change the connection settings in the Debug Settings Windows.

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Quick Installation Guide

7. Edit the code inside the Codewarrior IDE program.

8. Press F5 to run the program.

Single Step Development System

A simple procedure for using Single Step Debugger:

1. Install the Single Step Debugger on your PC.

2. Run Single Step Debugger

3. Choose Debug in the File pull-downmenutoopentheDebug pop-up window.

4. InsidetheDebug pop-upwindow,choosethe objectfile todownloador"debugwithout file" asshowninFigure2-5,select the serial port (COM1 orCOM2...)accordingto the serial port of the PC connecting to the ADS, disable "hardware flow control" and the baud rate should be 115200bps as shown in Figure 2-6.

5. The file should be downloadedandthenyoucanstartyourdevelopment. (For details, please refer to the SingleStep User’s Manual).

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Figure 2-5. Debug Pop-Up Window of SDS v7.4

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Figure 2-6. Connection Setting inside Debug Pop-up Window of SDS v7.4

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SECTION 3 HARDWARE DESCRIPTION AND BOARD OPERATION

3.1 OVERVIEW

Figure 3-1 shows the block diagram of M68EZ328ADS v2.0.

Logic Analyzer

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Extension

Connectors

Single

Tone

Generator

PWMO

Touch Panel

Controller

Extension

MC68EZ328

Connector

FLASH

1M x 16-bit

EDO DRAM

4M x 16-bit

Control Bus

UART SIGNALS RESET

FLASH

1M x 16-bit

Reset

Circuit

Address Bus

Data Bus

UART

CHIP

UART

and IRDA

Interface

Debug

Port

IRDA

UART

Power Connector

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4-bit LCD

LCD Connectors

Figure 3-1. M68EZ328ADS v2.0 Functional Block Diagram

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RESET

GND

ABORT

GND

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Hardware Description and Board Operation

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3.2 CONTROL SWITCHES

There are two push buttons on the ADS which function as follows:

1. Reset Switch (SW2): When pressed, a hardware reset is generated to the MC68EZ328 processor and resumes operation.

2. Abort Switch (SW1): This switch is used to generate a level 7 interrupt to the MC68EZ328 processor for aborting normal software execution and returning control to the debug monitor.

3.3 DIP SWITCHES

There are two DIP switch packs on the ADS board, S1 and S2. S1 is used to configure the memory system and operation modes. S2 is used to enable the on-board peripheral such as buzzer and touch panel controller. Table 3-1 and Table 3-2 show the description of each switch.

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Switch FUNCTION ON OFF

S1-1 UART Transceiver Enable Disable S1-2 IrDA Module Enable Disable S1-3 Buzzer Enable Disable S1-4 Pen IRQ Enable Disable S1-5 Chip Select of Touch Panel Controller Enable Disable S1-6 Unused S1-7 Unused S1-8 Unused

Table 3-1. DIP Switch pack S1 Setting

Table 3-2. DIP Switch pack S2 Setting

Switch FUNCTION ON OFF

S2-1 CSA0 - FLASH0 Connected Disconnected S2-2 CSA1 - FLASH1 Connected Disconnected S2-3 CSD0 - EDO DRAM Connected Disconnected S2-4 EMU Mode Enable Disable S2-5 Bootstrap Mode Enable Disable S2-6 Monitor Select SDS Metrowerks S2-7 Unused

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S2-8 Unused

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Hardware Description and Board Operation

3.4 OPERATION MODES

M68EZ328ADS v2.0 supports three operation modes of MC68EZ328: EMU Mode, Normal Mode and Bootstrap Mode. Selection of these operation modes is controlled by DIP switch S2-8. Operation mode has to be selected before resetting the system. Mode is not allowed to change during normal running. Table 3-3 shows the operation mode configuration.

Table 3-3. Operation Mode Setting

DIP Switch S2-4 DIP Switch S2-5 Operation Mode

ON OFF EMU

OFF OFF Normal

ON ON Bootstrap

OFF ON Bootstrap

Normal Mode - After power up or system reset in this mode, CSA0 is default to cover the

whole memory map except MC68EZ328 internal registers and EMU space. Also, as reset vector fetch is at the beginning of CSA0 space, CSA0 should be connected to the boot ROM in which the first two words are reset vectors.

Bootstrap Mode - When this mode is selected, the DragonBall-EZ will start its embedded bootloader. User can use this mode to do simple debugging or reprogram the flash memories. For detailed bootstrap mode operation, please refer MC68EZ328 user’s manual.

EMU Mode - When this mode is selected, the reset vectors are generated internally by the ICE module of MC68EZ328. The first instruction fetch is at $FFFC0020. Therefore, in EMU mode the debug monitor of MC68EZ328ADS v2.0 is located beginning at $FFFC0020. EMUCS is always running in 8-bit data bus mode covering the address space from $FFFC0000 to $FFFD0000

3.5 LED INDICATORS

There are four LED indicators on the ADS which function as shown in Table 3-4.

Table 3-4. Function of LED Indicators

Reference # Color Name Function

LED3 Yellow PD0 Status of PD0 LED4 Yellow PD1 Status of PD1

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The LED3 is connected to a counter. The counter is toggled by address line A1.

LED1 Red Heart Beat Blinking heart beat indicates the system is "alive" LED2 Green Power Power is applied to the system with right polarity

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3.6 MEMORY

M68EZ328ADS v2.0 provides on-board Flash memory and EDO DRAM, for application development.They canbeenabled ordisabled individuallyby setting thecorresponding DIP switches.

3.6.1 Memory Map

The default memory map of M68EZ328ADS v2.0 in normal mode is shown in Table 3-5. The chip select range to all of the memory are software programmable. Users can reconfigure the memory map for their applications.

Table 3-5. M68VZ328ADS v2.0 Default Memory Map

System Address Memory Assigned Chip Select $00000000-$007FFFFF 8MB EDO DRAM CSD0 $00800000-$009FFFFF 2MB FLASH BANK0 CSA0

$00A00000-$00BFFFFF 2MB FLASH BANK1 CSA1

$00C00000-$00FBFFFF Unused $FFFC0000-$FFFCFFFF EMU Monitor EMUCS $FFFD0000-$FFFDFFFF Debug Port EMUCS

$FFFFF000-$FFFFFFFF MC68EZ328 Internal Register -

3.6.2 FLASH Memory

MC68EZ328

CSA1

CSA0

A[1..20]

D[0..15]

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OE

WE

Figure 3-2. Interface of Flash Memories

S2-2

S2-1

VCC VCC

CE A[0..19]

D[0..15]

OE

WE

1MX16-Bit FLASH

CE

1MX16-Bit FLASH

FLASH1

FLASH0

M68EZ328ADS v2.0 supports up to two 2M-byte Flash memory chips. However, only one bank is installedwhentheboardisshippedout from the factory.Figure3-2.showstheinterface of them.Theyarechip-selected by *CSA0 and *CSA1signals.Theconnection of these *CSAx signals to the Flash memories is controlled by DIP switches S2-1 and S2-2.

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Hardware Description and Board Operation

When S2-1 is ON, *CSA0 is connected to FLASH0. When S2-2 is ON, *CSA1 is connected to FLASH1. In Normal Mode, FLASH0 is the boot ROM. User can reprogram Flashes with theirownapplication program.Formore detailsonflashmemory programming,please refer to Appendix C .

3.6.3 EMU ROM

8x8-Bit EMU ROM

EMUCS

A16

MC68EZ328

OR

Gate

CS

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OE

WE

A[0..15]

D[8..15]

OE

WE

A[0..15]

D[8..15]

Figure 3-3. Interface of EMU ROM

The M68EZ328ADS v2.0 is equipped with one 64K-byte EMU ROM. Figure 3-3 shows the interface of the EMU ROM. This EMU ROM has already been programmed with the SDS monitor and the Metrowerks monitor when the board is shipped out from the factory.

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Hardware Description and Board Operation

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3.6.4 EDO DRAM

VCC

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4MX16-Bit EDO DRAM

RAS UCAS

LCAS

OE

WE

A[0..12]

D[0..15]

MC68EZ328

S2-3

CSC0 CSD0 CSD1

OE

DWE

A[1..13]

D[0..15]

Figure 3-4. Interface of EDO DRAMs

Figure 3-4. shows the interface of EDO DRAMs. M68EZ328ADS v2.0 supports one bank of 4Mx16-bit EDO DRAMs. The EDO DRAM is enabled by turning DIP switch S2-3 on.

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3.7 UART AND IRDA

MC68VZ328

Hardware Description and Board Operation

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VCC

S1-1

GND

TXD RXD RTS

CTS

PD4

S1-2

VCC

RS232 Transceiver

EN

Buffer

EN

P9

UART

IRDA

EN

Figure 3-5. UART and IRDA Interface.

Figure 3-5 shows the UART and IRDA module. The M68EZ328ADS v2.0 has one RS232 serial ports P9. P9 is using the UART of MC68EZ328. It is 9-pin female D-Type connectors containing the signals as shown in Figure 3-6. The transceivers for UART can be enabled by turning the DIP switch S1-1 on.

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TXD

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RXD

NC

GND

Figure 3-6. Serial Port Pin Assignment

The IrDA transceiver is provided and connected to DragonBall’s UART Port only with a buffer in between for controlling its ON/OFF. If IrDA is being used, S1-1 should be switched OFF andS1-2shouldbe switched ON. Then, the enable/disable of IRDAistotallycontrolled by software through PD4 (Port D4).

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1 2

3 4 5

NC

6

CTS

7

RTS

8

NC

9

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3.8 DEBUG PORT

EMUCS

A16

MC68EZ328

OE WE

A[0..2]

OR

Gate

ST16C2552A

CS

OE WE A[0..2]

TXD

RXD CTS RTS

RS232 Transceiver

EN

P8

UART

D[8..15]

nc...

Figure 3-7. Debug Port Interface

As shown in Figure 3-7, an external UART chip ST16C2552A is used to provide one more debug port on the ADS board. This UART chip is connected with the DB9 connector P8. Its pin assignment is shown in Figure 3-6. The baud rate of this UART chip is defaulted to 115200bps.

3.9 LCD AND TOUCH PANEL INTERFACE

3.9.1 LCD Interface

M68EZ328ADS consists of one LCD panel connector, P10. P10 is designed for 4-bit LCD panel. The pin assignments of the LCD connector is shown in Figure 3-8.

LACD

LLP

VO

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GND

LD0 LD2

GND

PB1

TOP

LEFT

P10

1 3 5 7 9 11 13 15 17 19

D[8..15]

2

LFRM

4

LCLK

6

VCC

8

VEE

10

LD1

12

LD3

14

LCONTRAST

16

NC

18

BOTTOM

20

RIGHT

Figure 3-8. LCD and Touch Panel Connector Pin Assignment

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Hardware Description and Board Operation

For full description of the LCD signals, please refer to the MC68EZ328 User’s Manual.

3.9.2 Touch Panel Interface

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RIGHT

TOP

LEFT

BOTTOM

MC68EZ328

PB6

IRQ5

SPMCLK SPMTXD

SPMRXD

S1-5 S1-4

Touch Panel

VCC

ADS7843

CS PENIRQ

DCLK

DIN

DOUT

Figure 3-9. Touch Panel Controller Interface

The M68EZ328ADS board is equipped with Burr-Brown Touch Panel Controller ADS7843. Figure 3-9 shows the interface of Touch Panel Controller. Totally one I/O signal, one interrupt capable I/O signal and one set of SPIM signals from MC68EZ328 are used to implement the touch panel circuitry. All of these signals can be shared for other devices when touch panel interface controller i s being disabled. The on-board touch panel controller can be disabled by turning both DIP switches S1-4, S1-5 off.

Table 3-6. Signal Assignment for Touch Panel Controller

Signals Function

This set of serial port interface signals performs data transfer with

SPMRXD, SPMTXD, SPMCLK

~IRQ5 This signal is a MC68EZ328 interrupt capable I/O pin.

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PB6

ADS7843. For detailed operation on the SPI port, please refer to the

This MC68EZ328 general I/O signal is used to select the ADS7843 on data

The ADS7843 is a 12-bit sampling analog-to-digital converter (ADC) with a synchronous serial interface and low on-resistance switches for touch screens. The ADS7843 communicates with MC68EZ328 through SPI (Serial Peripheral Interface). In this case, ADS7843 is a slave, and MC68EZ328 is a master. For the detailed operation of ADS7843, please refer to its datasheet. The datasheet is available at the following web site.

http://www.burr-brown.com

For more details on the operation of resistive touch panel, please refer to Appendix B .

MC68EZ328 User’s Manual.

transfer.

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3.10 SINGLE TONE GENERATOR

S1-5

PWMO

MC68VZ328

Figure 3-10. Single Tone Generator

VCC

BC847

CitiSound CHB-03E

GND

nc...

Citizen single tone generator CHB-03E is provided on M68EZ328ADS v2.0. As shown in Figure 3-10, a simple transistor circuit is used to interface the CHB-03E with the PWMO pin of MC68EZ328.

3.11 LOGIC ANALYZER INTERFACE

Toprovidean convenientwayof connectingon-board signalsto alogicanalyzer, ADSboard provides five 10x2-pin headers for direct plug-in. Pin assignments to these five headers are showninFigure3-11.

POD2POD3

CLKO

D14 D12 D10

D8 D6 D4 D2 D0

1 3 5 7 9 11 13 15 17 19

10 12 14 16 18 20

2 4 6 8

D15 D13 D11 D9 D7 D5 D3 D1 GND

EMUCS

RSTIN

EMUCS

LWE

CONTRAST

LCLK

LFRM

LD2 LD0

1 3 5 7 9 11 13 15 17 19

2 4 6

8 10 12 14 16 18 20

EMUIRQ OE UWE DTACK LACD LLP LD3 LD1 GND

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Figure 3-11. Logic Analyzer Connectors

CSA0 CSA1 CSB1 RAS1 CAS1

A22 A20 A18 A16

POD1

1 3 5 7 9 11 13 15 17 19

10 12 14 16 18 20

2 4 6 8

CSA0 CSB0 RAS0 CAS0 A23 A21 A19 A17 GND

DTACK

A14 A12 A10

A8 A6 A4 A2 A0

POD4

1 3 5 7 9 11 13 15 17 19

10 12 14 16 18 20

2 4 6 8

A15 A13 A11 A9 A7 A5 A3 A1 GND

3.12 EXPANSION CONNECTORS

The M68EZ328ADS v2.0 provides basic features for software development and evaluation. If user wants to add application subsystem to M68EZ328ADS v2.0, it can utilize the signals providedon 32x3 localbus connector(P4).SomeoftheseMC68EZ328 signalsareusedby the on-board modules. If users want to use any of these signals for their daughter card, the corresponding on-board module may have to be disabled to avoid contention.

The pin assignments for extension connectors are shown in Table 3-7.

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Hardware Description and Board Operation

Table 3-7. Pin Assignments of P4

Pin# A B C

1 GND GND GND 2 D0/PA0 D1/PA1 D2/PA2 3 D3/PA3 D4/PA4 D5/PA5 4 D6/PA6 D7/PA7 D8 5 D9 D10 D11 6 D12 D13 D14 7 D15 CSA0 PF7/CSA1 8 PB0/CSB0 PB1/CSB1 PB2/CSC0/RAS0

9 PB3/CSC1/RAS1 PB4/CSD0/CAS0 PB5/CSD1/CAS1 10 PB6/TOUT/TIN PB7/PWMO1 PC0/LD0 11 PC1/LD1 PC2/LD2 PC3/LD3 12 PC4/LFRM PC5/LLP PC6/LCLK 13 PC7/LACD PD0/INT0 PD1/INT1 14 PD2/INT2 PD3/INT3 PD4/IRQ1 15 PD5/IRQ2 PD6/IRQ3 PD7/IRQ6 16 PE0/SPMTXD PE1/SPMRXD PE2/SPMCLK 17 PE3/DWE/UCLK PE4/RXD PE5/TXD 18 PE6/RTS PE7/CTS PF0/LCONTRAST 19 PF1/IRQ5 PF2/CLKO PG1/A0 20 MA0/A1 MA1/A2 MA2/A3 21 MA3/A4 MA4/A5 MA5/A6 22 MA6/A7 MA7/A8 MA8/A9 23 MA9/A10 MA10/A11 MA11/A12 24 MA12/A13 MA13/A14 MA14/A15 25 MA15/A16 A17 A18 26 A19 PF3/A20 PF4/A21 27 PF5/A22 PF6/A23 PG2/EMUIRQ 28 PG3/HIZ/P/D PG4/EMUCS PG5/EMUBRK 29 PG0/BUSW/DTACK RESET OE 30 UWE LWE PK2/LDS 31 PK3/UDS PK1/R/W NC 32 VCC VCC VCC

3.13 POWER SUPPLY

There are two power input connectors on the ADS, P1 and P2. P1 is designed for external

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3V DC main power supply, which supplies power to the MC68EZ328 processor and most of the on-board components. P2 is used for LCD driver (VEE) power supply. If an LCD panel

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is connected to the ADS, the LCD driver can be powered by this VEE input. Figure 3-12 locates the power connectors and their polarity.

P2

GND

VEE

Debug Port

nc...

P1

GND

_

EZ UART

3.0-3.3V

+

M68EZ328ADS

Figure 3-12. Power Connectors

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Comparison of M68EZ328ADS Version 1.x and 2.0

APPENDIX A COMPARISON OF M68EZ328ADS VERSION 1.X AND 2.0

This section describes the difference between the M68EZ328ADS version 1.x and 2.0. If user is not upgrading the development platform from M68EZ328ADS v1.x to v2.0, this section can be ignored.

A.1 HARDWARE

Table A-1 shows the difference between the M68EZ328ADS v1.x and v2.0.

Table A-1. Comparison of M68EZ328ADS v1.x and v2.0

Descriptions Version 1.x Version 2.0

Flash Memory 2M-byte Flash Memory using four AT29BV040

SRAM 256K-byte SRAM No SRAM

EDO DRAM

Touch Panel Interface MAXIM MAX1249 and four transistors Burr-Brown ADS7843E

Expansion Socket Same pin assignment Same pin assignment

LCD Connector Same pin assignment Same pin assignment

IrDA No HSDL-3201

Debug Port

Buzzer No Citizen CHB-03E

Bus Width 8-bit/16-bit 16-bit only

4M-byte EDO DRAM using the WE MC68EZ328

ADI Port andMC68681 Serial Port with max. baud rate = 57600bps

signal of

2M-byte Flash Memory using one MBM29LV160T (expandable to 4M-byte Flash Memory)

8M-byte EDO DRAM using the DWE signal of MC68EZ328

ST16C2552A SerialPort with max. baud rate = 115200bps

A.2 SOFTW ARE

Table A-2 shows the software change in M68EZ328ADS v2.0.

Table A-2. Software Change for using M68EZ328ADS v2.0

Items Descriptions

Initizalization Code

Touch Panel

Controller Device

Driver

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DWE

IrDA The IrDA module needs to beenabled by setting PD4 to zero.

The new ADSis equipped with differentmemory device. So, theinitizalizationcode needsto be changed.

Burr-Brown ADS7843E is used. A new device driver is required.

Pin12(DWE/UCLK/PE3) of MC68EZ328is programmed as DWEsignals foron-boardEDO DRAM. It cannot be used as Port or UCLKagain.

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A-29 M68EZ328ADS v2.0 USER’S MANUAL MOTOROLA

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APPENDIX B RESISTIVE TOUCH PANEL OPERATION

M68VZ328ADSfeaturespeninputthrough a resistive-film sensing panel.Thistype of panel provides high flexibility by accepting input form any kind of stimulus including fingers, which is most suitable for portable use. User can select a specific touch panel or order an LCD module which includes a touch resistive panel. This section describes the basic concepts of pen input and the required interface with the M68VZ328ADS.

B.1 GENERAL CONCEPTS OF RESISTIVE PANELS

Basically, resistive panel consists of two transparent resistive layers separated by insulating spacers as shown in Figure 2-1.

Figure 2-1. Resistive Touch Panel

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Transparent Resistive Layer

coated on dielectric (insulating) substrate, usually glass on bottom and plastic on top for actuation.

Bars

- highly conductivematerial such as silver ink, about1000timesmore conductivethan

ITO.

Spacers

the two opposite conductive layers.

MOTOROLA M68EZ328ADS v2.0 USER’S MANUAL B-30

- Non-conducting ink,adhesive, orothermaterial suchasMylaris used toseparate

- resistive material such as an indium tin oxide (ITO) film is

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Resistive Touch Panel Operation

The resistive panel works by applying a voltage gradient across one conductive layer and measuring the voltage at the point of contact with the opposing conductive layer. For instance, as shown in Figure 2-2, the resistive film acts as a series of resistors.

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Figure 2-2. Determination of X,Y Position

When a point is contacted, it means the two opposing conductive layers come into electrical contact. The x position of actuation can be determined by measuring the output voltage of the y layer. At the same time, the y position can be find out by measuring the x layer. The exact position can be determined by referencing the output voltage to the distance relationship.

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APPENDIX C PROGRAMMING ON-BOARD FLASH MEMORY

C.1 OVERVIEW

The Flash memory on the ADS board cannot be written directly. A special program command sequence is required to unlock it before starting the write process. A flash program is thereforeprovided withtheADS board forhelpingusersto do re-programming.The sections below will describe the program and provide further information about the process and other required elements.

Itisrecommended thatusershould haveabasicunderstandingofbootstrap modeoperation of MC68EZ328 before reading the material below. For more details on Bootstrap mode, please refer to the MC68EZ328 user’s manual.

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C.2 ELEMENTS FOR PROGRAMMING THE FLASH

The following files are necessary for programming the Flash memory

1. EZTOOLS including BBUG.EXE and STOB.EXE

2. INIT.B - b-record for initializing the ADS

3. ERASE.B - b-record for erasing the flash memory

4. FLASHNML.B-b-recordforprogramming flash.ROMimage is copiedfromRAM area to the Flash memory area

5. ROM.B - ROM image of user program in b-record/s-record format.

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Programming On-board Flash Memory

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C.3 METHOD

System RAM

FLASH Program

nc...

ROM Image

offset

Copy the ROM Image from system RAM to Flash Memory by the flash Program.

Flash Memory

Figure C-1. Method of programming on-board Flash memory

Flash memory can be programmed in bootstrap mode. First, a ROM image and a flash program are downloaded to the system memory by loading their b-records. Then, run the flash program. It will execute the Flash program command sequence and copy the ROM image from the system RAM to the Flash memory. The detailed steps are as follows.

1. Force the MC68EZ328 into bootstrap mode by turning S2-8 on and pressing RESET switch once.

2. Use BBUG.EXE or TERMINAL program to communicate with the M68EZ328ADS through RS232 port of a PC.

3. Initialize the internal registers of DragonBall-VZ by loading the INIT.B.

4. Make sure the Flash Memory is blank. Load ERASE.B to erase the flash memory when needed.

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5. Load FLASHNML.B (the Flash Program) and ROM.B (the ROM image) to system RAM (EDO DRAM on M68EZ328ADS).

6. Execute the Flash Program by using the execution B-record. For example, if the startingaddressof FlashProgramis 0x4000,the executionB-recordisthen"0000400000".

C.4 OFFSET ADDRESS OF ROM IMAGE

Figure C-1 shows that the ROM image is first put to the system RAM before it is copied to Flash. In order to create S-record/B-record with download address different from its execution address, an OFFSET is sometimes required to be specified in downloading program.

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Programming On-board Flash Memory

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For example, when using SDS’s DOWN.EXE to generate the s-record, the "-w offset" parameter can be used to specify this offset value. Please refer to the SingleStep User Guide for using this command.

C.5 EXECUTING PROGRAM COMMAND SEQUENCE

Listed below is the source code of the flash Program which contains the necessary steps to write the flash m emory MBM29LV160T. It executes the flash program command sequence and copies the ROM image from RAM area to the Flash memory area on ADS board. Figure C-2 shows the flow chart of this program. Different brands of Flash memory may have different program command sequences, please refer to their datasheets for more details.

XREF STKTOP

OFFSET1 equ $AAA OFFSET2 equ $554

nc...

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TIME equ $FFF

***************************************************************** ECHO MACRO CHAR

bsr TXD_RDY nop nop nop move.b #CHAR,$FFFFF907 ENDM

***************************************************************** ENABLE MACRO

move.w #$00AA,(A5) ; Unlock Flash move.w #$0055,(A6) move.w #$00A0,(A5) ENDM

*****************************************************************

SECTION parameter pSOURCE DC.L $00010000 pTARGET DC.L $01000000 pSIZE DC.L $00010000 pFLASH DC.L $01000000

pERROR DC.L $0 pFINISH DC.L $0 pERROR_ADDRESS DC.L $0

DC.L STKTOP

*****************************************************************

SECTION code START

MOVEA.L #STKTOP,a7 ;re-istall stack pointer in case bootstrap mode

MOVE.L #0,pERROR

MOVE.L #0,pFINISH

move.l #0,pERROR_ADDRESS

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Programming On-board Flash Memory

move.l pSOURCE,A0

move.l pTARGET,A1

move.l pSIZE,D0

move.l pFLASH,A5

move.l pFLASH,A6

******************************************* * BreakPoint Here if program flash in SDS * *******************************************

add.l #OFFSET1,A5

add.l #OFFSET2,A6

**************************************************

;*****************************************

; Input Parameters:

; a0 - (Long) Source Address

; a1 - (Long) Target Address

; d0 - (Long) Byte Size

; a5 - (long) Flash Starting Address Offset1

; a6 - (long) Flash Starting Address Offset2

;*****************************************

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move.l a0,a2 ; a2 as source

move.l a1,a3 ; a3 as target

clr.l d1 ; clear d1 as counter

clr.b d5 ; clear d5 as ECHO counter

PROGRAM

ENABLE

move.w (a2),(a3) ; Copy source to target

clr.l d4 ; clear d4 as polling counter POLLING

cmp.l #TIME,d4

bgt ERROR ; if d4>#TIME, bra ERROR

add.l #1,d4 ; d4++

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NO_W add.b #1,d5

move.w (a2),d2 ; Compare (a0),(a1)

move.w (a3),d3

cmp.w d2,d3

bne POLLING ; End of POLLING

add.l #2,a2

add.l #2,a3

add.l #2,d1

cmp.b #0,d5

bne NO_W

ECHO 'W'

ECHO 0

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Programming On-board Flash Memory

cmp.l d0,d1 ; if d1<=d0, bra PROGRAM

ble PROGRAM

;*****************************************

; Input Parameters:

; a0 - (Long) Source Address

; a1 - (Long) Target Address

; d0 - (Long) Byte Size

; a5 - (long) Flash Starting Address Offset 1

; a6 - (long) Flash Starting Address Offset 2

;*****************************************

move.l a0,a2 ;a2 & a3 are used to store the starting address

move.l a1,a3 ;for comparing.

clr.b d5 ;clear d5 as ECHO counter

clr.l d1 ;clear d1 as counter VERIFIY

cmp.b #0,d5

bne NO_V

ECHO 'V'

ECHO 0 NO_V add.b #1,d5

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move.w (a2)+,d2

move.w (a3)+,d3

cmp.w d2,d3

bne ERROR

add.l #2,d1

cmp.l d0,d1 ; if d1<=d0, bra CHECK

ble VERIFIY

bra FINISH

****************************************************************************

TXD_RDY

move.l d7,-(a7) ; Push d7 POLLTXD

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LP_RDY sub.w #1,d7

btst.b #5,$FFFFF906

beq.s POLLTXD ; bra if TXAVAIL not SET

move.w #$0FFF,d7

bne.b LP_RDY

move.l (a7)+,d7 ; Restore d7

rts

****************************************************************************

FINISH

ECHO '\n'

ECHO 'P'

ECHO 'A'

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Programming On-board Flash Memory

ECHO 'S'

ECHO '\n'

ECHO 0

move.l #1,pFINISH

bra BOOTSTRAP

************************************************************

ERROR

ECHO '\n'

ECHO 'E'

ECHO 'R'

ECHO 'O'

ECHO 'R'

ECHO '\n'

ECHO 0

sub.l #1,a3

move.l a3,pERROR_ADDRESS

move.l #1,pERROR

bra BOOTSTRAP

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************************************************************

BOOTSTRAP

jmp $FFFFFF44

************************************************************

END

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C-38 M68EZ328ADS v2.0 USER’S MANUAL MOTOROLA

Figure C-2. Flash Program Algorithm

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APPENDIX D MONITOR INITIALIZATION CODE

D.1 INITIALIZATION CODE OF METROWERKS MONITOR (RESET.S)

MON_STACKTOP.equ$4100; Above is TOO low, try this

M328BASE .equ $FFFFF000

; SIM28 System Configuration Registers SCR .equ (M328BASE+$000)

; Chip Select Registers GRPBASEA .equ (M328BASE+$100) GRPBASEB .equ (M328BASE+$102) GRPBASEC .equ (M328BASE+$104) GRPBASED .equ (M328BASE+$106) CSA .equ (M328BASE+$110) CSB .equ (M328BASE+$112) CSC .equ (M328BASE+$114) CSD .equ (M328BASE+$116) DRAMCFG .equ (M328BASE+$C00) DRAMCTL .equ (M328BASE+$C02) EMUCS .equ (M328BASE+$118) CSCTR .equ (M328BASE+$150)

; PLL Registers PLLCR .equ (M328BASE+$200) ; Control Reg PLLFSR .equ (M328BASE+$202) ; Freq Select Reg PLLTSR .equ (M328BASE+$204) ; Test Reg

; Power Control Registers PCTLR .equ (M328BASE+$206) ; Control Reg

; Interrupt Registers IVR .equ (M328BASE+$300) ; Interrupt Vector Reg ICR .equ (M328BASE+$302) ; Interrupt Control Reg IMR .equ (M328BASE+$304) ; Interrupt Mask Reg ISR .equ (M328BASE+$30C) ; Interrupt Status Reg IPR .equ (M328BASE+$310) ; Interrupt Pending Reg

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; PIO Registers

; Port A Registers PADIR .equ (M328BASE+$400) ; Direction Reg PADATA .equ (M328BASE+$401) ; Data Reg PAPUEN .equ (M328BASE+$402) ; Pullup Enable Reg

; Port B Registers PBDIR .equ (M328BASE+$408) ; Direction Reg PBDATA .equ (M328BASE+$409) ; Data Reg PBPUEN .equ (M328BASE+$40A) ; Pullup Enable Reg PBSEL .equ (M328BASE+$40B) ; Select Reg

; Port C Registers PCDIR .equ (M328BASE+$410) ; Direction Reg PCDATA .equ (M328BASE+$411) ; Data Reg

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Monitor Initialization Code

PCPDEN .equ (M328BASE+$412) ; Pull-down Enable Reg PCSEL .equ (M328BASE+$413) ; Select Reg

PDDIR .equ (M328BASE+$418) ; Direction Reg PDDATA .equ (M328BASE+$419) ; Data Reg PDPUEN .equ (M328BASE+$41A) ; Pullup Enable Reg PDSEL .equ (M328BASE+$41B) ; port D select PDPOL .equ (M328BASE+$41C) ; Polarity Reg PDIRQEN .equ (M328BASE+$41D) ; IRQ Enable Reg PDIRQEDGE .equ (M328BASE+$41F) ; IRQ Edge Reg

PEDIR .equ (M328BASE+$420) ; Direction Reg PEDATA .equ (M328BASE+$421) ; Data Reg PEPUEN .equ (M328BASE+$422) ; Pullup Enable Reg PESEL .equ (M328BASE+$423) ; Select Reg

PFDIR .equ (M328BASE+$428) ; Direction Reg PFDATA .equ (M328BASE+$429) ; Data Reg PFPUEN .equ (M328BASE+$42A) ; Pullup Enable Reg PFSEL .equ (M328BASE+$42B) ; Select Reg

PGDIR .equ (M328BASE+$430) ; Direction Reg PGDATA .equ (M328BASE+$431) ; Data Reg PGPUEN .equ (M328BASE+$432) ; Pullup Enable Reg PGSEL .equ (M328BASE+$433) ; Select Reg

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; Port D Registers

; Port E Registers

; Port F Registers

; Port G Registers

; PWM Registers PWMC .equ (M328BASE+$500) ; Control Reg PWMS .equ (M328BASE+$502) ; Sample Reg PWMCNT .equ (M328BASE+$504) ; Count Reg

; Timer Registers

; Timer 1 Registers TCTL .equ (M328BASE+$600) ; Control Reg TPRER .equ (M328BASE+$602) ; Prescalar Reg TCMP .equ (M328BASE+$604) ; Compare Reg TCR .equ (M328BASE+$606) ; Capture Reg TCN .equ (M328BASE+$608) ; Counter TSTAT .equ (M328BASE+$60A) ; Status Reg

; SPI Registers

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SPIMDATA .equ (M328BASE+$800) ; Control/Status Reg SPIMCONT .equ (M328BASE+$802) ; Data Reg

; UART Registers USTCNT .equ (M328BASE+$900) ; Status Control Reg UBAUD .equ (M328BASE+$902) ; Baud Control Reg UARTRX .equ (M328BASE+$904) ; Rx Reg UARTTX .equ (M328BASE+$906) ; Tx Reg UARTMISC .equ (M328BASE+$908) ; Misc Reg UARTNIPR .equ (M328BASE+$90A) ; None-Integer Prscaler reg

; LCDC Registers LSSA .equ (M328BASE+$A00) ; Screen Start Addr Reg LVPW .equ (M328BASE+$A05) ; Virtual Page Width Reg

D-41 M68EZ328ADS v2.0 USER’S MANUAL MOTOROLA

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Monitor Initialization Code

LXMAX .equ (M328BASE+$A08) ; Screen Width Reg LYMAX .equ (M328BASE+$A0A) ; Screen Height Reg LCXP .equ (M328BASE+$A18) ; Cursor X Position LCYP .equ (M328BASE+$A1A) ; Cursor Y Position LCWCH .equ (M328BASE+$A1C) ; Cursor Width & Height Reg LBLKC .equ (M328BASE+$A1F) ; Blink Control Reg LPICF .equ (M328BASE+$A20) ; Panel Interface Config Reg LPOLCF .equ (M328BASE+$A21) ; Polarity Config Reg LACDRC .equ (M328BASE+$A23) ; ACD (M) Rate Control Reg LPXCD .equ (M328BASE+$A25) ; Pixel Clock Divider Reg LCKCON .equ (M328BASE+$A27) ; Clocking Control Reg LRRA .equ (M328BASE+$A29) ; Refresh Rate Adjust reg LPOSR .equ (M328BASE+$A2D) ; Panning Offset Reg LFRCM .equ (M328BASE+$A31) ; Frame Rate Control Mod Reg LGPMR .equ (M328BASE+$A33) ; Gray Palette Mapping Reg LPWM .equ (M328BASE+$A36) ; contrast control Reg

; RTC Registers RTCHMSR .equ (M328BASE+$B00) ; Hrs Mins Secs Reg RTCALM0R .equ (M328BASE+$B04) ; Alarm Register RTCDAY .equ (M328BASE+$B08) ; RTC date reg RTCWD .equ (M328BASE+$B0A) ; RTC watch dog timer reg RTCCTL .equ (M328BASE+$B0C) ; Control Reg RTCISR .equ (M328BASE+$B0E) ; Interrupt Status Reg RTCIENR .equ (M328BASE+$B10) ; Interrupt Enable Reg RSTPWCH .equ (M328BASE+$B12) ; Stopwatch Minutes

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;ICEM registers ICEMACR .equ (M328BASE+$D00) ICEMAMR .equ (M328BASE+$D04) ICEMCCR .equ (M328BASE+$D08) ICEMCMR .equ (M328BASE+$D0A) ICEMCR .equ (M328BASE+$D0C) ICEMSR .equ (M328BASE+$D0E)

**************************************************************************** * RESET OPTIONS ****************************************************************************

.section .reset

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rom_base: ;-- SECTIONrom_reset - SP, start addr & space for Exception Vectors

.DC.LMON_STACKTOP; stack pointer .DC.Lrom_start ; program counter

.org0x10 ; int7 handler (in EMU mode) goes here .externemu_lvl7_handler jmp emu_lvl7_handler

.org0x20 ; initial code starts at offset 0x20

;-- SECTIONrom_code

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Monitor Initialization Code

.global ___reset ___reset: rom_start:

move.b #$9,PGSEL ; config PG0/DTACK to GPI/O,input move.w #$2410,PLLCR ; sysclk = VCO/1, enable clko move.l #MON_STACKTOP,A7 ; Install stack pointer move.w #$2700,sr ; mask off all interrupts move.b #$1C,SCR ; enable bus error timeout bit move.w #0,RTCWD ; disable watch dog move.b #$03,PFSEL ; select A23-A20, CLKO, CSA1 move.b #$00,PBSEL ; Config port B for chip select A,B,C and D move.b #$00,PESEL ; select *DWE move.w #$08,ICEMCR ; disable ICEM vector hardmap move.w #$07,ICEMSR ; clear level 7 interrupt

;***************************** ; Init Code for 512Kx16 Flash ;*****************************

move.w #$0400,GRPBASEA ; GROUPA BASE(FLASH), Start address=0x800000 move.w #$0189,CSA ; 2MB each, 0ws, FLASH,

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;********************************** ; Init Code 4Mx16 (12/10) EDO DRAM ;**********************************

move.w #$8F00,DRAMCFG ; DRAM Memory Config Register

; Col Address = PA1-PA10; Row Address = PA11-PA22 move.w #$9667,DRAMCTL ; DRAM Control Register, 0ws move.w #$0000,GRPBASED ; GROUPA BASE(DRAM),

;Start address=0x000000-0x7FFFFF

move.w #$069F,CSD ; enable DRAM cs

;********************************** ; Init Code for EMUCS ;**********************************

move.w #$30,EMUCS ; 3ws

clr.l d0 clr.l d1 clr.l d2 clr.l d3

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clr.l d4 clr.l d5 clr.l d6 clr.l d7

;********************************************************************** ; ; LCD Temp init for screen protection ; ;**********************************************************************

move.b #0,PCSEL move.b #0,PCPDEN

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Monitor Initialization Code

move.l #$4000,LSSA move.w #160,LXMAX move.w #239,LYMAX move.b #10,LVPW move.b #$08,LPICF move.b #$01,LPOLCF move.b #$00,LACDRC move.b #$02,LPXCD move.b #$14,LRRA move.b #$00,LPOSR move.b #$00,LCKCON ; disable LCDC move.b #$80,LCKCON ; enable LCDC, 0ws, 16-bit

;********************************************************************** ; Interrupt controller ;**********************************************************************

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nc...

move.b #$40,IVR move.l #$007fffff,IMR; mask all interrupts except *EMUIRQ,

button

.extern__start JMP __start ; jump to MW startup code

D.2 INITIA LIZATION CODE OF SDS MONITOR (MONITOR.H)

.option list="off" **************************************************************************** * EZ328EMU.H - Configuration file for Motorola's M68EZ328ADS ****************************************************************************

**************************************************************************** * CPU OPTIONS ****************************************************************************

opt p=68000

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M328BASE equ $FFFFF000

; since it is used for the abort

; on this board

; SIM28 System Configuration Registers SCR equ (M328BASE+$000)

; Chip Select Registers GRPBASEA equ (M328BASE+$100) GRPBASEB equ (M328BASE+$102) GRPBASEC equ (M328BASE+$104) GRPBASED equ (M328BASE+$106) CSA equ (M328BASE+$110) CSB equ (M328BASE+$112) CSC equ (M328BASE+$114) CSD equ (M328BASE+$116) DRAMCFG equ (M328BASE+$C00)

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Monitor Initialization Code

DRAMCTL equ (M328BASE+$C02) EMUCS equ (M328BASE+$118) CSCTR equ (M328BASE+$150)

; PLL Registers PLLCR equ (M328BASE+$200) ; Control Reg PLLFSR equ (M328BASE+$202) ; Freq Select Reg PLLTSR equ (M328BASE+$204) ; Test Reg

; Power Control Registers PCTLR equ (M328BASE+$206) ; Control Reg

; Interrupt Registers IVR equ (M328BASE+$300) ; Interrupt Vector Reg ICR equ (M328BASE+$302) ; Interrupt Control Reg IMR equ (M328BASE+$304) ; Interrupt Mask Reg ISR equ (M328BASE+$30C) ; Interrupt Status Reg IPR equ (M328BASE+$310) ; Interrupt Pending Reg

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nc...

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; PIO Registers

; Port A Registers PADIR equ (M328BASE+$400) ; Direction Reg PADATA equ (M328BASE+$401) ; Data Reg PAPUEN equ (M328BASE+$402) ; Pullup Enable Reg

; Port B Registers PBDIR equ (M328BASE+$408) ; Direction Reg PBDATA equ (M328BASE+$409) ; Data Reg PBPUEN equ (M328BASE+$40A) ; Pullup Enable Reg PBSEL equ (M328BASE+$40B) ; Select Reg

; Port C Registers PCDIR equ (M328BASE+$410) ; Direction Reg PCDATA equ (M328BASE+$411) ; Data Reg PCPDEN equ (M328BASE+$412) ; Pull-down Enable Reg PCSEL equ (M328BASE+$413) ; Select Reg

; Port D Registers PDDIR equ (M328BASE+$418) ; Direction Reg PDDATA equ (M328BASE+$419) ; Data Reg PDPUEN equ (M328BASE+$41A) ; Pullup Enable Reg PDSEL equ (M328BASE+$41B) ; port D select PDPOL equ (M328BASE+$41C) ; Polarity Reg PDIRQEN equ (M328BASE+$41D) ; IRQ Enable Reg PDIRQEDGE equ (M328BASE+$41F) ; IRQ Edge Reg

; Port E Registers PEDIR equ (M328BASE+$420) ; Direction Reg PEDATA equ (M328BASE+$421) ; Data Reg PEPUEN equ (M328BASE+$422) ; Pullup Enable Reg PESEL equ (M328BASE+$423) ; Select Reg

; Port F Registers PFDIR equ (M328BASE+$428) ; Direction Reg PFDATA equ (M328BASE+$429) ; Data Reg PFPUEN equ (M328BASE+$42A) ; Pullup Enable Reg PFSEL equ (M328BASE+$42B) ; Select Reg

; Port G Registers PGDIR equ (M328BASE+$430) ; Direction Reg PGDATA equ (M328BASE+$431) ; Data Reg

D-45 M68EZ328ADS v2.0 USER’S MANUAL MOTOROLA

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Monitor Initialization Code

PGPUEN equ (M328BASE+$432) ; Pullup Enable Reg PGSEL equ (M328BASE+$433) ; Select Reg

; PWM Registers PWMC equ (M328BASE+$500) ; Control Reg PWMS equ (M328BASE+$502) ; Sample Reg PWMCNT equ (M328BASE+$504) ; Count Reg

; Timer Registers

TCTL equ (M328BASE+$600) ; Control Reg TPRER equ (M328BASE+$602) ; Prescalar Reg TCMP equ (M328BASE+$604) ; Compare Reg TCR equ (M328BASE+$606) ; Capture Reg TCN equ (M328BASE+$608) ; Counter TSTAT equ (M328BASE+$60A) ; Status Reg

; SPI Registers SPIMDATA equ (M328BASE+$800) ; Control/Status Reg SPIMCONT equ (M328BASE+$802) ; Data Reg

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; Timer 1 Registers

; UART Registers USTCNT equ (M328BASE+$900) ; Status Control Reg UBAUD equ (M328BASE+$902) ; Baud Control Reg UARTRX equ (M328BASE+$904) ; Rx Reg UARTTX equ (M328BASE+$906) ; Tx Reg UARTMISC equ (M328BASE+$908) ; Misc Reg UARTNIPR equ (M328BASE+$90A) ; None-Integer Prscaler reg

; LCDC Registers LSSA equ (M328BASE+$A00) ; Screen Start Addr Reg LVPW equ (M328BASE+$A05) ; Virtual Page Width Reg LXMAX equ (M328BASE+$A08) ; Screen Width Reg LYMAX equ (M328BASE+$A0A) ; Screen Height Reg LCXP equ (M328BASE+$A18) ; Cursor X Position LCYP equ (M328BASE+$A1A) ; Cursor Y Position LCWCH equ (M328BASE+$A1C) ; Cursor Width & Height Reg LBLKC equ (M328BASE+$A1F) ; Blink Control Reg LPICF equ (M328BASE+$A20) ; Panel Interface Config Reg LPOLCF equ (M328BASE+$A21) ; Polarity Config Reg LACDRC equ (M328BASE+$A23) ; ACD (M) Rate Control Reg

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LPXCD equ (M328BASE+$A25) ; Pixel Clock Divider Reg LCKCON equ (M328BASE+$A27) ; Clocking Control Reg LRRA equ (M328BASE+$A29) ; Refresh Rate Adjust reg LPOSR equ (M328BASE+$A2D) ; Panning Offset Reg LFRCM equ (M328BASE+$A31) ; Frame Rate Control Mod Reg LGPMR equ (M328BASE+$A33) ; Gray Palette Mapping Reg LPWM equ (M328BASE+$A36) ; contrast control Reg

; RTC Registers RTCHMSR equ (M328BASE+$B00) ; Hrs Mins Secs Reg RTCALM0R equ (M328BASE+$B04) ; Alarm Register RTCDAY equ (M328BASE+$B08) ; RTC date reg RTCWD equ (M328BASE+$B0A) ; RTC watch dog timer reg RTCCTL equ (M328BASE+$B0C) ; Control Reg

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Monitor Initialization Code

RTCISR equ (M328BASE+$B0E) ; Interrupt Status Reg RTCIENR equ (M328BASE+$B10) ; Interrupt Enable Reg RSTPWCH equ (M328BASE+$B12) ; Stopwatch Minutes

;ICEM registers ICEMACR equ (M328BASE+$D00) ICEMAMR equ (M328BASE+$D04) ICEMCCR equ (M328BASE+$D08) ICEMCMR equ (M328BASE+$D0A) ICEMCR equ (M328BASE+$D0C) ICEMSR equ (M328BASE+$D0E)

**************************************************************************** * ADDRESSING OPTIONS **************************************************************************** ;INTERVAL: equ 2 INTERVAL: equ 1 **************************************************************************** * I/O DEVICE OPTIONS **************************************************************************** ***************************************************************** * WARNING: This file redefines _usr_gchar bypassing the BSP * *****************************************************************

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**************************************** * Setting for ST16C2552 **************************************** #define DEV_IN ST16C2552 #define DEV_OUT ST16C2552 BASE_IN: equ $FFFD0000 ; base address BASE_OUT: equ $FFFD0000 ; base address BAUD_IN: equ 576 ; baud rates = BAUD_IN/100 bps BAUD_OUT: equ 576 ; baud rates = BAUD_OUT/100 bps

**************************************** * Setting for EZ-UART **************************************** ;#define DEV_IN EZUART ;#define DEV_OUT EZUART ;BASE_IN: equ $fffd8000 ; base address not applicable ;BASE_OUT: equ $fffd8000 ; base address not applicable

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;BAUD_IN: equ 1152 ; baud rates = 115200 bps ;BAUD_OUT: equ 1152 ; baud rates = 115200 bps

**************************************** * Seting for ADI PORT on EZ-ADS **************************************** ;#define DEV_IN ADIPORT ;#define DEV_OUT ADIPORT ;BASE_IN: equ $fffd8000 ; base address of input device ;BASE_OUT: equ $fffd8000 ; base address of output device ;BAUD_IN: equ 0 ; baud rates not applicable ;BAUD_OUT: equ 0 ; baud rates not applicable

****************************************

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* Seting for MC68681 on EZ-ADS * Supported baudrate: 19200 * 9600 **************************************** ;#define DEV_IN MC68681 ;#define DEV_OUT MC68681 ;#define PNAME_IN A ;#define PNAME_OUT A ;BASE_IN: equ $fffd0001 ; base address of input device ;BASE_OUT: equ $fffd0001 ; base address of output device ;BAUD_IN: equ 19200 ; baud rates (bits/sec) ;BAUD_OUT: equ 19200 ; baud rates (bits/sec) ;ACR_VAL: equ $80 ; choose baud set 2 (bit#7=1) ;IRQ_MASK: equ $00 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

***************************************************** * Seting for MC68681 on EZ-ADS with BaudRate=57600bps ***************************************************** ;#define DEV_IN MC68681 ;#define DEV_OUT MC68681 ;#define PNAME_IN A ;#define PNAME_OUT A ;BASE_IN: equ $fffd0001 ; base address of input device ;BASE_OUT: equ $fffd0001 ; base address of output device ;BAUD_IN: equ 0 ;BAUD_OUT: equ 0 ;ACR_VAL: equ $60 ;IRQ_MASK: equ $00 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

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**************************************************************************** * INTERRUPT BEHAVIOR OPTIONS **************************************************************************** #define STOP_LEVEL 7

#define VECT_STOP $47 ; ABORT interrupt

; ************************************************** ; If your board hardware requires you to clear the ; "read" interrupt, then you must include the necessary

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INT_RCLEAR: macro

INT_STOP: macro

; code inside the INT_RCLEAR macro below. ; **************************************************

endm

; ************************************************** ; "stop" interrupt ; We will only stop the target if the ABORT switch is pressed. We ; will not stop for HOST_NMI or EXT_NMI interrupts. ; The Non-Maskable Interrupt status is in the NMI_STATUS register ; which is in even-byte locations at NMI_STATUS. Bit #0 of the ; first byte at NMI_STATUS indicates that the ABORT switch was pressed. ; **************************************************

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move.w #$7,ICEMSR ; clear level 7 interrupt or.w #$FF80,ISR endm ; return non-zero in D0 if ABORT

INT_DOG: macro

endm

; ************************************************** ; Macros for use at application startup (EXEC) ; and stop (DONE). Normally these are empty. ; **************************************************

USR_EXEC: macro

endm

USR_DONE: macro

endm

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nc...

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**************************************************************************** * RESET OPTIONS ****************************************************************************

; ************************************************** ; Contents of the "usr_reset" section. In the usual ; case, this is two longwords long, with the first word ; containing the value with which the processor ; loads up its stack pointer, and the second of ; which is the value with which the processor ; loads up its program counter. This will bring up ; the monitor on a hardware reset. ; **************************************************

USR_RESET: macro

dc.l MON_STACKTOP ; stack pointer (default) dc.l reset$$$ ; program counter (default) dcb.l 6,0 endm

; ************************************************** ; Hard reset macro - contains very high priority ; instructions which must be executed immediately ; upon a hardware reset. ; **************************************************

RESET_HARD: macro

move.b #$9,PGSEL ; config PG0/DTACK to GPI/O,input move.w #$2410,PLLCR ; sysclk = VCO/1, enable clko move.l #MON_STACKTOP,A7 ; Install stack pointer move.w #$2700,sr ; mask off all interrupts move.b #$1C,SCR ; enable bus error timeout bit move.w #0,RTCWD ; disable watch dog move.b #$03,PFSEL ; select A23-A20, CLKO, CSA1 move.b #$00,PBSEL ; Config port B for chip select A,B,C and D move.b #$00,PESEL ; select *DWE move.w #$08,ICEMCR ; disable ICEM vector hardmap

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Monitor Initialization Code

move.w #$07,ICEMSR ; clear level 7 interrupt

;***************************** ; Init Code for 512Kx16 Flash ;*****************************

move.w #$0400,GRPBASEA ; GROUPA BASE(FLASH), Start address=0x800000 move.w #$0189,CSA ; 2MB each, 0ws, FLASH,

;********************************** ; Init Code 4Mx16 (12/10) EDO DRAM ;**********************************

move.w #$8F00,DRAMCFG ; DRAM Memory Config Register

move.w #$9667,DRAMCTL ; DRAM Control Register, 0ws move.w #$0000,GRPBASED ; GROUPA BASE(DRAM), Start address=0x000000-

0x7FFFFF

move.w #$069F,CSD ; enable DRAM cs

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; Col Address = PA1-PA10; Row Address = PA11-PA22

nc...

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;********************************** ; Init Code for EMUCS ;**********************************

move.w #$30,EMUCS ; 3ws

clr.l d0 clr.l d1 clr.l d2 clr.l d3 clr.l d4 clr.l d5 clr.l d6 clr.l d7

;********************************************************************** ; ; LCD Temp init for screen protection ; ;**********************************************************************

move.b #0,PCSEL move.b #0,PCPDEN

move.l #$4000,LSSA move.w #160,LXMAX move.w #239,LYMAX move.b #10,LVPW move.b #$08,LPICF move.b #$01,LPOLCF move.b #$00,LACDRC move.b #$02,LPXCD move.b #$14,LRRA move.b #$00,LPOSR move.b #$00,LCKCON ; disable LCDC move.b #$80,LCKCON ; enable LCDC, 0ws, 16-bit

;**********************************************************************

D-50 M68EZ328ADS v2.0 USER’S MANUAL MOTOROLA

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Monitor Initialization Code

; ; Initialize I/O to avoid contention ; ;**********************************************************************

; TBD since the contention does not affect ADS operation

;********************************************************************** ; ; Program Interrupt Controller ; ;**********************************************************************

move.b #$40,IVR move.l #$007FFFFF,IMR ;enable NMI interrupt

endm

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nc...

RESET_SOFT: macro

MC68681ctur equ (BASE_IN+OFF6) MC68681ctlr equ (BASE_IN+OFF7)

****************************************************************************

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* OTHER DEFINITIONS ****************************************************************************

; ************************************************** ; Soft reset macro - contains instructions ; which must be executed upon a processor reset. ; **************************************************

; *************************************** ; * Setting for MC68681 ; *************************************** .if "\{DEV_IN}"=="MC68681"

move.b #IRQ_MASK,MC68681imr ;set value of IMR move.b #ACR_VAL,MC68681acr ;set value of ACR ; Setting for baudrates = 57600bps move.b #00,MC68681ctur move.b #02,MC68681ctlr ; divider=2 .endif

endm

USER_DEFS: macro

; *************************************** ; * Setting for MC68681 ; *************************************** .if "\{DEV_IN}"=="MC68681" xdef MC68681acr xdef MC68681imr

SECTION usr_ram MC68681acr: ds.b 1 ;ACR register

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Monitor Initialization Code

endm

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MC68681imr: ds.b 1 ;IMR register .endif

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Monitor Initialization Code

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APPENDIX E SCHEMATICS

E.1 M68EZ328ADS V2.0

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MOTOROLA M68EZ328ADS v2.0 USER’S MANUAL E-54

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nc...

J

I

H

G

J

I

H

G

F

E

D

Freescale Semiconductor, I

C

F

E

D

C

B

M68EZ328ADS

2.0

EZADS20.DSN

A

Motorola Semiconductors Hong Kong Ltd.

2 Dai King St, Tai Po Ind Est, Tai Po, NT, Hong Kong.

10 10

9 9

Version:

Schematic:

File Name:

For More Information On This Product,

8 8

Last Updated: Teddy Wong on 5 Nov, 1999

Go to: www.freescale.com

7 7

B

A

6 6

5 5

4 4

3 3

2 2

1 1

ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005

Freescale Semiconductor, Inc.

8

VCCEZ_VDD

JP1

JP2

7

C20

0.1u

C19

0.1u

TXD

RXD

SPMRXD

~DWE

~RTS

~IRQ1

~IRQ2

~IRQ3

~IRQ6

~IRQ5

SPMTXD

~INT0

~INT1

~INT2

6

C18

0.1u

~INT3

~CTS

SPMCLK

PWMO

~EMUIRQ

TOUT/TIN

nc...

C17

0.1u

VCC VCC VCC VCC

5

EZ_VDD

A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11

A[0..23]

A10

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

4

3

Freescale Semiconductor, I

2

VCC

U1

R49

17 40 58 78 97

7 6 5 4 3 2 1 100 99 98 96 95 94 93 92 91 90 89 88 86 85 84 83 82

2K

~INT0

VDD VDD VDD VDD VDD

PF6/A23 PF5/A22 PF4/A21

PF3/A20 A19 A18 A17 A16 A15 A14

MD8/A9 MD7/A8 MD6/A7 MD5/A6 MD4/A5 MD3/A4 MD2/A3 MD1/A2 MD0/A1

A0

BBUSW/DTACK76RESET77OE79UWE/WE80LWE

~RSTIN

~DTACK

~INT1

~INT2

~INT3

~IRQ1

~IRQ2

~IRQ3

33

INT0/PD036INT1/PD135INT2/PD234INT3/PD3

IRQ1/PD432IRQ2/PD530IRQ3/PD629IRQ6/PD728IRQ5/PF1

MD12/A13 MD11/A12 MD10/A11

MD9/A10

CSA057CSA156CSB0/PB055CSB1/PB154CSC0/RAS0/PB2

81

~OE

~UWE

~LWE

~CSA0

~CSA1

~OE

~LWE

~UWE

~CSA0

~RSTIN

~CSA1

~IRQ6

~CSB0

~IRQ5

27

~CSB1

SPMTXD

9

53

52

~RAS0

~RAS1

~RAS0

~RAS1

SPMRXD

SPMCLK

~DWE

RXD

TXD

12

13

14

10

11

PE3

TXD/PE5

RXD/PE4

SPMCLK/PE2

SPMTXD/PE0

SPMRXD/PE1

0&(=

CSC1/RAS1/PB3

CSD0/CAS0/PB4

CSD1/CAS1/PB5

LD0/PC046LD1/PC145LD2/PC244LD3/PC343LFRM/PC442LLP/PC541LCLK/PC639LACD/PC7

51

50

LD0

~CAS0

~CAS1

~CAS0

~CAS1

LD[0..3]

~RTS

~CTS

15

16

RTS/PE6

LD1

LD2

PWMO

47

CTS/PE7

PWMO/PB7

LD3

LFRM

TOUT/TIN

~EMUIRQ

~HIZ

18

19

48

EMUIRQ

TOUT/TIN/PB6

38

37

LLP

LCLK

LACD

CONTRAST

LLP

LCLK

LACD

~HIZ

~EMUCS

~EMUBRK

~EMUCS

~EMUBRK

20

21

HIZ/P/D

EMUCS

BST/EMUBRK

CONTRAST/PF0

CONTRAST

PLLVDD

D9 D8 PA7/D7 PA6/D6 PA5/D5 PA4/D4 PA3/D3 PA2/D2 PA1/D1 PA0/D0

CLKO/PF2

XTAL EXTAL

PLLGND GND

GND GND GND GND

D15 D14 D13 D12 D11 D10

of

8

210Wednesday, January 05, 2000

7

EZADS20.DSN 2.0

M68EZ328ADS

0RWRUROD6HPLFRQGXFWRUV+RQJ.RQJ/LPLWHG

2 Dai King Street, Tai Po Industrial Estate, Tai Po, NT, Hong Kong.

VCC

R50

330

C21

4.7u

+

CLKO

26 25 24 23 22

87 67 49 31

8

59

D15

60

D14

61

D13

62

D12

63

D11

64

D10

65

D9

66

D8

68

D7

69

D6

70

D5

71

D4

72

D3

73

D2

74

D1

75

D0

D[0..15]

C22

0.1u

22p

C24

32.768k

Y1

C23 22p

Address Decoder

U12A

VCC

1

3

~EMUCS

~CSBOOT

2

A16

C26

0.1u

6

MC74HC32AD

U12B

4

U13A

~CSUARTX

5

1 2

Title

MC74HC32AD

MC74HC14AD

B

Size Document Number Rev

Date: Sheet

6

5

4

3

~INT1

VCC

D[0..15]

VCC

C25

~INT0

LED3

0.1u

300

R52

YELLOW LED

U11E

11 10

R51

LED4

300

YELLOW LED

R54

MC74HC14AD

U11F

000

R53

2

MC74HC14AD

13 12

000

1

A[0..23]

~DTACK

LD[0..3]

For More Information On This Product,

A A

Go to: www.freescale.com

B B

~INT0

C C

~INT1

~INT0

~INT1

D D

1

ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005

Freescale Semiconductor, Inc.

C8

0.1u

8

7

VCC

A6

A2

A1

A3

A4

A025A124A223A322A421A520A619A718A88A9 VCC

37

VCC

A10

A9

A8A7A11

7

A106A115A124A133A142A151A16

*

R6000R36000

A18

A15

A17

A14

A12

A13

A16

48

A1717A18

TSOP (I)

DQ131DQ233DQ335DQ438DQ540DQ642DQ744DQ830DQ9

DQ0

U6

29

D4

D0

D2

D1

D3

D6

D5

DQ1034DQ1136DQ1239DQ1341DQ1443DQ15/A-1

32

D8

D10

D7A5D9

D11

D12

D13

D14

45

D15

47

*

R44K7

BYTE

A20

A22

A19

16

A199A20

RESET

WP/ACC14NC

12

*

R74K7

R54K7

A21

10

15

R9000

R8000

RY/BY

C10

0.1u

VCC

~UWE

~OE

~CSROM0

~OE

~UWE

11OE28CE26

USER FLASH0

WE

VSS

27

VSS

46

13

37

VCC

U8

VCC

A6

A2

A1

A4A8A7

A025A124A223A322A421A520A619A718A88A9

VCC

DQ131DQ233DQ335DQ438DQ540DQ642DQ744DQ830DQ9

DQ0

29

D4

D1

D0D5D3

D7

D2

A10

A9

A11

A12

7

A106A115A124A133A142A151A16

TSOP (I)

DQ1034DQ1136DQ1239DQ1341DQ1443DQ15/A-1

32

D8

D11

D12D6D15

D9

D10

A14A5A13

D13

A15

D14

A17

A16

48

45

A20

A22

R15000

A19

A18A3A21

16

A1717A18

A199A20

BYTE

RESET

WP/ACC14NC

47

12

*

* *

R124K7

R174K7

R144K7

10

15

R19000

R18000

RY/BY

~OE

~UWE

~CSROM1

~OE

~UWE

11OE28CE26

USER FLASH1

WE

VSS

27

VSS

46

0RWRUROD6HPLFRQGXFWRUV+RQJ.RQJ/LPLWHG

2 Dai King Street, Tai Po Industrial Estate, Tai Po, NT, Hong Kong.

13

VCC

EZADS20.DSN 2.0

M68EZ328ADS

B

Title

Size Document Number Rev

of

8

310Wednesday, January 05, 2000

7

Date: Sheet

6

A20

VCC

MBM29LV160T-90PFTN

nc...

R4, R5, R6

R4, R5, R6, R7

R4, R5

R4, R5, R7, R8, R9

INSTALL

5

C9

Am29LV640DU/Am29LV641DU

Am29DL322C/Am29DL323C

Am29LV160B/MBM29LV160

Am29LV800B

4

3

DEFAULT

VCC

0.1u

VCC

D14

D15

49

EDO DRAM

VCC

25

VCC

12

VCC

6

VCC

1

A12

U7

32

33

D13

D12

D11

D10

D6

D8

D9

42

DQ1043DQ1144DQ1246DQ1347DQ1448DQ15

D1

D4

D2

D5

D3

D0

NC11NC34NC

NC15NC16NC17NC

DQ02DQ13DQ24DQ35DQ47DQ58DQ69DQ710DQ841DQ9

A019A120A221A322A423A524A627A728A829A930A1031A11

RAS14LCAS38UCAS37OE

WE

13

Freescale Semiconductor, I

*

R33000

R35000

R34000

R31000

R32000

R30000

R29000

2

A12

A9

A8

A10

A11

A8

A13

~OE

A3

A2

A7A9A5

A4

A6

A1

~DWED7~OE

~CAS0

*

R37000

A8

~DRAM0

R38000

~DWE

~DRAM0

A10

~DWE

~CAS1

~CAS0

~DRAM0

~DWE

~DRAM0

18

36

~OE

~CAS1

A20

VCC

~CAS0

~CAS1

MBM29LV160T-90PFTN

R12, R14, R15, R17

R12, R14, R17, R18, R19

R12, R14, R15

INSTALL

Am29LV640DU/Am29LV641DU

Am29DL322C/Am29DL323C

Am29LV160B/MBM29LV160

R12, R14

INSTALL

Am29LV800B

6

5

DEFAULT

4

~CAS1

~CAS0

35

40

NC

uPD42S65165G5-A60

GND

50

GND

45

GND

39

GND

26

D8

(R29, R31, R33, R36, R38)

(R31, R33, R35, R37)

(R30, R31, R33, R35, R37)

INSTALL1M X 16 10/10 (R29, R32, R34, R35)

INSTALL

1M X 16 12/8

4M X 16 12/10

4M X 16 13/9

O013O114O215O317O418O519O620O7

U9

A012A111A210A39A48A57A66A75A827A926A1023A1125A124A1328A1429A153A162CE22OE

A1

VCC

D11

D12

D10

A5A2A8A0A11

A4

C11

0.1u

D14

D15D9D13

EMU ROM

21

3

A18

A1730WE

A10

A6

A7

A15

A12A3A13

A9

A14

A16

1

24

31

~OE

~UWE

~CSBOOT

~OE

~CSBOOT

AT29LV010A-25JI

2

~UWE

A2

A3

A4

A8A5A6

1

A[0..23]

A9A0A14

A11

A12

A10

A15

A13

A7

A21

A17

A18A1A20

A22

A19

A16

Memory

A[0..23]

A A

For More Information On This Product,

Go to: www.freescale.com

B B

D0

D[0..15]

D4

D5

D2

D1

D6

D8D7D11D3D9

D10

D12

D13

D14

C C

D15

1

D D

ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005

Freescale Semiconductor, Inc.

nc...

8

of

8

410Wednesday, January 05, 2000

VEE

7

6

VCC

LCLK

LFRM

LD3

LD1

CONTRAST

LD1

LFRM

LCLK

LD3

CONTRAST

P10

1 2

3 4

5 6

7 8

9 10

HEADER 10X2

11 12

13 14

15 16

17 18

19 20

0RWRUROD6HPLFRQGXFWRUV+RQJ.RQJ/LPLWHG

2 Dai King Street, Tai Po Industrial Estate, Tai Po, NT, Hong Kong.

Title

7

EZADS20.DSN 2.0

M68EZ328ADS

B

Size Document Number Rev

Date: Sheet

6

Connector for 4-Bit LCD

LD2

LACD

LLP

LD0

LD2

LLP

5

4

LACD

R61

000

VCC

VR1

VR_10K

VEE

VCC10VCC

U17

~CSB1

~PEN_IRQ

1

RIGHT

BOTTOM

3

11

X+2Y+

PENIRQ

DCLK16CS15DIN14DOUT12BUSY

SPMCLK

~PEN_CS

SPMRXD

SPMTXD

TOP

LEFT

5

8

X-4Y-

IN37IN4

Vref

GND

ADS7843E

9

6

13

C44

0.1u

5

4

3

RIGHT

(XMAX,YMAX)

Freescale Semiconductor, I

TOP

LCD SCREEN

(0,0)

2

1

Touch Panel & LCD

A A

LEFT

For More Information On This Product,

BOTTOM

Go to: www.freescale.com

B B

R58 10

VCC

SPMCLK

SPMRXD

2R2

C42

+

SPMTXD

~PEN_CS

22u

C43

0.1u

3

~PEN_IRQ

R57

VCC

2

1

C C

D D

ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005

Freescale Semiconductor, Inc.

nc...

8

of

8

510Wednesday, January 05, 2000

DEBUG PORT

P8

594837261

7

C29

0805_1u

C28

0805_1u

5

6

1

4

U14

0805_1u

3

C5-

C5+

STB

VSS

RIMON

28

C27

0805_1u

C31

6

5

9

RX17RX28RX3

11

10

TX1

DB9 FEMALE

13

12

14

TX2

RX4

RX5

TX3

MC145583VF

DI315DO516DI217DO418DI119DO320DO221DO122VDD23C1-24C1+25C2-26C2+

7

EZADS20.DSN 2.0

M68EZ328ADS

0RWRUROD6HPLFRQGXFWRUV+RQJ.RQJ/LPLWHG

C32

2 Dai King Street, Tai Po Industrial Estate, Tai Po, NT, Hong Kong.

0.1u

B

Title

Size Document Number Rev

Date: Sheet

6

VCC

UART

P9

594837261

MON_SEL0

MON_SEL1

MON_SEL2

DB9 FEMALE

5

VCCVCC

C30

0805_1u

4

25

26

27

TXA38TXB

RXA39RXB

DTRA37DTRB

VCC

44

VCC

32

U15

IOR24IOW20RESET21CS18CHSEL16INTA34INTB17TXRDYA1TXRDYB32A010A114A215D02D13D24D35D46D57D68D79XTAL111XTAL2

3

Freescale Semiconductor, I

2

R55

4K7

VCC

~OE

~UWE

~CSUARTX

RST_UARTX

23

RTSA36RTSB

A0A1A2

A[0..2]

19

MFA35MFB

28

CTSA40CTSB

D8D9D10

D[8..15]

D11

31

RIA43RIB

D12

D13

D14

30

CDA42CDB

D15

29

DSRA41DSRB

GND GND

13

R56 1M

VCC

22 12

ST16C2552

Y2

C35

C34

33p

3.6864MHz

C33

22p

0.1u

C39

0805_1u

C38

0805_1u

5

6

9

11

RX17RX28RX3

RXD

~CTS

13

10

12

14

TX1

TX2

TX3

RX4

RX5

DI315DO516DI217DO418DI119DO320DO221DO122VDD23C1-24C1+25C2-26C2+

MC145583VF

~RTS

TXD

1

4

3

C5-

C5+

STB

VSS

RIMON

U16

28

0805_1u

C37

0805_1u

C41

VCC

C40

RXD

~CTS

~RTS

TXD

~UART_EN

0805_1u

4

3

2

1

UART Ports

For More Information On This Product,

A A

Go to: www.freescale.com

B B

C36

0.1u

VCC

C C

D D

1

ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005

Freescale Semiconductor, Inc.

nc...

J

I

0RWRUROD6HPLFRQGXFWRUV+RQJ.RQJ/LPLWHG

2 Dai King Street, Tai Po Industrial Estate, Tai Po, NT, Hong Kong.

H

G

VCC

R39

000

C1

0.1u

F

VCC

U2

VLED

8

TXD7RXD6SD

5

VCC3GND

1

AGND

4

HSDL-3201

VCCVCCVC C

0.1u

C3

Title

of

610Wednesday, January 05, 2000

EZADS20.DSN 2.0

M68EZ328ADS

B

Size Document Number Rev

Date: Sheet

J

I

H

G

F

E

D

Freescale Semiconductor, I

C

B

1

~IRDA_EN

MC74HC125AD

U3A

+

C2

1u

E

R40

10K

2 3

56

4

U3B

MC74HC125AD

D

TXD

RXD

C

B

A

IrDA

For More Information On This Product,

10 10

9 9

8 8

Go to: www.freescale.com

7 7

A

6 6

5 5

4 4

3 3

2 2

1 1

ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005

Freescale Semiconductor, Inc.

nc...

8

C15

0.1u

of

8

710Wednesday, January 05, 2000

VCCVCC

C14

0.1u

7

0RWRUROD6HPLFRQGXFWRUV+RQJ.RQJ/LPLWHG

2 Dai King Street, Tai Po Industrial Estate, Tai Po, NT, Hong Kong.

Title

6

5

~EMU

U10A

1 2

MC74AC05D

U10B

~BOOTSTRAP

MC74AC05D

3 4

7

EZADS20.DSN 2.0

M68EZ328ADS

B

Size Document Number Rev

Date: Sheet

6

5

RST_UARTX

U11C

MC74HC14AD

5 6

4

3

Freescale Semiconductor, I

2

RST_UARTX

U11B

MC74HC14AD

3 4

U11A

MC74HC14AD

1 2

C13

4.7u

+

R46

300K

VCC

RESET

SW1

1

Reset Circuit

A A

For More Information On This Product,

Go to: www.freescale.com

B B

PUSHBUTTON

~RSTIN

R48

100K

U11D

U10C

~EMUIRQ

5 6

9 8

MC74AC05D

MC74HC14AD

C16

+

4.7u

4

3

2

VCC

SW2

ABORT

PUSHBUTTON

C C

D D

1

ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005

Freescale Semiconductor, Inc.

nc...

EZADS20.DSN 2.0

M68EZ328ADS

B

Title

Size Document Number Rev

GND

of

8

810Wednesday, January 05, 2000

7

Date: Sheet

6

8

R60

4K7

~UART_EN

~IRDA_EN

VCC

R59

4K7

RP3

~PEN_CS

~PEN_IRQ

TONE_OUT

7

VCC

4 5

RP1

4K7 X 4

3 6 2 7 1 8

8

S1

9

VCC

1234567

RP2

SW DIP-8

16151413121110

VCC

6

4K7 X 4

4 5 3 6 2 7 1 8

S2

~CSROM0

~CSROM1

~DRAM0

~EMUBRK

~EMUIRQ

~DRAM0

~EMUIRQ

~CSROM0~CSA0

~EMUBRK

MON_SEL0

16151413121110

1234567

MON_SEL0

MON_SEL1

MON_SEL2

MON_SEL1

0RWRUROD6HPLFRQGXFWRUV+RQJ.RQJ/LPLWHG

2 Dai King Street, Tai Po Industrial Estate, Tai Po, NT, Hong Kong.

9

SW DIP-8

8

VCCVDD

VSS

~RAS0

~CSA1 ~CSROM1

~IRQ5

PWMO

~IRQ1

TOUT/TIN

5

R41

330

LED2

GREEN LED

POWER

~EMU

~CSA1

~RAS0

~CSA0

~BOOTSTRAP

5

VCC

LED1

RED LED

HEART BEAT

R42

U5A

1 2

Q1810Q1911Q2012Q2113Q2214Q2315Q24

U4

IN19IN26RST

2

A1

C4

0.1u

330

MC74HC14D

1

VDD5VSS

3

4

OT17OT2

MC14521BD

VCC

4

3

Freescale Semiconductor, I

VCC

2

VCC

R43

BC847AWT1

Q1

1K

R44

100K

R45

33R

1

BZ1

CitiSound CHB-03E

-

+

D2

C7

0.1u

1

2

P2

GND

VEEVCC

2

TP1

Test Point - VCC

1

VCC XVEE

D1

C6

0.1u

220u

C5

+

4

3

2

1

Single Tone Generator

MISC

A A

For More Information On This Product,

Go to: www.freescale.com

B B

TONE_OUT

C C

P1

D D

1

ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005

Freescale Semiconductor, Inc.

nc...

EZADS20.DSN 2.0

M68EZ328ADS

B

Title

Size Document Number Rev

of

8

910Wednesday, January 05, 2000

7

Date: Sheet

6

5

8

7

0RWRUROD6HPLFRQGXFWRUV+RQJ.RQJ/LPLWHG

2 Dai King Street, Tai Po Industrial Estate, Tai Po, NT, Hong Kong.

6

D[0..15]

~OE

~DTACK

LACD

~EMUIRQ

5

D[0..15]

~UWE

A[0..26]

~CSA0

~CSB0

~RAS0

LLP

LD3

LD1

A[0..26]

~CAS0

D15

POD3

1 2

3 4

5 6

7 8

9 10

11 12

13 14

15 16

17 18

4

CLKO

D14 D13

D12 D11

3

CLKO

19 20

D10 D9

D8 D7

D6 D5

D4 D3

D2 D1

D0

POD2

~EMUIRQ

1 2

3 4

5 6

7 8

9 10

11 12

13 14

~RSTIN ~OE

~EMUCS ~UWE

~LWE ~DTACK

CONTRAST LACD

LCLK LLP

LFRM LD3

LCLK

~LWE

~RSTIN

~EMUCS

CONTRAST

Freescale Semiconductor, I

2

A15

POD1

15 16

17 18

19 20

1 2

3 4

5 6

7 8

9 10

11 12

13 14

~CSA0 ~CSA0

~CSA1 ~CSB0

~CSB1 ~CSC0

~CSC1 ~CSD0

~CSD1 A23

LD2 LD1

LD0

LD2

LD0

LFRM

A22 A21

~CSA1

~CSB1

~RAS1

~CAS1

~CSA0

POD4

15 16

17 18

19 20

1 2

3 4

5 6

7 8

9 10

11 12

13 14

15 16

17 18

19 20

A20 A19

A18 A17

A16

A14 A13

A12 A11

A10 A9

A8 A7

A6 A5

A4 A3

A2 A1

A0

~DTACK

4

3

2

1

Logic Analyzer Connectors

A A

For More Information On This Product,

Go to: www.freescale.com

B B

1

C C

D D

ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005

Freescale Semiconductor, Inc.

nc...

EZADS20.DSN 2.0

M68EZ328ADS

B

Title

Size Document Number Rev

of

8

10 10Wednesday, January 05, 2000

7

Date: Sheet

6

5

8

7

6

5

P4C

*C1*C2*C3*C4*C5*C6*C7*C8*C9*

D8D5D2

D11

D2D5D8

P4B

*B1*B2*B3*B4*B5*B6*B7*B8*B9*

D1D4D7

D10

D1D4D7

P4A

*A1*A2*A3*A4*A5*A6*A7*A8*A9*

D0D3D6D9D12

D0D3D6

C10*C11*C12*C13*C14*C15*C16*C17*C18*C19*C20*C21*C22*C23*C24*C25*C26*C27*C28*C29*C30*C31*C32

LD0

~CAS1

~RAS0

LCLK

LD3

~CSA1

D11

D10

D9

D14

D13

D12

~INT1

~IRQ1

~IRQ6

SPMCLK

TXD

LD3

LD0

LCLK

~IRQ1A9~IRQ6

~INT1

~CAS1

~CSA1

~RAS0

B10*B11*B12*B13*B14*B15*B16*B17*B18*B19*B20*B21*B22*B23*B24*B25*B26*B27*B28*B29*B30*B31*B32

~CSA0

~CSB1

~CAS0

PWMO

~CAS0

~CSA0

~CSB1

A10*A11*A12*A13*A14*A15*A16*A17*A18*A19*A20*A21*A22*A23*A24*A25*A26*A27*A28*A29*A30*A31*A32

~RAS1

D15

~CSB0

TOUT/TIN

D15

~CSB0

~RAS1

PWMO

TOUT/TIN

LD2

LD1

LD2

LD1

LLP

~INT0

LLP

~INT0

LACD

LFRM

LACD

LFRM

SPMCLK

~INT3

~IRQ3A2A5A8A11

SPMRXD

RXD

~INT3A8~IRQ3

SPMRXD

~INT2

~IRQ2

~DWEA1A4A7A10

SPMTXD

~INT2

~IRQ2

SPMTXD

CONTRAST

TXD

CONTRAST

~CTS

RXD

~CTS

~RTS

~DWE

~RTS

A0

CLKO

~IRQ5

A6

A3

A5

A2

A1A4A7

A12A9A6A3A0

VME 32x3 FEMALE

A15

A18

A21

~OE

~EMUIRQ

~EMUBRK

A12

A18

A15

A21

~OE

~EMUIRQ

~EMUBRK

VME 32x3 FEMALE

A14

A17

A20

A23

~EMUCS

~LWE

~RSTIN

A11

A23

A17

A14

A20

~LWE

~RSTIN

~EMUCS

VME 32x3 FEMALE

A13

A16

A19

A22

~DTACK

~UWE

~HIZ

A16

A19

A22

A13

A10

~HIZ

~UWE

~DTACK

0RWRUROD6HPLFRQGXFWRUV+RQJ.RQJ/LPLWHG

2 Dai King Street, Tai Po Industrial Estate, Tai Po, NT, Hong Kong.

VCC VCC VCC

4

~IRQ5

VCC VCC

~IRQ3

~IRQ1

~INT2

~INT0

LACD

LD3

~IRQ3

~IRQ1

~INT2

LACD

~INT0~INT1

7 8

~IRQ2

~INT3

~IRQ2

LD1

LD3

9 10

11 12

13 14

15 16

17 18

CONTRAST

LCLK LLP

LFRM

LD2

LCLK LLP

~INT3

~INT1

LFRM

CONTRAST

~IRQ5

P5

1 2

3 4

5 6

CLKO

~IRQ6

CLKO

~IRQ6

A18

A20

A22

~RTS

RXD

SPMTXD

SPMCLK

~EMUIRQ

~EMUCS

A18

A20

A22

VCCVCC

3

Freescale Semiconductor, I

2

1

P3

RXD

~RTS

SPMTXD

SPMCLK

~EMUIRQ

~EMUCS

1 2

3 4

5 6

7 8

9 10

11 12

13 14

15 16

17 18

A19

A21

A17

A23

~CTS

~HIZ

TXD

~DWE

SPMRXD

A21

A17

A23

A19

TXD

~CTS

~DWE

SPMRXD

19 20

~HIZ

HEADER 14X2

21 22

23 24

25 26

27 28

~EMUBRK

LD1

19 20

LD2

PWMO

LD0

PWMO

LD0

21 22

~CAS1

23 24

TOUT/TIN

25 26

27 28

HEADER 14X2

VCC VCC

4

~UWEA8A10

P7

VCC VCC

~RSTIN

~UWEA2A4A0A6A8A10

1 2

3 4

5 6

7 8

~LWEA9A3

A1A5A7

~OE

~DTACK

~OE

~LWE

~DTACK

~CSA1D5~RAS1

~CSB1

D15

~CAS1

~CSA1

D15

~CSB1

~CAS1

~RAS1

P6

1 2

3 4

5 6

7 8

9 10

~CSB0

~RAS0

~CSA0D4D14

~CAS0

D14

~CSB0

~CSA0

~CAS0

~RAS0

D3

D11D9D13

D7

D1

D3

D11

D9D7D5

D13

D1

19 20

D6

D6D0D2

21 22

D4

23 24

D2

25 26

27 28

HEADER 14X2

11 12

13 14

15 16

17 18

D12

D8D0D10

D8

D10

D12

A6A0A4

A2

9 10

11 12

13 14

A1A3A7

A14

A12

A16

A12

A14

A16

3

19 20

A11

A11A5A13

HEADER 14X2

21 22

23 24

25 26

27 28

A15

A13

A15

2

1

15 16

17 18

A9

Test pin & VME connector

For More Information On This Product,

A A

Go to: www.freescale.com

B B

C C

D D

Motorola M68EZ328ADS User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Section 1

General Information

Section 2

Quick Installation Guide

Section 3

Hardware Description and Board Operation

Comparison of M68EZ328ADS Version 1.x and 2.0

Programming On-board Flash Memory

Appendix A

Appendix B

Resistive Touch Panel Operation

Appendix C

Appendix D

Monitor Initialization Code

1.1 INTRODUCTION

1.2 FEATURES

1.3 RELATED DOCUMENTATION

1.4 TECHNICAL SUPPORT

2.1 OVERVIEW

2.2 EQUIPMENTS REQUIRED

2.3 INSTALLATION PROCEDURE

3.1 OVERVIEW

3.2 CONTROL SWITCHES

3.3 DIP SWITCHES

3.4 OPERATION MODES

3.5 LED INDICATORS

3.6 MEMORY

3.7 UART AND IRDA

3.8 DEBUG PORT

3.9 LCD AND TOUCH PANEL INTERFACE

3.10 SINGLE TONE GENERATOR

3.11 LOGIC ANALYZER INTERFACE

3.12 EXPANSION CONNECTORS

3.13 POWER SUPPLY

A.1 HARDWARE

A.2 SOFTW ARE

B.1 GENERAL CONCEPTS OF RESISTIVE PANELS

C.1 OVERVIEW

C.2 ELEMENTS FOR PROGRAMMING THE FLASH

C.3 METHOD

C.4 OFFSET ADDRESS OF ROM IMAGE

C.5 EXECUTING PROGRAM COMMAND SEQUENCE

D.1 INITIALIZATION CODE OF METROWERKS MONITOR (RESET.S)

D.2 INITIA LIZATION CODE OF SDS MONITOR (MONITOR.H)

E.1 M68EZ328ADS V2.0