µ MOTOROLA
Microprocessors User’s Manual
M68000
8-/16-/32-Bit
Ninth Edition
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©MOTOROLA INC., 1993
µ
TABLE OF CONTENTS
Paragraph Page
Number Title Number
Section 1
Overview
1.1 MC68000..................................................................................................... 1-1
1.2 MC68008..................................................................................................... 1-2
1.3 MC68010..................................................................................................... 1-2
1.4 MC68HC000................................................................................................ 1-2
1.5 MC68HC001................................................................................................ 1-3
1.6 MC68EC000................................................................................................ 1-3
Section 2
Introduction
2.1 Programmer's Model ................................................................................... 2-1
2.1.1 User's Programmer's Model .................................................................... 2-1
2.1.2 Supervisor Programmer's Model ............................................................. 2-2
2.1.3 Status Register........................................................................................ 2-3
2.2 Data Types and Addressing Modes ............................................................ 2-3
2.3 Data Organization In Registers................................................................... 2-5
2.3.1 Data Registers......................................................................................... 2-5
2.3.2 Address Registers ................................................................................... 2-6
2.4 Data Organization In Memory ..................................................................... 2-6
2.5 Instruction Set Summary............................................................................. 2-8
Section 3
Signal Description
3.1 Address Bus................................................................................................ 3-3
3.2 Data Bus...................................................................................................... 3-4
3.3 Asynchronous Bus Control.......................................................................... 3-4
3.4 Bus Arbitration Control ................................................................................ 3-5
3.5 Interrupt Control .......................................................................................... 3-6
3.6 System Control............................................................................................ 3-7
3.7 M6800 Peripheral Control ........................................................................... 3-8
3.8 Processor Function Codes.......................................................................... 3-8
3.9 Clock ........................................................................................................... 3-9
3.10 Power Supply.............................................................................................. 3-9
3.11 Signal Summary......................................................................................... 3-10
MOTOROLA M68000 USER’S MANUAL vii
TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
Section 4
8-Bit Bus Operations
4.1 Data Transfer Operations............................................................................. 4-1
4.1.1 Read Operations ...................................................................................... 4-1
4.1.2 Write Cycle ............................................................................................... 4-3
4.1.3 Read-Modify-Write Cycle.......................................................................... 4-5
4.2 Other Bus Operations............................................................................... 4-8
Section 5
16-Bit Bus Operations
5.1 Data Transfer Operations............................................................................ 5-1
5.1.1 Read Operations ..................................................................................... 5-1
5.1.2 Write Cycle .............................................................................................. 5-4
5.1.3 Read-Modify-Write Cycle......................................................................... 5-7
5.1.4 CPU Space Cycle.................................................................................... 5-9
5.2 Bus Arbitration .......................................................................................... 5-11
5.2.1 Requesting The Bus.............................................................................. 5-14
5.2.2 Receiving The Bus Grant ...................................................................... 5-15
5.2.3 Acknowledgment of Mastership (3-Wire Arbitration Only)..................... 5-15
5.3 Bus Arbitration Control.............................................................................. 5-15
5.4 Bus Error and Halt Operation.................................................................... 5-23
5.4.1 Bus Error Operation .............................................................................. 5-24
5.4.2 Retrying The Bus Cycle......................................................................... 5-26
5.4.3 Halt Operation ....................................................................................... 5-27
5.4.4 Double Bus Fault................................................................................... 5-28
5.5 Reset Operation........................................................................................ 5-29
5.6 The Relationship of DTACK, BERR, and HALT ......................................... 5-30
5.7 Asynchronous Operation .......................................................................... 5-32
5.8 Synchronous Operation ............................................................................ 5-35
Section 6
Exception Processing
6.1 Privilege Modes............................................................................................ 6-1
6.1.1 Supervisor Mode ...................................................................................... 6-2
6.1.2 User Mode................................................................................................ 6-2
6.1.3 Privilege Mode Changes .......................................................................... 6-2
6.1.4 Reference Classification........................................................................... 6-3
6.2 Exception Processing................................................................................... 6-4
6.2.1 Exception Vectors .................................................................................... 6-4
6.2.2 Kinds Of Exceptions................................................................................. 6-5
6.2.3 Multiple Exceptions................................................................................... 6-8
viii M68000 USER’S MANUAL MOTOROLA
TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
Section 6
Exception Processing
6.2.4 Exception Stack Frames.......................................................................... 6-9
6.2.5 Exception Processing Sequence............................................................ 6-11
6.3 Processing of Specific Exceptions ............................................................. 6-11
6.3.1 Reset ...................................................................................................... 6-11
6.3.2 Interrupts ................................................................................................ 6-12
6.3.3 Uninitialized Interrupt.............................................................................. 6-13
6.3.4 Spurious Interrupt ................................................................................... 6-13
6.3.5 Instruction Traps..................................................................................... 6-13
6.3.6 Illegal and Unimplemented Instructions.................................................. 6-14
6.3.7 Privilege Violations ................................................................................. 6-15
6.3.8 Tracing.................................................................................................... 6-15
6.3.9 Bus Errors............................................................................................... 6-16
6.3.9.1 Bus Error............................................................................................. 6-16
6.3.9.2 Bus Error (MC68010) .......................................................................... 6-17
6.3.10 Address Error ......................................................................................... 6-19
6.4 Return From Exception (MC68010) ........................................................... 6-20
Section 7
8-Bit Instruction Timing
7.1 Operand Effective Address Calculation Times............................................ 7-1
7.2 Move Instruction Execution Times .............................................................. 7-2
7.3 Standard Instruction Execution Times......................................................... 7-3
7.4 Immediate Instruction Execution Times ...................................................... 7-4
7.5 Single Operand Instruction Execution Times.............................................. 7-5
7.6 Shift/Rotate Instruction Execution Times .................................................... 7-6
7.7 Bit Manipulation Instruction Execution Times ............................................. 7-7
7.8 Conditional Instruction Execution Times ..................................................... 7-7
7.9 JMP, JSR, LEA, PEA, and MOVEM Instruction Execution Times............... 7-8
7.10 Multiprecision Instruction Execution Times................................................. 7-8
7.11 Miscellaneous Instruction Execution Times ................................................ 7-9
7.12 Exception Processing Instruction Execution Times ................................... 7-10
MOTOROLA M68000 USER’S MANUAL ix
TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
Section 8
16-Bit Instruction Timing
8.1 Operand Effective Address Calculation Times ........................................... 8-1
8.2 Move Instruction Execution Times.............................................................. 8-2
8.3 Standard Instruction Execution Times ........................................................ 8-3
8.4 Immediate Instruction Execution Times ...................................................... 8-4
8.5 Single Operand Instruction Execution Times.............................................. 8-5
8.6 Shift/Rotate Instruction Execution Times .................................................... 8-6
8.7 Bit Manipulation Instruction Execution Times ............................................. 8-7
8.8 Conditional Instruction Execution Times..................................................... 8-7
8.9 JMP, JSR, LEA, PEA, and MOVEM Instruction Execution Times .............. 8-8
8.10 Multiprecision Instruction Execution Times................................................. 8-8
8.11 Miscellaneous Instruction Execution Times ................................................ 8-9
8.12 Exception Processing Instruction Execution Times .................................. 8-10
Section 9
MC68010 Instruction Timing
9.1 Operand Effective Address Calculation Times ........................................... 9-2
9.2 Move Instruction Execution Times.............................................................. 9-2
9.3 Standard Instruction Execution Times ........................................................ 9-4
9.4 Immediate Instruction Execution Times ...................................................... 9-6
9.5 Single Operand Instruction Execution Times.............................................. 9-6
9.6 Shift/Rotate Instruction Execution Times .................................................... 9-8
9.7 Bit Manipulation Instruction Execution Times ............................................. 9-9
9.8 Conditional Instruction Execution Times..................................................... 9-9
9.9 JMP, JSR, LEA, PEA, and MOVEM Instruction Execution Times ............ 9-10
9.10 Multiprecision Instruction Execution Times............................................... 9-11
9.11 Miscellaneous Instruction Execution Times .............................................. 9-11
9.12 Exception Processing Instruction Execution Times .................................. 9-13
Section 10
Electrical and Thermal Characteristics
10.1 Maximum Ratings ..................................................................................... 10-1
10.2 Thermal Characteristics ............................................................................ 10-1
10.3 Power Considerations............................................................................... 10-2
10.4 CMOS Considerations .............................................................................. 10-4
10.5 AC Electrical Specifications Definitions..................................................... 10-5
10.6 MC68000/68008/68010 DC Electrical Characteristics.............................. 10-7
10.7 DC Electrical Characteristics .................................................................... 10-8
10.8 AC Electrical Specifications—Clock Timing.............................................. 10-8
x M68000 USER’S MANUAL MOTOROLA
TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
Section 10
Electrical and Thermal Characteristics
10.9 MC68008 AC Electrical Specifications—Clock Timing ............................. 10-9
10.10 AC Electrical Specifications—Read and Write Cycles ............................ 10-10
10.11 AC Electrical Specifications—MC68000 To M6800 Peripheral............... 10-15
10.12 AC Electrical Specifications—Bus Arbitration ......................................... 10-17
10.13 MC68EC000 DC Electrical Spec ifications.............................................. 10-23
10.14 MC68EC000 AC Electrical Specifications—Read and Write .................. 10-24
10.15 MC68EC000 AC Electrical Specifications—Bus Arbitration.................... 10-28
Section 11
Ordering Information and Mechanical Data
11.1 Pin Assignments........................................................................................ 11-1
11.2 Package Dimensions ................................................................................ 11-7
Appendix A
MC68010 Loop Mode Operation
Appendix B
M6800 Peripheral Interface
B.1 Data Transfer Operation............................................................................. B-1
B.2 Interrupt Interface Operation ...................................................................... B-4
MOTOROLA M68000 USER’S MANUAL xi
LIST OF ILLUSTRATIONS
Figure Page
Number Title Number
2-1 User Programmer's Model ................................................................................... 2-2
2-2 Supervisor Programmer's Model Supplement ..................................................... 2-2
2-3 Supervisor Programmer's Model Supplement (MC68010) .................................. 2-3
2-4 Status Register .................................................................................................... 2-3
2-5 Word Organization In Memory............................................................................. 2-6
2-6 Data Organization In Memory .............................................................................. 2-7
2-7 Memory Data Organization (MC68008) ............................................................... 2-3
3-1 Input and Output Signals (MC68000, MC68HC000, MC68010).......................... 3-1
3-2 Input and Output Signals ( MC68HC001) ............................................................ 3-2
3-3 Input and Output Signals (MC68EC000) ............................................................. 3-2
3-4 Input and Output Signals (MC68008 48-Pin Version).......................................... 3-3
3-5 Input and Output Signals (MC68008 52-Pin Version).......................................... 3-3
4-1 Byte Read-Cycle Flowchart.................................................................................. 4-2
4-2 Read and Write-Cycle Timing Diagram................................................................ 4-2
4-3 Byte Write-Cycle Flowchart.................................................................................. 4-4
4-4 Write-Cycle Timing Diagram ................................................................................ 4-4
4-5 Read-Modify-Write Cycle Flowchart .................................................................... 4-6
4-6 Read-Modify-Write Cycle Timing Diagram........................................................... 4-7
5-1 Word Read-Cycle Flowchart ................................................................................ 5-2
5-2 Byte Read-Cycle Flowchart.................................................................................. 5-2
5-3 Read and Write-Cycle Timing Diagram................................................................ 5-3
5-4 Word and Byte Read-Cycle Timing Diagram ....................................................... 5-3
5-5 Word Write-Cycle Flowchart ................................................................................ 5-5
5-6 Byte Write-Cycle Flowchart.................................................................................. 5-5
5-7 Word and Byte Write-Cycle Timing Diagram ....................................................... 5-6
5-8 Read-Modify-Write Cycle Flowchart .................................................................... 5-7
5-9 Read-Modify-Write Cycle Timing Diagram........................................................... 5-8
5-10 CPU Space Address Encoding ............................................................................ 5-9
5-11 Interrupt Acknowledge Cycle Timing Diagram................................................... 5-10
5-12 Breakpoint Acknowledge Cycle Timing Diagram ............................................... 5-11
5-13 3-Wire Bus Arbitration Flowchart
(NA to 48-Pin MC68008 and MC68EC000 ........................................................ 5-12
5-14 2-Wire Bus Arbitration Cycle Flowchart ............................................................. 5-13
xii M68000 USER’S MANUAL MOTOROLA
LIST OF ILLUSTRATIONS (Continued)
Figure Page
Number Title Number
5-15 3-Wire Bus Arbitration Timing Diagram
(NA to 48-Pin MC68008 and MC68EC000 ........................................................ 5-13
5-16 2-Wire Bus Arbitration Timing Diagram.............................................................. 5-14
5-17 External Asynchronous Signal Synchronization................................................. 5-16
5-18 Bus Arbitration Unit State Diagrams................................................................... 5-17
5-19 3-Wire Bus Arbitration Timing Diagram—Processor Active ............................... 5-18
5-20 3-Wire Bus Arbitration Timing Diagram—Bus Active ......................................... 5-19
5-21 3-Wire Bus Arbitration Timing Diagram—Special Case ..................................... 5-20
5-22 2-Wire Bus Arbitration Timing Diagram—Processor Active ............................... 5-21
5-23 2-Wire Bus Arbitration Timing Diagram—Bus Active ......................................... 5-22
5-24 2-Wire Bus Arbitration Timing Diagram—Special Case ..................................... 5-23
5-25 Bus Error Timing Diagram.................................................................................. 5-24
5-26 Delayed Bus Error Timing Diagram (MC68010)................................................. 5-25
5-27 Retry Bus Cycle Timing Diagram ....................................................................... 5-26
5-28 Delayed Retry Bus Cycle Timing Diagram......................................................... 5-27
5-29 Halt Operation Timing Diagram.......................................................................... 5-28
5-30 Reset Operation Timing Diagram....................................................................... 5-29
5-31 Fully Asynchronous Read Cycle ........................................................................ 5-32
5-32 Fully Asynchronous Write Cycle......................................................................... 5-33
5-33 Pseudo-Asynchronous Read Cycle ................................................................... 5-34
5-34 Pseudo-Asynchronous Write Cycle.................................................................... 5-35
5-35 Synchronous Read Cycle................................................................................... 5-37
5-36 Synchronous Write Cycle................................................................................... 5-38
5-37 Input Synchronizers ........................................................................................... 5-38
6-1 Exception Vector Format...................................................................................... 6-4
6-2 Peripheral Vector Number Format ....................................................................... 6-5
6-3 Address Translated from 8-Bit Vector Number ................................................... 6-5
6-4 Exception Vector Address Calculation (MC68010).............................................. 6-5
6-5 Group 1 and 2 Exception Stack Frame.............................................................. 6-10
6-6 MC68010 Stack Frame ...................................................................................... 6-10
6-7 Supervisor Stack Order for Bus or Address Error Exception ............................. 6-17
6-8 Exception Stack Order (Bus and Address Error) ............................................... 6-18
6-9 Special Status Word Format .............................................................................. 6-19
10-1 MC68000 Power Dissipation (PD) vs Ambient Temperature (TA) ..................... 10-3
10-2 Drive Levels and Test Points for AC Specifications ........................................... 10-6
10-3 Clock Input Timing Diagram ............................................................................... 10-9
10-4 Read Cycle Timing Diagram ............................................................................ 10-13
10-5 Write Cycle Timing Diagram............................................................................. 10-14
10-6 MC68000 to M6800 Peripheral Timing Diagram (Best Case).......................... 10-16
MOTOROLA M68000 USER’S MANUAL xiii
LIST OF ILLUSTRATIONS (Concluded)
Figure Page
Number Title Number
10-7 Bus Arbitration Timing...................................................................................... 10-18
10-8 Bus Arbitration Timing...................................................................................... 10-19
10-9 Bus Arbitration Timing—Idle Bus Case............................................................ 10-20
10-10 Bus Arbitration Timing—Active Bus Case........................................................ 10-21
10-11 Bus Arbitration Timing—Multiple Bus Request ................................................ 10-22
10-12 MC68EC000 Read Cycle Timing Diagram ...................................................... 10-26
10-13 MC68EC000 Write Cycle Timing Diagram....................................................... 10-27
10-14 MC68EC000 Bus Arbitration Timing Diagram ................................................. 10-29
11-1 64-Pin Dual In Line ............................................................................................ 11-2
11-2 68-Lead Pin Grid Array ...................................................................................... 11-3
11-3 68-Lead Quad Pack ........................................................................................... 11-4
11-4 52-Lead Quad Pack ........................................................................................... 11-5
11-5 48-Pin Dual In Line ............................................................................................ 11-6
11-6 64-Lead Quad Flat Pack.................................................................................... 11-7
11-7 Case 740-03—L Suffix....................................................................................... 11-8
11-8 Case 767-02—P Suffix ...................................................................................... 11-9
11-9 Case 746-01—LC Suffix .................................................................................. 11-10
11-10 Case — Suffix ...................................................................................................... 11-
11-11 Case 765A-05—RC Suffix ............................................................................... 11-12
11-12 Case 778-02—FN Suffix.................................................................................. 11-13
11-13 Case 779-02—FN Suffix.................................................................................. 11-14
11-14 Case 847-01—FC Suffix.................................................................................. 11-15
11-15 Case 840B-01—FU Suffix................................................................................ 11-16
A-1 DBcc Loop Mode Program Example................................................................... A-1
B-1 M6800 Data Transfer Flowchart ......................................................................... B-1
B-2 Example External VMA Circuit............................................................................ B-2
B-3 External VMA Timing .......................................................................................... B-2
B-4 M6800 Peripheral Timing—Best Case................................................................ B-3
B-5 M6800 Peripheral Timing—Worst Case ............................................................. B-3
B-6 Autovector Operation Timing Diagram................................................................ B-5
xiv M68000 USER’S MANUAL MOTOROLA
LIST OF TABLES
Table Page
Number Title Number
2-1 Data Addressing Modes....................................................................................... 2-4
2-2 Instruction Set Summary.................................................................................... 2-11
3-1 Data Strobe Control of Data Bus.......................................................................... 3-5
3-2 Data Strobe Control of Data Bus (MC68008)....................................................... 3-5
3-3 Function Code Output .......................................................................................... 3-9
3-4 Signal Summary................................................................................................. 3-10
5-1 DTACK, BERR, and HALT Assertion Results ..................................................... 5-31
6-1 Reference Classification....................................................................................... 6-3
6-2 Exception Vector Assignment .............................................................................. 6-7
6-3 Exception Grouping and Priority........................................................................... 6-9
6-4 MC68010 Format Code...................................................................................... 6-11
7-1 Effective Address Calculation Times.................................................................... 7-2
7-2 Move Byte Instruction Execution Times ............................................................... 7-2
7-3 Move Word Instruction Execution Times.............................................................. 7-3
7-4 Move Long Instruction Execution Times .............................................................. 7-3
7-5 Standard Instruction Execution Times.................................................................. 7-4
7-6 Immediate Instruction Execution Times ............................................................... 7-5
7-7 Single Operand Instruction Execution Times....................................................... 7-6
7-8 Shift/Rotate Instruction Execution Times ............................................................. 7-6
7-9 Bit Manipulation Instruction Execution Times ...................................................... 7-7
7-10 Conditional Instruction Execution Times .............................................................. 7-7
7-11 JMP, JSR, LEA, PEA, and MOVEM Instruction Execution Times........................ 7-8
7-12 Multiprecision Instruction Execution Times.......................................................... 7-9
7-13 Miscellaneous Instruction Execution Times ....................................................... 7-10
7-14 Move Peripheral Instruction Execution Times.................................................... 7-10
7-15 Exception Processing Instruction Execution Times ........................................... 7-11
8-1 Effective Address Calculation Times.................................................................... 8-2
8-2 Move Byte Instruction Execution Times ............................................................... 8-2
8-3 Move Word Instruction Execution Times.............................................................. 8-3
8-4 Move Long Instruction Execution Times .............................................................. 8-3
MOTOROLA M68000 USER’S MANUAL xv
LIST OF TABLES (Concluded)
Table Page
Number Title Number
8-5 Standard Instruction Execution Times ................................................................. 8-4
8-6 Immediate Instruction Execution Times ............................................................... 8-5
8-7 Single Operand Instruction Execution Times....................................................... 8-6
8-8 Shift/Rotate Instruction Execution Times ............................................................. 8-6
8-9 Bit Manipulation Instruction Execution Times ...................................................... 8-7
8-10 Conditional Instruction Execution Times.............................................................. 8-7
8-11 JMP, JSR, LEA, PEA, and MOVEM Instruction Execution Times ....................... 8-8
8-12 Multiprecision Instruction Execution Times.......................................................... 8-9
8-13 Miscellaneous Instruction Execution Times ....................................................... 8-10
8-14 Move Peripheral Instruction Execution Times.................................................... 8-10
8-15 Exception Processing Instruction Execution Times ........................................... 8-11
9-1 Effective Address Calculation Times ................................................................... 9-2
9-2 Move Byte and Word Instruction Execution Times .............................................. 9-3
9-3 Move Byte and Word Instruction Loop Mode Execution Times ........................... 9-3
9-4 Move Long Instruction Execution Times.............................................................. 9-4
9-5 Move Long Instruction Loop Mode Execution Times ........................................... 9-4
9-6 Standard Instruction Execution Times ................................................................. 9-5
9-7 Standard Instruction Loop Mode Execution Times .............................................. 9-5
9-8 Immediate Instruction Execution Times ............................................................... 9-6
9-9 Single Operand Instruction Execution Times....................................................... 9-7
9-10 Clear Instruction Execution Times ....................................................................... 9-7
9-11 Single Operand Instruction Loop Mode Execution Times.................................... 9-8
9-12 Shift/Rotate Instruction Execution Times ............................................................. 9-8
9-13 Shift/Rotate Instruction Loop Mode Execution Times .......................................... 9-9
9-14 Bit Manipulation Instruction Execution Times ...................................................... 9-9
9-15 Conditional Instruction Execution Times............................................................ 9-10
9-16 JMP, JSR, LEA, PEA, and MOVEM Instruction Execution Times ..................... 9-10
9-17 Multiprecision Instruction Execution Times........................................................ 9-11
9-18 Miscellaneous Instruction Execution Times ....................................................... 9-12
9-19 Exception Processing Instruction Execution Times ........................................... 9-13
10-1 Power Dissipation and Junction Temperature vs Temperature
(θJC = θJA) ........................................................................................................ 10-4
10-2 Power Dissipation and Junction Temperature vs Temperature
(θJC = θJC)........................................................................................................ 10-4
A-1 MC68010 Loop Mode Instructions...................................................................... A-3
xvi M68000 USER’S MANUAL MOTOROLA
SECTION 1
OVERVIEW
This manual includes hardware details and programming information for the MC68000,
the MC68HC000, the MC68HC001, the MC68008, the MC68010, and the MC68EC000.
For ease of reading, the name M68000 MPUs will be used when referring to all
processors. Refer to M68000PM/AD,
detailed information on the MC68000 instruction set.
The six microprocessors are very similar. They all contain the following features
• 16 32-Bit Data and Address Registers
• 16-Mbyte Direct Addressing Range
• Program Counter
• 6 Powerful Instruction Types
• Operations on Five Main Data Types
• Memory-Mapped Input/Output (I/O)
• 14 Addressing Modes
The following processors contain additional features:
M68000 Programmer's Reference Manual
, for
• MC68010
—Virtual Memory/Machine Support
—High-Performance Looping Instructions
• MC68HC001/MC68EC000
—Statically Selectable 8- or 16-Bit Data Bus
• MC68HC000/MC68EC000/MC68HC001
—Low-Power
All the processors are basically the same with the exception of the MC68008. The
MC68008 differs from the others in that the data bus size is eight bits, and the address
range is smaller. The MC68010 has a few additional instructions and instructions that
operate differently than the corresponding instructions of the other devices.
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL 1-1
1.1 MC68000
The MC68000 is the first implementation of the M68000 16/-32 bit microprocessor
architecture. The MC68000 has a 16-bit data bus and 24-bit address bus while the full
architecture provides for 32-bit address and data buses. It is completely code-compatible
with the MC68008 8-bit data bus implementation of the M68000 and is upward code
compatible with the MC68010 virtual extensions and the MC68020 32-bit implementation
of the architecture. Any user-mode programs using the MC68000 instruction set will run
unchanged on the MC68008, MC68010, MC68020, MC68030, and MC68040. This is
possible because the user programming model is identical for all processors and the
instruction sets are proper subsets of the complete architecture.
1.2 MC68008
The MC68008 is a member of the M68000 family of advanced microprocessors. This
device allows the design of cost-effective systems using 8-bit data buses while providing
the benefits of a 32-bit microprocessor architecture. The performance of the MC68008 is
greater than any 8-bit microprocessor and superior to several 16-bit microprocessors.
The MC68008 is available as a 48-pin dual-in-line package (plastic or ceramic) and 52-pin
plastic leaded chip carrier. The additional four pins of the 52-pin package allow for
additional signals: A20, A21, BGACK, and IPL2. The 48-pin version supports a 20-bit
address that provides a 1-Mbyte address space; the 52-pin version supports a 22-bit
address that extends the address space to 4 Mbytes. The 48-pin MC68008 contains a
simple two-wire arbitration circuit; the 52-pin MC68008 contains a full three-wire MC68000
bus arbitration control. Both versions are designed to work with daisy-chained networks,
priority encoded networks, or a combination of these techniques.
A system implementation based on an 8-bit data bus reduces system cost in comparison
to 16-bit systems due to a more effective use of components and byte-wide memories and
peripherals. In addition, the nonmultiplexed address and data buses eliminate the need for
external demultiplexers, further simplifying the system.
The large nonsegmented linear address space of the MC68008 allows large modular
programs to be developed and executed efficiently. A large linear address space allows
program segment sizes to be determined by the application rather than forcing the
designer to adopt an arbitrary segment size without regard to the application's individual
requirements.
1.3 MC68010
The MC68010 utilizes VLSI technology and is a fully implemented 16-bit microprocessor
with 32-bit registers, a rich basic instruction set, and versatile addressing modes. The
vector base register (VBR) allows the vector table to be dynamically relocated
1-2 M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL MOTOROLA
1.4 MC68HC000
The primary benefit of the MC68HC000 is reduced power consumption. The device
dissipates an order of magnitude less power than the HMOS MC68000.
The MC68HC000 is an implementation of the M68000 16/-32 bit microprocessor
architecture. The MC68HC000 has a 16-bit data bus implementation of the MC68000 and
is upward code-compatible with the MC68010 virtual extensions and the MC68020 32-bit
implementation of the architecture.
1.5 MC68HC001
The MC68HC001 provides a functional extension to the MC68HC000 HCMOS 16-/32-bit
microprocessor with the addition of statically selectable 8- or 16-bit data bus operation.
The MC68HC001 is object-code compatible with the MC68HC000, and code written for
the MC68HC001 can be migrated without modification to any member of the M68000
Family.
1.6 MC68EC000
The MC68EC000 is an economical high-performance embedded controller designed to
suit the needs of the cost-sensitive embedded controller market. The HCMOS
MC68EC000 has an internal 32-bit architecture that is supported by a statically selectable
8- or 16-bit data bus. This architecture provides a fast and efficient processing device that
can satisfy the requirements of sophisticated applications based on high-level languages.
The MC68EC000 is object-code compatible with the MC68000, and code written for the
MC68EC000 can be migrated without modification to any member of the M68000 Family.
The MC68EC000 brings the performance level of the M68000 Family to cost levels
previously associated with 8-bit microprocessors. The MC68EC000 benefits from the rich
M68000 instruction set and its related high code density with low memory bandwidth
requirements.
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL 1-3
SECTION 2
INTRODUCTION
The section provide a brief introduction to the M68000 microprocessors (MPUs).
Detailed information on the programming model, data types, addressing modes, data
organization and instruction set can be found in M68000PM/AD,
Reference Manual
except that the MC68000 can directly access 16 Mbytes (24-bit address) and the
MC68008 can directly access 1 Mbyte (20-bit address on 48-pin version or 22-bit
address on 52-pin version). The MC68010, which also uses a 24-bit address, has much
in common with the other devices; however, it supports additional instructions and
registers and provides full virtual machine/memory capability. Unless noted, all
information pertains to all the M68000 MPUs.
. All the processors are identical from the programmer's viewpoint,
2.1 PROGRAMMER'S MODEL
All the microprocessors executes instructions in one of two modes—user mode or
supervisor mode. The user mode provides the execution environment for the majority of
application programs. The supervisor mode, which allows some additional instructions
and privileges, is used by the operating system and other system software.
M68000 Programmer's
2.1.1 User' Programmer's Model
The user programmer's model (see Figure 2-1) is common to all M68000 MPUs. The
user programmer's model, contains 16, 32-bit, general-purpose registers (D0–D7, A0–
A7), a 32-bit program counter, and an 8-bit condition code register. The first eight
registers (D0–D7) are used as data registers for byte (8-bit), word (16-bit), and long-word
(32-bit) operations. The second set of seven registers (A0–A6) and the user stack pointer
(USP) can be used as software stack pointers and base address registers. In addition,
the address registers can be used for word and long-word operations. All of the 16
registers can be used as index registers.
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSOR USER’S MANUAL 2-1
31 16 15 8 7 0
D0
D1
D2
D3
D4
D5
D6
D7
EIGHT
DATA
REGISTERS
31 16 15
31
70
0
A0
A1
A2
SEVEN
A3
ADDRESS
REGISTERS
A4
A5
A6
A7
USER STACK
(USP) POINTER
0
PROGRAM
PC
COUNTER
STATUS
CCR
REGISTER
Figure 2-1. User Programmer's Model
(MC68000/MC68HC000/MC68008/MC68010)
2.1.2 Supervisor Programmer's Model
The supervisor programmer's model consists of supplementary registers used in the
supervisor mode. The M68000 MPUs contain identical supervisor mode register
resources, which are shown in Figure 2-2, including the status register (high-order byte)
and the supervisor stack pointer (SSP/A7').
31 16 15 0
15 8 7 0
CCR
A7'
SUPERVISOR STACK
(SSP)
POINTER
STATUS REGISTER
SR
Figure 2-2. Supervisor Programmer's Model Supplement
The supervisor programmer's model supplement of the MC68010 is shown in Figure 2-
3. In addition to the supervisor stack pointer and status register, it includes the vector
base register (VRB) and the alternate function code registers (AFC).The VBR is used to
determine the location of the exception vector table in memory to support multiple vector
2-2 M68000 8-/16-/32-BIT MICROPROCESSOR USER’S MANUAL MOTOROLA
tables. The SFC and DFC registers allow the supervisor to access user data space or
emulate CPU space cycles.
31 16 15 0
15 8 7 0
CCR
31 0
20
A7'
SUPERVISOR STACK
(SSP)
POINTER
SR STATUS REGISTER
VBR VECTOR BASE REGISTER
SFC
ALTERNATE FUNCTION
CODE REGISTERS
DFC
Figure 2-3. Supervisor Programmer's Model Supplement
(MC68010)
2.1.3 Status Register
The status register (SR),contains the interrupt mask (eight levels available) and the
following condition codes: overflow (V), zero (Z), negative (N), carry (C), and extend (X).
Additional status bits indicate that the processor is in the trace (T) mode and/or in the
supervisor (S) state (see Figure 2-4). Bits 5, 6, 7, 11, 12, and 14 are undefined and
reserved for future expansion
SYSTEM BYTE USER BYTE
15 13 10 8 4 0
III
210
XNZVC
TRACE MODE
SUPERVISOR
STATE
INTERRUPT
MASK
S
T
Figure 2-4. Status Register
2.2 DATA TYPES AND ADDRESSING MODES
The five basic data types supported are as follows:
1. Bits
2. Binary-Coded-Decimal (BCD) Digits (4 Bits)
3. Bytes (8 Bits)
4. Words (16 Bits)
EXTEND
NEGATIVE
ZERO
OVERFLOW
CARRY
CONDITION
CODES
5. Long Words (32 Bits)
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSOR USER’S MANUAL 2-3
In addition, operations on other data types, such as memory addresses, status word
data, etc., are provided in the instruction set.
The 14 flexible addressing modes, shown in Table 2-1, include six basic types:
1. Register Direct
2. Register Indirect
3. Absolute
4. Immediate
5. Program Counter Relative
6. Implied
The register indirect addressing modes provide postincrementing, predecrementing,
offsetting, and indexing capabilities. The program counter relative mode also supports
indexing and offsetting. For detail information on addressing modes refer to
M68000PM/AD,
M68000 Programmer Reference Manual
.
2-4 M68000 8-/16-/32-BIT MICROPROCESSOR USER’S MANUAL MOTOROLA
Table 2-1. Data Addressing Modes
Mode Generation Syntax
Register Direct Addressing
Data Register Direct
Address Register Direct
Absolute Data Addressing
Absolute Short
Absolute Long
Program Counter Relative
Addressing
Relative with Offset
Relative with Index and Offset
Register Indirect Addressing
Register Indirect
Postincrement Register Indirect
Predecrement Register Indirect
Register Indirect with Offset
Indexed Register Indirect with Offset
Immediate Data Addressing
Immediate
Quick Immediate
Implied Addressing
Implied Register EA = SR, USP, SSP, PC,
NOTES: 1. The VBR, SFC, and DFC apply to the MC68010 only
EA = Effective Address
Dn = Data Register
An = Address Register
( ) = Contents of
PC = Program Counter
d8= 8-Bit Offset (Displacement)
d16= 16-Bit Offset (Displacement)
N = 1 for byte, 2 for word, and 4 for long word. If An is the stack pointer and
1
the operand size is byte, N = 2 to keep the stack pointer on a word boundary.
¯ = Replaces
Xn = Address or Data Register used as Index Register
SR = Status Register
USP = User Stack Pointer
SSP = Supervisor Stack Pointer
CP = Program Counter
VBR = Vector Base Register
EA=Dn
EA=An
EA = (Next Word)
EA = (Next Two Words)
EA = (PC)+d
EA = (PC)+d
EA = (An)
EA = (An), An ← An+N
An
¯ An–N, EA=(An)
EA = (An)+d
EA = (An)+(Xn)+d
DATA = Next Word(s)
Inherent Data
16
8
16
VBR, SFC, DFC
Dn
An
(xxx).W
(xxx).L
(d16,PC)
(d8,PC,Xn)
(An)
(An)+
-(An)
(d16,An)
8
(d8,An,Xn)
#<data>
SR,USP,SSP,PC,
VBR, SFC,DFC
2.3 DATA ORGANIZATION IN REGISTERS
The eight data registers support data operands of 1, 8, 16, or 32 bits. The seven address
registers and the active stack pointer support address operands of 32 bits.
2.3.1 Data Registers
Each data register is 32 bits wide. Byte operands occupy the low-order 8 bits, word
operands the low-order 16 bits, and long-word operands, the entire 32 bits. The least
significant bit is addressed as bit zero; the most significant bit is addressed as bit 31.
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSOR USER’S MANUAL 2-5
When a data register is used as either a source or a destination operand, only the
appropriate low-order portion is changed; the remaining high-order portion is neither
used nor changed.
2.3.2 Address Registers
Each address register (and the stack pointer) is 32 bits wide and holds a full, 32-bit
address. Address registers do not support byte-sized operands. Therefore, when an
address register is used as a source operand, either the low-order word or the entire
long-word operand is used, depending upon the operation size. When an address
register is used as the destination operand, the entire register is affected, regardless of
the operation size. If the operation size is word, operands are sign-extended to 32 bits
before the operation is performed.
2.4 DATA ORGANIZATION IN MEMORY
Bytes are individually addressable. As shown in Figure 2-5, the high-order byte of a
word has the same address as the word. The low-order byte has an odd address, one
count higher. Instructions and multibyte data are accessed only on word (even byte)
boundaries. If a long-word operand is located at address n (n even), then the second
word of that operand is located at address n+2.
1514131211109876543210
ADDRESS
$000000
$000002
$FFFFFE
BYTE 000000 BYTE 000001
BYTE 000002
BYTE FFFFFE
WORD 0
WORD 1
BYTE 000003
WORD 7FFFFF
BYTE FFFFFE
Figure 2-5. Word Organization in Memory
The data types supported by the M68000 MPUs are bit data, integer data of 8, 16, and
32 bits, 32-bit addresses, and binary-coded-decimal data. Each data type is stored in
memory as shown in Figure 2-6. The numbers indicate the order of accessing the data
from the processor. For the MC68008 with its 8-bit bus, the appearance of data in
memory is identical to the all the M68000 MPUs. The organization of data in the memory
of the MC68008 is shown in Figure 2-7.
2-6 M68000 8-/16-/32-BIT MICROPROCESSOR USER’S MANUAL MOTOROLA
BIT DATA
1 BYTE = 8 BITS
76543210
INTEGER DATA
1 BYTE = 8 BITS
1514131211109876543210
MSB
1514131211109876543210
BYTE 0
BYTE 2
LSB
1 WORD = 16 BITS
BYTE 1
BYTE 3
WORD 0
WORD 1
WORD 2
EVEN BYTE ODD BYTE
76 543210
1 LONG WORD = 32 BITS
1514131211109876543210
MSB
LONG WORD 0
LONG WORD 1
LONG WORD 2
1 ADDRESS = 32 BITS
1514131211109876543210
MSB
ADDRESS 0
76 543210
HIGH ORDER
LOW ORDER
ADDRESSES
HIGH ORDER
LOW ORDER
LSBMSB
LSB
LSB
ADDRESS 1
ADDRESS 2
MSB = MOST SIGNIFICANT BIT
LSB = LEAST SIGNIFICANT BIT
2 BINARY-CODED-DECIMAL DIGITS = 1 BYTE
1514131211109876543210
MSD
MSD = MOST SIGNIFICANT DIGIT
LSD = LEAST SIGNIFICANT DIGIT
BCD 0
BCD 4
BCD 1
BCD 5
DECIMAL DATA
LSD
BCD 2
BCD 6
BCD 3
BCD 7
Figure 2-6. Data Organization in Memory
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSOR USER’S MANUAL 2-7
BIT DATA 1 BYTE = 8 BITS
76543210
INTEGER DATA 1 BYTE = 8 BITS
76543210
BYTE 0
BYTE 1
BYTE 2
LOWER ADDRESSES
BYTE 3
1 WORD = 2 BYTES = 16 BITS
(MS BYTE)
WORD 0
BYTE 1
(LS BYTE)
(MS BYTE)
BYTE 0
WORD 1
BYTE 1
(LS BYTE)
1 LONG WORD = 2 WORDS = 4 BYTES = 32 BITS
BYTE 0
BYTE 1
LONG WORD 0
BYTE 2
BYTE 3
BYTE 0
BYTE 1
LONG WORD 1
BYTE 2
BYTE 3
HIGH-ORDER
WORD
LOW-ORDER
WORD
HIGH-ORDER
WORD
LOW-ORDER
WORD
HIGHER ADDRESSES
LOWER ADDRESSESBYTE 0
HIGHER ADDRESSES
LOWER ADDRESSES
HIGHER ADDRESSES
Figure 2-7. Memory Data Organization of the MC68008
2.5 INSTRUCTION SET SUMMARY
Table 2-2 provides an alphabetized listing of the M68000 instruction set listed by
opcode, operation, and syntax. In the syntax descriptions, the left operand is the source
operand, and the right operand is the destination operand. The following list contains the
notations used in Table 2-2.
2-8 M68000 8-/16-/32-BIT MICROPROCESSOR USER’S MANUAL MOTOROLA
Notation for operands:
PC — Program counter
SR — Status register
V — Overflow condition code
Immediate Data — Immediate data from the instruction
Source — Source contents
Destination — Destination contents
Vector — Location of exception vector
+inf — Positive infinity
–inf — Negative infinity
<fmt> — Operand data format: byte (B), word (W), long (L), single
(S), double (D), extended (X), or packed (P).
FPm — One of eight floating-point data registers (always
specifies the source register)
FPn — One of eight floating-point data registers (always
specifies the destination register)
Notation for subfields and qualifiers:
<bit> of <operand> — Selects a single bit of the operand
<ea>{offset:width} — Selects a bit field
(<ope ra nd >) — The contents of the referenced location
<operand>10 — The operand is binary-coded decimal, operations are
performed in decimal
(<address register>) — The register indirect operator
–(<address register>) — Indicates that the operand register points to the memory
(<address register>)+ — Location of the instruction operand—the optional mode
qualifiers are –, +, (d), and (d, ix)
#xxx or #<data> — Immediate data that follows the instruction word(s)
Notations for operations that have two operands, written <operand> <op> <operand>,
where <op> is one of the following:
→ — The source operand is moved to the destination operand
↔ — The two operands are exchanged
+ — The operands are added
– — The destination operand is subtracted from the source
operand
× — The operands are multiplied
÷ — The source operand is divided by the destination
operand
< — Relational test, true if source operand is less than
destination operand
> — Relational test, true if source operand is greater than
destination operand
V — Logical OR
⊕ — Logical exclusive OR
Λ — Logical AND
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSOR USER’S MANUAL 2-9
shifted by, rotated by — The source operand is shifted or rotated by the number of
positions specified by the second operand
Notation for single-operand operations:
~<operand> — The operand is logically complemented
<operand>sign-extended — The operand is sign-extended, all bits of the upper
portion are made equal to the high-order bit of the lower
portion
<operand>tested — The operand is compared to zero and the condition
codes are set appropriately
Notation for other operations:
TRAP — Equivalent to Format/Offset Word → (SSP); SSP–2 →
SSP; PC → (SSP); SSP–4 → SSP; SR → (SSP);
SSP–2 → SSP; (vector) → PC
STOP — Enter the stopped state, waiting for interrupts
If <condition> then — The condition is tested. If true, the operations after "then"
<operations> else are performed. If the condition is false and the optional
<operations> "else" clause is present, the operations after "else" are
performed. If the condition is false and else is omitted, the
instruction performs no operation. Refer to the Bcc
instruction description as an example.
2-10 M68000 8-/16-/32-BIT MICROPROCESSOR USER’S MANUAL MOTOROLA
Table 2-2. Instruction Set Summary (Sheet 1 of 4)
Opcode Operation Syntax
ABCD Source10 + Destination10 + X → Destination ABCD Dy,Dx
ABCD –(Ay), –(Ax)
ADD Source + Destination → Destination ADD <ea>,Dn
ADD Dn,<ea>
ADDA Source + Destination → Destination ADDA <ea>,An
ADDI Immediate Data + Destination → Destination ADDI # <data>,<ea>
ADDQ Immediate Data + Destination → Destination ADDQ # <data>,<ea>
ADDX Source + Destination + X → Destination ADDX Dy, Dx
ADDX –(Ay), –(Ax)
AND Source Λ Destination → Destination AND <ea>,Dn
AND Dn,<ea>
ANDI Immediate Data Λ Destination → Destination ANDI # <data>, <ea>
ANDI to CCR Source Λ CCR → CC R ANDI # <data>, CCR
ANDI to SR If supervisor state
then Source Λ SR → SR
else TRAP
ASL, ASR Destination Shifted by <count> → Destination ASd Dx,Dy
Bcc If (condition true) then PC + d → PC Bcc <label>
BCHG ~ (<number> of Destination) → Z;
~ (<number> of Destination) → <bit number> of Destination
BCLR ~ (<bit number> of Destination) → Z;
0 → <bit number> of Destination
BKPT Run breakpoint acknowledge cycle;
TRAP as illegal instruction
BRA PC + d → P C BRA <label>
BSET ~ (<bit number> of Destination) → Z;
1 → <bit number> of Destination
BSR SP – 4 → SP; PC → (SP); PC + d → PC BSR <label>
BTST – (<bit number> of Destination) → Z; BTST Dn,<ea>
CHK If Dn < 0 or Dn > Source then TRAP CHK <ea>,Dn
CLR 0 → Destination CLR <ea>
CMP Destination—Source → cc CMP <ea>,Dn
CMPA Destination—Source CMPA <ea>,An
CMPI Destination —Immediate Data CMPI # <data>,<ea>
CMPM Destination—Source → cc CMPM (Ay)+, (Ax)+
DBcc If condition false then (Dn – 1 → Dn;
If Dn ≠ –1 then PC + d → PC)
ANDI # <data>, SR
ASd # <data>,Dy
ASd <ea>
BCHG Dn,<ea>
BCHG # <data>,<ea>
BCLR Dn,<ea>
BCLR # <data>,<ea>
BKPT # <data>
BSET Dn,<ea>
BSET # <data>,<ea>
BTST # <data>,<ea>
DBcc Dn,<label>
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSOR USER’S MANUAL 2-11
Table 2-2. Instruction Set Summary (Sheet 2 of 4)
Opcode Operation Syntax
DIVS Destination/Source → Destination DIVS.W <ea>,Dn 32/16 → 16r:16q
DIVU Destination/Source → Destination DIVU.W <ea>,Dn 32/16 → 16r:16q
EOR Source ⊕ Destination → Destination EOR Dn,<ea>
EORI Immediate Data ⊕ Destination → Destination EORI # <data>,<ea>
EORI to CCR Source ⊕ CCR → CCR EORI # <data>,CCR
EORI to SR If supervisor state
then Source ⊕SR → SR
else TRAP
EXG Rx ↔ Ry EXG Dx,Dy
EXT Destination Sign-Extended → Destination EXT.W Dn extend byte to word
ILLEGAL SSP – 2 → SSP; Vector Offset → (SSP);
SSP – 4 → SSP; PC → (SSP);
SSP – 2 → SSP; SR → (SSP);
Illegal Instruction Vector Address → PC
JMP Destination Address → PC JMP <ea>
JSR SP – 4 → SP; PC → (SP)
Destination Address → PC
LEA <ea> → An LEA <ea>,An
LINK SP – 4 → SP; An → (SP)
SP → An, SP + d → SP
LSL,LSR Destination Shifted by <count> → Destination LSd1 Dx,Dy
MOVE Source → Destination MOVE <ea>,<ea>
MOVEA Source → Destination MOVEA <ea>,An
MOVE from
CCR
MOVE to
CCR
MOVE fromSRSR → Destination
MOVE to SR If supervisor state
CCR → Destination MOVE CCR,<ea>
Source → CCR MOVE <ea>,CCR
If supervisor state
then SR → Destination
else TRAP (MC68010 only)
then Source → SR
else TRAP
EORI # <data>,SR
EXG Ax,Ay
EXG Dx,Ay
EXG Ay,Dx
EXT.L Dn extend word to long word
ILLEGAL
JSR <ea>
LINK An, # <displacement>
LSd1 # <data>,Dy
LSd1 <ea>
MOVE SR,<ea>
MOVE <ea>,SR
2-12 M68000 8-/16-/32-BIT MICROPROCESSOR USER’S MANUAL MOTOROLA
Table 2-2. Instruction Set Summary (Sheet 3 of 4)
Opcode Operation Syntax
MOVE USP If supervisor state
then USP → An or An → USP
else TRAP
MOVEC If supervisor state
then Rc → Rn or Rn → Rc
else TRAP
MOVEM Registers → Destination
Source → Registers
MOVEP Source → Destination MOVEP Dx,(d,Ay)
MOVEQ Immediate Data → Destination MOVEQ # <data>,Dn
MOVES If supervisor state
then Rn → Destination [DFC] or Source [SFC] → Rn
else TRAP
MULS Source × Destination → Destination MULS.W <ea>,Dn 16 x 16 → 32
MULU Source × Destination → Destination MULU.W <ea>,Dn 16 x 16 → 32
NBCD 0 – (Destination10) – X → Destination NBCD <ea>
NEG 0 – (Destination) → Destination NEG <ea>
NEGX 0 – (Destination) – X → Destination NEGX <ea>
NOP None NOP
NOT ~Destination → Destination NOT <ea>
OR Source V Destination → Destination OR <ea>,Dn
ORI Immediate Data V Destination → Destination ORI # <data>,<ea>
ORI to CCR Source V CCR → CC R ORI # <data>,CCR
ORI to SR If supervisor state
then Source V SR → SR
else TRAP
PEA Sp – 4 → SP; <ea> → (SP) PEA <ea>
RESET If supervisor state
then Assert RESET Line
else TRAP
ROL, ROR Destination Rotated by <count> → Destination ROd1 Rx,Dy
ROXL,
ROXR
RTD (SP) → PC; SP + 4 + d → SP RTD #<displacement>
Destination Rotated with X by <count> → Destination ROXd1 Dx,Dy
MOVE USP,An
MOVE An,USP
MOVEC Rc,Rn
MOVEC Rn,Rc
MOVEM register list,<ea>
MOVEM <ea>,register list
MOVEP (d,Ay),Dx
MOVES Rn,<ea>
MOVES <ea>,Rn
OR Dn,<ea>
ORI # <data>,SR
RESET
ROd1 # <data>,Dy
ROd1 <ea>
1 #
ROXd
ROXd1 <ea>
<data>,Dy
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSOR USER’S MANUAL 2-13
Table 2-2. Instruction Set Summary (Sheet 4 of 4)
Opcode Operation Syntax
RTE If supervisor state
then (SP) → SR; SP + 2 → SP; (SP) → PC;
SP + 4 → SP;
restore state and deallocate stack according to (SP)
else TRAP
RTR (SP) → CCR; SP + 2 → SP;
(SP) → PC; SP + 4 → SP
RT S (SP) → PC; SP + 4 → SP RTS
SBCD Destination
Sc c If condition true
then 1s → Destination
else 0s → Destination
STOP If supervisor state
then Immediate Data → SR; STOP
else TRAP
SUB Destination – Source → Destination SUB <ea>,Dn
SUBA Destination – Source → Destination SUBA <ea>,An
SUBI Destination – Immediate Data → Destination SUBI # <data>,<ea>
SUBQ Destination – Immediate Data → Destination SUBQ # <data>,<ea>
SUBX Destination – Source – X → Destination SUBX Dx,Dy
SWAP Register [31:16] ↔ Register [15:0] SWAP Dn
TAS Destination Tested → Condition Codes; 1 → bit 7 of
Destination
TRAP SSP – 2 → SSP; Format/Offset → (SSP);
SSP – 4 → SSP; PC → (SSP); SSP–2 → SSP;
SR → (SSP); Vector Address → PC
TRAPV If V then TRAP TRAPV
TST Destination Tested → Condition Codes TST <ea>
UNLK An → SP; (SP) → An; SP + 4 → SP UNLK An
NOTE: d is direction, L or R.
– Source
10
– X → Destination SBCD Dx,Dy
10
RTE
RTR
SBCD –(Ax),–(Ay)
Scc <ea>
STOP # <data>
SUB Dn,<ea>
SUBX –(Ax),–(Ay)
TAS <ea>
TRAP # <vector>
2-14 M68000 8-/16-/32-BIT MICROPROCESSOR USER’S MANUAL MOTOROLA
SECTION 3
SIGNAL DESCRIPTION
This section contains descriptions of the input and output signals. The input and output
signals can be functionally organized into the groups shown in Figure 3-1 (for the
MC68000, the MC68HC000 and the MC68010), Figure 3-2 ( for the MC68HC001), Figure
3-3 (for the MC68EC000), Figure 3-4 (for the MC68008, 48-pin version), and Figure 3-5
(for the MC68008, 52-pin version). The following paragraphs provide brief descriptions of
the signals and references (where applicable) to other paragraphs that contain more
information about the signals.
NOTE
The terms assertion and negation are used extensively in this
manual to avoid confusion when describing a mixture of
"active-low" and "active-high" signals. The term assert or
assertion is used to indicate that a signal is active or true,
independently of whether that level is represented by a high or
low voltage. The term negate or negation is used to indicate
that a signal is inactive or false.
PROCESSOR
STATUS
MC6800
PERIPHERAL
CONTROL
SYSTEM
CONTROL
(2)
V
CC
GND(2)
CLK
FC0
FC1
FC2
E
VMA
VPA
BERR
RESET
HALT
ADDRESS
BUS
DATA BUS
AS
R/W
UDS
LDS
DTACK
BR
BG
BGACK
IPL0
IPL1
IPL2
A23–A1
D15–D0
ASYNCHRONOUS
BUS
CONTROL
BUS
ARBITRATION
CONTROL
INTERRUPT
CONTROL
Figure 3-1. Input and Output Signals
(MC68000, MC68HC000 and MC68010)
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 3-1
PROCESSOR
STATUS
V
CC
GND(2)
CLK
FC0
FC1
FC2
(2)
ADDRESS
BUS
DATA BUS
AS
R/W
UDS
LDS
DTACK
A23–A0
D15–D0
ASYNCHRONOUS
BUS
CONTROL
MC6800
PERIPHERAL
CONTROL
SYSTEM
CONTROL
PROCESSOR
STATUS
E
VMA
VPA
BERR
RESET
HALT
MODE
BR
BG
BGACK
IPL0
IPL1
IPL2
Figure 3-2. Input and Output Signals
(MC68HC001)
(2)
V
CC
GND(2)
CLK
FC0
FC1
FC2
MC68EC000
ADDRESS
BUS
DATA BUS
AS
R/W
UDS
LDS
DTACK
A23–A0
D15–D0
BUS
ARBITRATION
CONTROL
INTERRUPT
CONTROL
ASYNCHRONOUS
BUS
CONTROL
BR
BG
BERR
SYSTEM
CONTROL
RESET
HALT
MODE
IPL0
IPL1
IPL2
AVEC
BUS
ARBITRATION
CONTROL
INTERRUPT
CONTROL
Figure 3-3. Input and Output Signals
(MC68EC000)
3-2 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA
VCC(2)
GND(2)
CLK
ADDRESS
BUS A19–A0
DATA BUS
D7–D0
PROCESSOR
STATUS
MC6800
PERIPHERAL
CONTROL
SYSTEM
CONTROL
FC0
FC1
FC2
VPA
BERR
RESET
HALT
AS
R/W
MC6808
E
DS
DTACK
BR
BG
IPL2/IPL0
IPL1
ASYNCHRONOUS
BUS
CONTROL
BUS
ARBITRATION
CONTROL
INTERRUPT
CONTROL
Figure 3-4. Input and Output Signals (MC68008, 48-Pin Version)
V
PROCESSOR
STATUS
CC
GND(2)
CLK
FC0
FC1
FC2
MC68008
ADDRESS
BUS
DATA BUS D7–D0
AS
R/W
DS
DTACK
A21–A0
ASYNCHRONOUS
BUS
CONTROL
MC6800
PERIPHERAL
CONTROL
SYSTEM
CONTROL
VPA
BERR
RESET
HALT
E
BR
BG
BGACK
IPL0
IPL1
IPL2
BUS
ARBITRATION
CONTROL
INTERRUPT
CONTROL
Figure 3-5. Input and Output Signals (MC68008, 52-Pin Version)
3.1 ADDRESS BUS (A23–A1)
This 23-bit, unidirectional, three-state bus is capable of addressing 16 Mbytes of data.
This bus provides the address for bus operation during all cycles except interrupt
acknowledge cycles and breakpoint cycles. During interrupt acknowledge cycles, address
lines A1, A2, and A3 provide the level number of the interrupt being acknowledged, and
address lines A23–A4 are driven to logic high.
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 3-3
Address Bus (A23–A0)
AS
W
UDS, LDS
This 24-bit, unidirectional, three-state bus is capable of addressing 16 Mbytes of data.
This bus provides the address for bus operation during all cycles except interrupt
acknowledge cycles and breakpoint cycles. During interrupt acknowledge cycles,
address lines A1, A2, and A3 provide the level number of the interrupt being
acknowledged, and address lines A23–A4 and A0 are driven to logic high. In 16-Bit
mode, A0 is always driven high.
MC68008 Address Bus
The unidirectional, three-state buses in the two versions of the MC68008 differ from
each other and from the other processor bus only in the number of address lines and
the addressing range. The 20-bit address (A19–A0) of the 48-pin version provides a 1 Mbyte address space; the 52-pin version supports a 22-bit address (A21–A0), extending
the address space to 4 Mbytes. During an interrupt acknowledge cycle, the interrupt
level number is placed on lines A1, A2, and A3. Lines A0 and A4 through the most
significant address line are driven to logic high.
3.2 DATA BUS (D15–D0; MC68008: D7–D0)
This bidirectional, three-state bus is the general-purpose data path. It is 16 bits wide in the
all the processors except the MC68008 which is 8 bits wide. The bus can transfer and
accept data of either word or byte length. During an interrupt acknowledge cycle, the
external device supplies the vector number on data lines D7–D0. The MC68EC000 and
MC68HC001 use D7–D0 in 8-bit mode, and D15–D8 are undefined.
3.3 ASYNCHRONOUS BUS CONTROL
Asynchronous data transfers are controlled by the following signals: address strobe,
read/write, upper and lower data strobes, and data transfer acknowledge. These signals
are described in the following paragraphs.
Address Strobe (
This three-state signal indicates that the information on the address bus is a valid
address.
Read/Write (R/
This three-state signal defines the data bus transfer as a read or write cycle. The R/ W
signal relates to the data strobe signals described in the following paragraphs.
Upper And Lower Data Strobes (
These three-state signals and R/W control the flow of data on the data bus. Table 3-1
lists the combinations of these signals and the corresponding data on the bus. When
the R/W line is high, the processor reads from the data bus. When the R/W line is low,
the processor drives the data bus. In 8-bit mode , UDS is always forced high and the
LDS signal is used.
).
).
).
3-4 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA
Table 3-1. Data Strobe Control of Data Bus
UDS LDS
W
DS
W
DTACK
R/
High High — No Valid Data No Valid Data
Low Low High Valid Data Bits
High Low High No Valid Data Valid Data Bits
Low High High Valid Data Bus
Low Low Low Valid Data Bits
High Low Low Valid Data Bits
Low High Low Valid Data Bits
*These conditions are a result of current implementation and may not appear
on future devices.
D8–D15 D0–D7
Valid Data Bits
15–8
15–8
15–8
7–0*
15–8
7–0
7–0
No Valid Data
Valid Data Bits
7–0
Valid Data Bits
7–0
Valid Data Bits
15–8*
Data Strobe (DS) (MC68008)
This three-state signal and R/W control the flow of data on the data bus of the
MC68008. Table 3-2 lists the combinations of these signals and the corresponding data
on the bus. When the R/W line is high, the processor reads from the data bus. When
the R/W line is low, the processor drives the data bus.
Table 3-2. Data Strobe Control
of Data Bus (MC68008)
1 — No Valid Data
0 1 Valid Data Bits 7–0 (Read Cycle)
0 0 Valid Data Bits 7–0 (Write Cycle)
Data Transfer Acknowledge (
R/
).
D0–D7
This input signal indicates the completion of the data transfer. When the processor
recognizes DTACK during a read cycle, data is latched, and the bus cycle is terminated.
When DTACK is recognized during a write cycle, the bus cycle is terminated.
3.4 BUS ARBITRATION CONTROL
The bus request, bus grant, and bus grant acknowledge signals form a bus arbitration
circuit to determine which device becomes the bus master device. In the 48-pin version of
the MC68008 and MC68EC000, no pin is available for the bus grant acknowledge signal;
this microprocessor uses a two-wire bus arbitration scheme. All M68000 processors can
use two-wire bus arbitration.
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 3-5
Bus Request (BR).
BG
BGACK
IPL0, IPL1, IPL2
This input can be wire-ORed with bus request signals from all other devices that could
be bus masters. This signal indicates to the processor that some other device needs to
become the bus master. Bus requests can be issued at any time during a cycle or
between cycles.
Bus Grant (
This output signal indicates to all other potential bus master devices that the processor
will relinquish bus control at the end of the current bus cycle.
Bus Grant Acknowledge (
This input indicates that some other device has become the bus master. This signal
should not be asserted until the following conditions are met:
1. A bus grant has been received.
2. Address strobe is inactive, which indicates that the microprocessor is not using the
bus.
3. Data transfer acknowledge is inactive, which indicates that neither memory nor
peripherals are using the bus.
4. Bus grant acknowledge is inactive, which indicates that no other device is still
claiming bus mastership.
The 48-pin version of the MC68008 has no pin available for the bus grant acknowledge
signal and uses a two-wire bus arbitration scheme instead. If another device in a system
supplies a bus grant acknowledge signal, the bus request input signal to the processor
should be asserted when either the bus request or the bus grant acknowledge from that
device is asserted.
).
).
3.5 INTERRUPT CONTROL (
These input signals indicate the encoded priority level of the device requesting an
interrupt. Level seven, which cannot be masked, has the highest priority; level zero
indicates that no interrupts are requested. IPL0 is the least significant bit of the encoded
level, and IPL2 is the most significant bit. For each interrupt request, these signals must
remain asserted until the processor signals interrupt acknowledge (FC2–FC0 and A19–
A16 high) for that request to ensure that the interrupt is recognized.
The 48-pin version of the MC68008 has only two interrupt
control signals: IPL0/IPL2 and IPL1. IPL0 /IPL2 is internally
connected to both IPL0 and IPL2, which provides four interrupt
priority levels: levels 0, 2, 5, and 7. In all other respects, the
interrupt priority levels in this version of the MC68008 are
identical to those levels in the other microprocessors described
in this manual.
3-6 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA
NOTE
)
3.6 SYSTEM CONTROL
BERR
RESET
HALT
The system control inputs are used to reset the processor, to halt the processor, and to
signal a bus error to the processor. The outputs reset the external devices in the system
and signal a processor error halt to those devices. The three system control signals are
described in the following paragraphs.
Bus Error (
This input signal indicates a problem in the current bus cycle. The problem may be the
following:
1. No response from a device.
2. No interrupt vector number returned.
3. An illegal access request rejected by a memory management unit.
4. Some other application-dependent error.
Either the processor retries the bus cycle or performs exception processing, as
determined by interaction between the bus error signal and the halt signal.
Reset (
The external assertion of this bidirectional signal along with the assertion of HALT starts
a system initialization sequence by resetting the processor. The processor assertion of
RESET (from executing a RESET instruction) resets all external devices of a system
without affecting the internal state of the processor. To reset both the processor and the
external devices, the RESET and HALT input signals must be asserted at the same
time.
Halt (
An input to this bidirectional signal causes the processor to stop bus activity at the
completion of the current bus cycle. This operation places all control signals in the
inactive state and places all three-state lines in the high-impedance state (refer to Table
3-4).
)
)
)
When the processor has stopped executing instructions (in the case of a double bus
fault condition, for example), the HALT line is driven by the processor to indicate the
condition to external devices.
Mode (MODE) (MC68HC001/68EC000)
The MODE input selects between the 8-bit and 16-bit operating modes. If this input is
grounded at reset, the processor will come out of reset in the 8-bit mode. If this input is
tied high or floating at reset, the processor will come out of reset in the 16-bit mode .
This input should be changed only at reset and must be stable two clocks after RESET
is negated. Changing this input during normal operation may produce unpredictable
results.
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 3-7
3.7 M6800 PERIPHERAL CONTROL
VPA
VMA
These control signals are used to interface the asynchronous M68000 processors with the
synchronous M6800 peripheral devices. These signals are described in the following
paragraphs.
Enable (E)
This signal is the standard enable signal common to all M6800 Family peripheral
devices. A single period of clock E consists of 10 MC68000 clock periods (six clocks
low, four clocks high). This signal is generated by an internal ring counter that may
come up in any state. (At power-on, it is impossible to guarantee phase relationship of E
to CLK.) The E signal is a free-running clock that runs regardless of the state of the
MPU bus.
Valid Peripheral Address (
This input signal indicates that the device or memory area addressed is an M6800
Family device or a memory area assigned to M6800 Family devices and that data
transfer should be synchronized with the E signal. This input also indicates that the
processor should use automatic vectoring for an interrupt. Refer to Appendix B M6800
Peripheral Interface.
Valid Memory Address (
This output signal indicates to M6800 peripheral devices that the address on the
address bus is valid and that the processor is synchronized to the E signal. This signal
only responds to a VPA input that identifies an M6800 Family device.
The MC68008 does not supply a VMA signal. This signal can be produced by a
transistor-to-transistor logic (TTL) circuit; an example is described in Appendix B
M6800 Peripheral Interface.
)
)
3.8 PROCESSOR FUNCTION CODES (FC0, FC1, FC2)
These function code outputs indicate the mode (user or supervisor) and the address
space type currently being accessed, as shown in Table 3-3. The function code outputs
are valid whenever AS is active.
3-8 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA
Table 3-3. Function Code Outputs
Function Code Output
FC2 FC1 FC0 Address Space Type
Low Low Low (Undefined, Reserved)
Low Low High User Data
Low High Low User Program
Low High High (Undefined, Reserved)
High Low Low (Undefined, Reserved)
High Low High Supervisor Data
High High Low Supervisor Program
High High High CPU Space
3.9 CLOCK (CLK)
The clock input is a TTL-compatible signal that is internally buffered for development of
the internal clocks needed by the processor. This clock signal is a constant frequency
square wave that requires no stretching or shaping. The clock input should not be gated
off at any time, and the clock signal must conform to minimum and maximum pulse-width
times listed in Section 10 Electrical Characteristics.
3.10 POWER SUPPLY (VCC and GND)
Power is supplied to the processor using these connections. The positive output of the
power supply is connected to the V
pins and ground is connected to the GND pins.
CC
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 3-9
3.11 SIGNAL SUMMARY
HALT
Table 3-4 summarizes the signals discussed in the preceding paragraphs.
Table 3-4. Signal Summary
Signal Name Mnemonic Input/Output Active State On
Hi-Z
On Bus
Relinquish
Address Bus A0–A23 Output High Yes Yes
Data Bus D0–D15 Input/Output High Yes Yes
Address Strobe AS Output Low No Yes
Read/Write R/W Output Read-High
Write-Low
Data Strobe DS Output Low No Yes
Upper and Lower Data Strobes UDS, LDS Output Low No Yes
Data Transfer Acknowledge DTACK Input Low No No
Bus Request BR Input Low No No
Bus Grant BG Output Low No No
Bus Grant Acknowledge BGACK Input Low No No
Interrupt Priority Level IPL 0, IPL1,
IPL 2
Bus Error BERR Input Low No No
Mode MODE Input High — —
Reset RESET Input/Output Low No* No*
Halt HALT Input/Output Low No* No*
Enable E Output High No N o
Valid Memory Address VMA Output Low No Yes
Valid Peripheral Address VPA Input Low No No
Function Code Output FC0, FC1,
FC2
Input Low No No
Output High No Y es
No Yes
Clock CLK Input High No No
Power Input V
Ground GND Input — — —
*Open drain.
CC
Input — — —
3-10 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA
SECTION 4
8-BIT BUS OPERATION
The following paragraphs describe control signal and bus operation for 8-bit operation
during data transfer operations, bus arbitration, bus error and halt conditions, and reset
operation. The 8-bit bus operations devices are the MC68008, MC68HC001 in 8-bit mode,
and MC68EC000 in 8-bit mode. The MC68HC001 and MC68EC000 select 8-bit mode by
grounding mode during reset.
4.1 DATA TRANSFER OPERATIONS
Transfer of data between devices involves the following signals:
1. Address bus A0 through highest numbered address line
2. Data bus D0 through D7
3. Control signals
The address and data buses are separate parallel buses used to transfer data using an
asynchronous bus structure. In all cases, the bus master must deskew all signals it issues
at both the start and end of a bus cycle. In addition, the bus master must deskew the
acknowledge and data signals from the slave device. For the MC68HC001 and
MC68EC000, UDS is held negated and D15–D8 are undefined in 8-bit mode.
The following paragraphs describe the read, write, read-modify-write, and CPU space
cycles. The indivisible read-modify-write cycle implements interlocked multiprocessor
communications. A CPU space cycle is a special processor cycle.
4.1.1 Read Cycle
During a read cycle, the processor receives one byte of data from the memory or from a
peripheral device. When the data is received, the processor internally positions the byte
appropriately.
The 8-bit operation must perform two or four read cycles to access a word or long word,
asserting the data strobe to read a single byte during each cycle. The address bus in 8-bit
operation includes A0, which selects the appropriate byte for each read cycle. Figure 4-1
and 4-2 illustrate the byte read-cycle operation.
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 4-1
BUS MASTER
ADDRESS THE DEVICE
1) SET R/W TO READ
2) PLACE FUNCTION CODE ON FC2–FC0
3) PLACE ADDRESS ON A23-A0
4) ASSERT ADDRESS STROBE (AS)
5) ASSERT LOWER DATA STROBE (LDS)
(DS ON MC68008)
ACQUIRE THE DATA
1) LATCH DATA
2) NEGATE LDS (DS FOR MC68008)
3) NEGATE AS
START NEXT CYCLE
Figure 4-1. Byte Read-Cycle Flowchart
SLAVE
INPUT THE DATA
1) DECODE ADDRESS
2) PLACE DATA ON D7–D0
3) ASSERT DATA TRANSFER
ACKNOWLEDGE (DTACK)
TERMINATE THE CYCLE
1) REMOVE DATA FROM D7–D0
2) NEGATE DTACK
S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 w w w w S5 S6 S7
CLK
FC2–FC0
A23–A0
AS
(DS)
LDS
R/W
DTACK
D7–D0
READ WRITE 2 WAIT STATE READ
Figure 4-2. Read and Write-Cycle Timing Diagram
4-2 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA
A bus cycle consists of eight states. The various signals are asserted during specific
states of a read cycle, as follows:
STATE 0 The read cycle starts in state 0 (S0). The processor places valid function
codes on FC0–FC2 and drives R/W high to identify a read cycle.
STATE 1 Entering state 1 (S1), the processor drives a valid address on the address
bus.
STATE 2 On the rising edge of state 2 (S2), the processor asserts AS and LDS,
or DS .
STATE 3 During state 3 (S3), no bus signals are altered.
STATE 4 During state 4 (S4), the processor waits for a cycle termination signal
(DTACK or BERR) or VPA, an M6800 peripheral signal. When VPA is
asserted during S4, the cycle becomes a peripheral cycle (refer to
Appendix B M6800 Peripheral Interface ). If neither termination signal is
asserted before the falling edge at the end of S4, the processor inserts wait
states (full clock cycles) until either DTACK or BERR is asserted.
STATE 5 During state 5 (S5), no bus signals are altered.
STATE 6 During state 6 (S6), data from the device is driven onto the data bus.
STATE 7 On the falling edge of the clock entering state 7 (S7), the processor latches
data from the addressed device and negates AS and LDS, or DS . At
the rising edge of S7, the processor places the address bus in the high-
impedance state. The device negates DTACK or BERR at this time.
NOTE
During an active bus cycle, VPA and BERR are sampled on
every falling edge of the clock beginning with S4, and data is
latched on the falling edge of S6 during a read cycle. The bus
cycle terminates in S7, except when BERR is asserted in the
absence of DTACK. In that case, the bus cycle terminates one
clock cycle later in S9.
4.1.2 Write Cycle
During a write cycle, the processor sends bytes of data to the memory or peripheral
device. Figures 4-3 and 4-4 illustrate the write-cycle operation
The 8-bit operation performs two write cycles for a word write operation, issuing the data
strobe signal during each cycle. The address bus includes the A0 bit to select the desired
byte.
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 4-3
BUS MASTER
S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7
ADDRESS THE DEVICE
1) PLACE FUNCTION CODE ON FC2–FC0
2) PLACE ADDRESS ON A23–A0
3) ASSERT ADDRESS STROBE (AS)
4) SET R/W TO WRITE
5) PLACE DATA ON D0–D7
6) ASSERT LOWER DATA STROBE (LDS)
OR DS
TERMINATE OUTPUT TRANSFER
1) NEGATE LDS OR DS
2) NEGATE AS
3) REMOVE DATA FROM D7-D0
4) SET R/W TO READ
START NEXT CYCLE
Figure 4-3. Byte Write-Cycle Flowchart
SLAVE
INPUT THE DATA
1) DECODE ADDRESS
2) STORE DATA ON D7–D0
3) ASSERT DATA TRANSFER
ACKNOWLEDGE (DTACK)
TERMINATE THE CYCLE
1) NEGATE DTACK
CLK
FC2–FC0
A23–A0
AS
LDS
R/W
DTACK
D7–D0
ODD BYTE WRITE ODD BYTE WRITE
EVEN BYTE WRITE
Figure 4-4. Write-Cycle Timing Diagram
4-4 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA
The descriptions of the eight states of a write cycle are as follows:
STATE 0 The write cycle starts in S0. The processor places valid function codes on
FC2–FC0 and drives R/W high (if a preceding write cycle has left R/W low).
STATE 1 Entering S1, the processor drives a valid address on the address bus.
STATE 2 On the rising edge of S2, the processor asserts AS and drives R/W low.
STATE 3 During S3, the data bus is driven out of the high-impedance state as the
data to be written is placed on the bus.
STATE 4 At the rising edge of S4, the processor asserts LDS, or DS. The
processor waits for a cycle termination signal (DTACK or BERR) or VPA, an
M6800 peripheral signal. When VPA is asserted during S4, the cycle
becomes a peripheral cycle (refer to Appendix B M6800 Peripheral
Interface). If neither termination signal is asserted before the falling
edge at the end of S4, the processor inserts wait states (full clock cycles)
until either DTACK or BERR is asserted.
STATE 5 During S5, no bus signals are altered.
STATE 6 During S6, no bus signals are altered.
STATE 7 On the falling edge of the clock entering S7, the processor negates AS,
LDS, and DS . As the clock rises at the end of S7, the processor places
the address and data buses in the high-impedance state, and drives R/ W
high. The device negates DTACK or BERR at this time.
4.1.3 Read-Modify-Write Cycle.
The read-modify-write cycle performs a read operation, modifies the data in the arithmetic
logic unit, and writes the data back to the same address. The address strobe (AS ) remains
asserted throughout the entire cycle, making the cycle indivisible. The test and set (TAS)
instruction uses this cycle to provide a signaling capability without deadlock between
processors in a multiprocessing environment. The TAS instruction (the only instruction
that uses the read-modify-write cycle) only operates on bytes. Thus, all read-modify-write
cycles are byte operations. Figure 4-5 and 4-6 illustrate the read-modify-write cycle
operation.
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 4-5
BUS MASTER
ADDRESS THE DEVICE
1) SET R/W TO READ
2) PLACE FUNCTION CODE ON FC2–FC0
3) PLACE ADDRESS ON A23–A0
4) ASSERT ADDRESS STROBE (AS)
5) ASSERT LOWER DATA STROBE (LDS)
(DS ON MC68008)
ACQUIRE THE DATA
1) LATCH DATA
1) NEGATE LDS OR DS
2) START DATA MODIFICATION
START OUTPUT TRANSFER
1) SET R/W TO WRITE
2) PLACE DATA ON D7–D0
3) ASSERT LOWER DATA STROBE (LDS)
(DS ON MC68008)
TERMINATE OUTPUT TRANSFER
1) NEGATE DS OR LDS
2) NEGATE AS
3) REMOVE DATA FROM D7–D0
4) SET R/W TO READ
SLAVE
INPUT THE DATA
1) DECODE ADDRESS
2) PLACE DATA ON D7–D0
3) ASSERT DATA TRANSFER
ACKNOWLEDGE (DTACK)
TERMINATE THE CYCLE
1) REMOVE DATA FROM D7–D0
2) NEGATE DTACK
INPUT THE DATA
1) STORE DATA ON D7–D0
2) ASSERT DATA TRANSFER
ACKNOWLEDGE (DTACK)
TERMINATE THE CYCLE
1) NEGATE DTACK
START NEXT CYCLE
Figure 4-5. Read-Modify-Write Cycle Flowchart
4-6 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA
S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19
CLK
FC2–FC0
A23–A0
AS
DS OR LDS
R/W
DTACK
D7–D0
INDIVISIBLE CYCLE
Figure 4-6. Read-Modify-Write Cycle Timing Diagram
The descriptions of the read-modify-write cycle states are as follows:
STATE 0 The read cycle starts in S0. The processor places valid function codes on
FC2–FC0 and drives R/W high to identify a read cycle.
STATE 1 Entering S1, the processor drives a valid address on the address bus.
STATE 2 On the rising edge of S2, the processor asserts AS and LDS , or DS .
STATE 3 During S3, no bus signals are altered.
STATE 4 During S4, the processor waits for a cycle termination signal (DTACK or
BERR) or VPA, an M6800 peripheral signal. When VPA is asserted during
S4, the cycle becomes a peripheral cycle (refer to Appendix B M6800
Peripheral Interface). If neither termination signal is asserted before the
falling edge at the end of S4, the processor inserts wait states (full clock
cycles) until either DTACK or BERR is asserted.
STATE 5 During S5, no bus signals are altered.
STATE 6 During S6, data from the device are driven onto the data bus.
STATE 7 On the falling edge of the clock entering S7, the processor accepts data
from the device and negates LDS, and DS. The device negates
DTACK or BERR at this time.
STATES 8–11
The bus signals are unaltered during S8–S11, during which the arithmetic
logic unit makes appropriate modifications to the data.
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 4-7
STATE 12 The write portion of the cycle starts in S12. The valid function codes on
FC2–FC0, the address bus lines, AS, and R/W remain unaltered.
STATE 13 During S13, no bus signals are altered.
STATE 14 On the rising edge of S14, the processor drives R/W low.
STATE 15 During S15, the data bus is driven out of the high-impedance state as the
data to be written are placed on the bus.
STATE 16 At the rising edge of S16, the processor asserts LDS or DS. The
processor waits for DTACK or BERR or VPA, an M6800 peripheral signal.
When VPA is asserted during S16, the cycle becomes a peripheral cycle
(refer to Appendix B M6800 Peripheral Interface). If neither termination
signal is asserted before the falling edge at the close of S16, the processor
inserts wait states (full clock cycles) until either DTACK or BERR is asserted.
STATE 17 During S17, no bus signals are altered.
STATE 18 During S18, no bus signals are altered.
STATE 19 On the falling edge of the clock entering S19, the processor negates AS,
LDS, and DS . As the clock rises at the end of S19, the processor
places the address and data buses in the high-impedance state, and drives
R/W high. The device negates DTACK or BERR at this time.
4.2 OTHER BUS OPERATIONS
Refer to Section 5 16-Bit Bus Operations for information on the following items:
• CPU Space Cycle
• Bus Arbitration
— Bus Request
— Bus Grant
— Bus Acknowledgment
• Bus Control
• Bus Errors and Halt Operations
• Reset Operations
• Asynchronous Operations
• Synchronous Operations
4-8 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA
SECTION 5
16-BIT BUS OPERATION
The following paragraphs describe control signal and bus operation for 16-bit bus
operations during data transfer operations, bus arbitration, bus error and halt conditions,
and reset operation. The 16-bit bus operation devices are the MC68000, MC68HC000,
MC68010, and the MC68HC001 and MC68EC000 in 16-bit mode. The MC68HC001 and
MC68EC000 select 16-bit mode by pulling mode high or leave it floating during reset.
5.1 DATA TRANSFER OPERATIONS
Transfer of data between devices involves the following signals:
1. Address bus A1 through highest numbered address line
2. Data bus D0 through D15
3. Control signals
The address and data buses are separate parallel buses used to transfer data using an
asynchronous bus structure. In all cases, the bus master must deskew all signals it issues
at both the start and end of a bus cycle. In addition, the bus master must deskew the
acknowledge and data signals from the slave device.
The following paragraphs describe the read, write, read-modify-write, and CPU space
cycles. The indivisible read-modify-write cycle implements interlocked multiprocessor
communications. A CPU space cycle is a special processor cycle.
5.1.1 Read Cycle
During a read cycle, the processor receives either one or two bytes of data from the
memory or from a peripheral device. If the instruction specifies a word or long-word
operation, the MC68000, MC68HC000, MC68HC001, MC68EC000, or MC68010
processor reads both upper and lower bytes simultaneously by asserting both upper and
lower data strobes. When the instruction specifies byte operation, the processor uses the
internal A0 bit to determine which byte to read and issues the appropriate data strobe.
When A0 equals zero, the upper data strobe is issued; when A0 equals one, the lower
data strobe is issued. When the data is received, the processor internally positions the
byte appropriately.
The word read-cycle flowchart is shown in Figure 5-1 and the byte read-cycle flowchart is
shown in Figure 5-2. The read and write cycle timing is shown in Figure 5-3 and the word
and byte read-cycle timing diagram is shown in Figure 5-4.
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 5-1
BUS MASTER
ADDRESS THE DEVICE
1) SET R/W TO READ
2) PLACE FUNCTION CODE ON FC2–FC0
3) PLACE ADDRESS ON A23–A1
4) ASSERT ADDRESS STROBE (AS)
5) ASSERT UPPER DATA STROBE (UDS)
AND LOWER DATA STROBE (LDS)
ACQUIRE THE DATA
1) LATCH DATA
2) NEGATE UDS AND LDS
3) NEGATE AS
START NEXT CYCLE
Figure 5-1. Word Read-Cycle Flowchart
SLAVE
INPUT THE DATA
1) DECODE ADDRESS
2) PLACE DATA ON D15–D0
3) ASSERT DATA TRANSFER
ACKNOWLEDGE (DTACK)
TERMINATE THE CYCLE
1) REMOVE DATA FROM D15–D0
2) NEGATE DTACK
BUS MASTER
SLAVE
ADDRESS THE DEVICE
1) SET R/W TO READ
2) PLACE FUNCTION CODE ON FC2–FC0
3) PLACE ADDRESS ON A23-A1
4) ASSERT ADDRESS STROBE (AS)
5) ASSERT UPPER DATA STROBE (UDS)
OR LOWER DATA STROBE (LDS)
(BASED ON INTERNAL A0)
1) DECODE ADDRESS
INPUT THE DATA
2) PLACE DATA ON D7–D0 OR D15–D8
(BASED ON UDS OR LDS)
ACQUIRE THE DATA
3) ASSERT DATA TRANSFER
ACKNOWLEDGE (DTACK)
1) LATCH DATA
2) NEGATE UDS AND LDS
3) NEGATE AS
TERMINATE THE CYCLE
1) REMOVE DATA FROM D7–D0
OR D15–D8
2) NEGATE DTACK
START NEXT CYCLE
Figure 5-2. Byte Read-Cycle Flowchart
5-2 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA
CLK
S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7
FC2–FC0
A23–A1
AS
UDS
LDS
R/W
DTACK
D15–D8
D7–D0
S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 w w w w S5 S6 S7
READ WRITE 2 WAIT STATE READ
Figure 5-3. Read and Write-Cycle Timing Diagram
CLK
FC2–FC0
A23–A1
A0 *
AS
UDS
LDS
R/W
DTACK
D15–D8
D7–D0
*Internal Signal Only
READ WRITE
READ
Figure 5-4. Word and Byte Read-Cycle Timing Diagram
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 5-3
A bus cycle consists of eight states. The various signals are asserted during specific
states of a read cycle, as follows:
STATE 0 The read cycle starts in state 0 (S0). The processor places valid function
codes on FC0–FC2 and drives R/W high to identify a read cycle.
STATE 1 Entering state 1 (S1), the processor drives a valid address on the address
bus.
STATE 2 On the rising edge of state 2 (S2), the processor asserts AS and UDS, LDS,
or DS .
STATE 3 During state 3 (S3), no bus signals are altered.
STATE 4 During state 4 (S4), the processor waits for a cycle termination signal
(DTACK or BERR) or VPA, an M6800 peripheral signal. When VPA is
asserted during S4, the cycle becomes a peripheral cycle (refer to
Appendix B M6800 Peripheral Interface ). If neither termination signal is
asserted before the falling edge at the end of S4, the processor inserts wait
states (full clock cycles) until either DTACK or BERR is asserted.
STATE 5 During state 5 (S5), no bus signals are altered.
STATE 6 During state 6 (S6), data from the device is driven onto the data bus.
STATE 7 On the falling edge of the clock entering state 7 (S7), the processor latches
data from the addressed device and negates AS, UDS, and LDS. At
the rising edge of S7, the processor places the address bus in the high-
impedance state. The device negates DTACK or BERR at this time.
NOTE
During an active bus cycle, VPA and BERR are sampled on
every falling edge of the clock beginning with S4, and data is
latched on the falling edge of S6 during a read cycle. The bus
cycle terminates in S7, except when BERR is asserted in the
absence of DTACK. In that case, the bus cycle terminates one
clock cycle later in S9.
5.1.2 Write Cycle
During a write cycle, the processor sends bytes of data to the memory or peripheral
device. If the instruction specifies a word operation, the processor issues both UDS and
LDS and writes both bytes. When the instruction specifies a byte operation, the processor
uses the internal A0 bit to determine which byte to write and issues the appropriate data
strobe. When the A0 bit equals zero, UDS is asserted; when the A0 bit equals one, LDS is
asserted.
5-4 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA
The word and byte write-cycle timing diagram and flowcharts in Figures 5-5, 5-6, and 5-7
BUS MASTER
applies directly to the MC68000, the MC68HC000, the MC68HC001 (in 16-bit mode), the
MC68EC000 (in 16-bit mode), and the MC68010.
ADDRESS THE DEVICE
1) PLACE FUNCTION CODE ON FC2–FC0
2) PLACE ADDRESS ON A23–A1
3) ASSERT ADDRESS STROBE (AS)
4) SET R/W TO WRITE
5) PLACE DATA ON D15–D0
6) ASSERT UPPER DATA STROBE (UDS)
AND LOWER DATA STROBE (LDS)
TERMINATE OUTPUT TRANSFER
1) NEGATE UDS AND LDS
2) NEGATE AS
3) REMOVE DATA FROM D15–D0
4) SET R/W TO READ
START NEXT CYCLE
Figure 5-5. Word Write-Cycle Flowchart
SLAVE
INPUT THE DATA
1) DECODE ADDRESS
2) STORE DATA ON D15–D0
3) ASSERT DATA TRANSFER
ACKNOWLEDGE (DTACK)
TERMINATE THE CYCLE
1) NEGATE DTACK
BUS MASTER
ADDRESS THE DEVICE
1) PLACE FUNCTION CODE ON FC2–FC0
2) PLACE ADDRESS ON A23–A1
3) ASSERT ADDRESS STROBE (AS)
4) SET R/W TO WRITE
5) PLACE DATA ON D0–D7 OR D15–D8
(ACCORDING TO INTERNAL A0)
6) ASSERT UPPER DATA STROBE (UDS)
OR LOWER DATA STROBE (LDS)
(BASED ON INTERNAL A0)
TERMINATE OUTPUT TRANSFER
1) NEGATE UDS AND LDS
2) NEGATE AS
3) REMOVE DATA FROM D7-D0 OR
D15-D8
4) SET R/W TO READ
START NEXT CYCLE
1) DECODE ADDRESS
2) STORE DATA ON D7–D0 IF LDS IS
ASSERTED. STORE DATA ON D15–D8
IF UDS IS ASSERTED
3) ASSERT DATA TRANSFER
ACKNOWLEDGE (DTACK)
1) NEGATE DTACK
SLAVE
INPUT THE DATA
TERMINATE THE CYCLE
Figure 5-6. Byte Write-Cycle Flowchart
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 5-5
S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7
CLK
FC2–FC0
A23–A1
*
A0
AS
UDS
LDS
R/W
DTACK
D15–D8
D7–D0
*INTERNAL SIGNAL ONLY
WORD WRITE ODD BYTE WRITE
EVEN BYTE WRITE
Figure 5-7. Word and Byte Write-Cycle Timing Diagram
The descriptions of the eight states of a write cycle are as follows:
STATE 0 The write cycle starts in S0. The processor places valid function codes on
FC2–FC0 and drives R/W high (if a preceding write cycle has left R/W low).
STATE 1 Entering S1, the processor drives a valid address on the address bus.
STATE 2 On the rising edge of S2, the processor asserts AS and drives R/W low.
STATE 3 During S3, the data bus is driven out of the high-impedance state as the
data to be written is placed on the bus.
STATE 4 At the rising edge of S4, the processor asserts UDS, or LDS. The
processor waits for a cycle termination signal (DTACK or BERR) or VPA, an
M6800 peripheral signal. When VPA is asserted during S4, the cycle
becomes a peripheral cycle (refer to Appendix B M6800 Peripheral
Interface. If neither termination signal is asserted before the falling
edge at the end of S4, the processor inserts wait states (full clock cycles)
until either DTACK or BERR is asserted.
STATE 5 During S5, no bus signals are altered.
STATE 6 During S6, no bus signals are altered.
5-6 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA
STATE 7 On the falling edge of the clock entering S7, the processor negates AS,
BUS MASTER
ADDRESS THE DEVICE
1) SET R/W TO READ
2
3
4
5
TERMINATE THE CYCLE
INPUT THE DATA
1) DECODE ADDRESS
2
3
SLAVE
START NEXT CYCLE
1) REMOVE DATA FROM D7–D0
2
1) LATCH DATA
1
2
ACQUIRE THE DATA
START OUTPUT TRANSFER
1) SET R/W TO WRITE
2
3
TERMINATE OUTPUT TRANSFER
1) NEGATE UDS OR LDS
2
3
4
INPUT THE DATA
1) STORE DATA ON D7–D0 OR D15–D8
2
TERMINATE THE CYCLE
1) NEGATE DTACK
UDS, or LDS. As the clock rises at the end of S7, the processor places
the address and data buses in the high-impedance state, and drives R/ W
high. The device negates DTACK or BERR at this time.
5.1.3 Read-Modify-Write Cycle.
The read-modify-write cycle performs a read operation, modifies the data in the arithmetic
logic unit, and writes the data back to the same address. The address strobe (AS ) remains
asserted throughout the entire cycle, making the cycle indivisible. The test and set (TAS)
instruction uses this cycle to provide a signaling capability without deadlock between
processors in a multiprocessing environment. The TAS instruction (the only instruction
that uses the read-modify-write cycle) only operates on bytes. Thus, all read-modify-write
cycles are byte operations. The read-modify-write flowchart shown in Figure 5-8 and the
timing diagram in Figure 5-9, applies to the MC68000, the MC68HC000, the MC68HC001
(in 16-bit mode), the MC68EC000 (in 16-bit mode), and the MC68010.
) PLACE FUNCTION CODE ON FC2–FC0
) PLACE ADDRESS ON A23–A1
) ASSERT ADDRESS STROBE (AS)
) ASSERT UPPER DATA STROBE (UDS)
OR LOWER DATA STROBE (LDS)
) NEGATE UDS AND LDS
) START DATA MODIFICATION
) PLACE DATA ON D7–D0 OR D15–D8
) ASSERT UPPER DATA STROBE (UDS)
OR LOWER DATA STROBE (LDS)
) NEGATE AS
) REMOVE DATA FROM D7–D0 OR
D15–D8
) SET R/W TO READ
) PLACE DATA ON D7–D0 OR D15–D0
) ASSERT DATA TRANSFER
ACKNOWLEDGE (DTACK)
OR D15–D8
) NEGATE DTACK
) ASSERT DATA TRANSFER
ACKNOWLEDGE (DTACK)
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 5-7
Figure 5-8. Read-Modify-Write Cycle Flowchart
CLK
A23–A1
ASS0S1S2S3S4S5S6S7S8S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
INDIVISIBLE CYCLE
UDS OR LDS
R/W
DTACK
D15–D8
FC2–FC0
Figure 5-9. Read-Modify-Write Cycle Timing Diagram
The descriptions of the read-modify-write cycle states are as follows:
STATE 0 The read cycle starts in S0. The processor places valid function codes on
FC2–FC0 and drives R/W high to identify a read cycle.
STATE 1 Entering S1, the processor drives a valid address on the address bus.
STATE 2 On the rising edge of S2, the processor asserts AS and UDS , or LDS .
STATE 3 During S3, no bus signals are altered.
STATE 4 During S4, the processor waits for a cycle termination signal (DTACK or
BERR) or VPA, an M6800 peripheral signal. When VPA is asserted during
S4, the cycle becomes a peripheral cycle (refer to Appendix B M6800
Peripheral Interface). If neither termination signal is asserted before the
falling edge at the end of S4, the processor inserts wait states (full clock
cycles) until either DTACK or BERR is asserted.
STATE 5 During S5, no bus signals are altered.
STATE 6 During S6, data from the device are driven onto the data bus.
STATE 7 On the falling edge of the clock entering S7, the processor accepts data
from the device and negates UDS, and LDS. The device negates
DTACK or BERR at this time.
STATES 8–11
The bus signals are unaltered during S8–S11, during which the arithmetic
logic unit makes appropriate modifications to the data.
5-8 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA
STATE 12 The write portion of the cycle starts in S12. The valid function codes on
FC2–FC0 , the address bus lines, AS, and R/W remain unaltered.
STATE 13 During S13, no bus signals are altered.
STATE 14 On the rising edge of S14, the processor drives R/W low.
STATE 15 During S15, the data bus is driven out of the high-impedance state as the
data to be written are placed on the bus.
STATE 16 At the rising edge of S16, the processor asserts UDS or LDS. The
processor waits for DTACK or BERR or VPA, an M6800 peripheral signal.
When VPA is asserted during S16, the cycle becomes a peripheral cycle
(refer to Appendix B M6800 Peripheral Interface). If neither termination
signal is asserted before the falling edge at the close of S16, the processor
inserts wait states (full clock cycles) until either DTACK or BERR is asserted.
STATE 17 During S17, no bus signals are altered.
STATE 18 During S18, no bus signals are altered.
STATE 19 On the falling edge of the clock entering S19, the processor negates AS,
UDS, and LDS. As the clock rises at the end of S19, the processor
places the address and data buses in the high-impedance state, and drives
R/W high. The device negates DTACK or BERR at this time.
5.1.4 CPU Space Cycle
A CPU space cycle, indicated when the function codes are all high, is a special processor
cycle. Bits A16–A19 of the address bus identify eight types of CPU space cycles. Only the
interrupt acknowledge cycle, in which A16–A19 are high, applies to all the
microprocessors described in this manual. The MC68010 defines an additional type of
CPU space cycle, the breakpoint acknowledge cycle, in which A16–A19 are all low. Other
configurations of A16–A19 are reserved by Motorola to define other types of CPU cycles
used in other M68000 Family microprocessors. Figure 5-10 shows the encoding of CPU
space addresses.
FUNCTION
CODE
BREAKPOINT
ACKNOWLEDGE
(MC68010 only)
INTERRUPT
ACKNOWLEDGE
2031
111
111
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
31
1111111111111111111111111111
23 19 16 0
ADDRESS BUS
310
LEVEL 1
CPU SPACE
TYPE FIELD
Figure 5-10. CPU Space Address Encoding
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 5-9
The interrupt acknowledge cycle places the level of the interrupt being acknowledged on
IPL2–IPL0 VALID INTERNALLY
address bits A3–A1 and drives all other address lines high. The interrupt acknowledge
cycle reads a vector number when the interrupting device places a vector number on the
data bus and asserts DTACK to acknowledge the cycle.
The timing diagram for an interrupt acknowledge cycle is shown in Figure 5-11.
Alternately, the interrupt acknowledge cycle can be autovectored. The interrupt
acknowledge cycle is the same, except the interrupting device asserts VPA instead of
DTACK. For an autovectored interrupt, the vector number used is $18 plus the interrupt
level. This is generated internally by the microprocessor when VPA (or AVEC) is asserted
on an interrupt acknowledge cycle. DTACK and VPA (AVEC) should never be
simultaneously asserted.
IPL2–IPL0 SAMPLED
IPL2–IPL0 TRANSITION
CLK
FC2–FC0
A23–A4
A3–A1
AS
UDS*
LDS
R/W
DTACK
D15–D8
D7–D0
S0 S1 S2 S3 S4 S5 S6 S7 S0S1S2 S3 S4 S5
S6 S7 S0
S1 S2 S3 S4 w w w w S5 S6
IPL2–IPL0
LAST BUS CYCLE OF INSTRUCTION
(READ OR WRITE)
*
Although a vector number is one byte, both data strobes are asserted due to the microcode used for exception processing. The processor does not
recognize anything on data lines D8 through D15 at this time.
STACK
PCL
(SSP)
IACK CYCLE
(VECTOR NUMBER
ACQUISITION)
STACK AND
VECTOR
FETCH
Figure 5-11. Interrupt Acknowledge Cycle Timing Diagram
5-10 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA
The breakpoint acknowledge cycle is performed by the MC68010 to provide an indication
to hardware that a software breakpoint is being executed when the processor executes a
breakpoint (BKPT) instruction. The processor neither accepts nor sends data during this
cycle, which is otherwise similar to a read cycle. The cycle is terminated by either DTACK,
BERR, or as an M6800 peripheral cycle when VPA is asserted, and the processor
continues illegal instruction exception processing. Figure 5-12 illustrates the timing
diagram for the breakpoint acknowledge cycle.
S0 S2 S4 S6 S0 S2 S4 S6 S0 S2 S4 S6
CLK
FC2–FC0
A23–A1
AS
UDS
LDS
R/W
DTACK
D15–D8
D7–D0
WORD READ
BREAKPOINT
CYCLE
STACK PC LOW
Figure 5-12. Breakpoint Acknowledge Cycle Timing Diagram
5.2 BUS ARBITRATION
Bus arbitration is a technique used by bus master devices to request, to be granted, and
to acknowledge bus mastership. Bus arbitration consists of the following:
1. Asserting a bus mastership request
2. Receiving a grant indicating that the bus is available at the end of the current cycle
3. Acknowledging that mastership has been assumed
There are two ways to arbitrate the bus, 3-wire and 2-wire bus arbitration. The MC68000,
MC68HC000, MC68EC000, MC68HC001, MC68008, and MC68010 can do 2-wire bus
arbitration. The MC68000, MC68HC000, MC68HC001, and MC68010 can do 3-wire bus
arbitration. Figures 5-13 and 5-15 show 3-wire bus arbitration and Figures 5-14 and 5-16
show 2-wire bus arbitration. Bus arbitration on all microprocessors, except the 48-pin
MC68008 and MC68EC000, BGACK must be pulled high for 2-wire bus arbitration.
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 5-11
GRANT BUS ARBITRATION
REQUESTING DEVICE
PROCESSOR
1) ASSERT BUS GRANT (BG)
TERMINATE ARBITRATION
1) NEGATE BG (AND WAIT FOR BGACK
TO BE NEGATED)
REQUEST THE BUS
1) ASSERT BUS REQUEST (BR)
ACKNOWLEDGE BUS MASTERSHIP
1) EXTERNAL ARBITRATION DETER MINES NEXT BUS MASTER
2) NEXT BUS MASTER WAITS FOR
CURRENT CYCLE TO COMPLETE
3) NEXT BUS MASTER ASSERTS BUS
GRANT ACKNOWLEDGE (BGACK)
TO BECOME NEW MASTER
4) BUS MASTER NEGATES BR
OPERATE AS BUS MASTER
1) PERFORM DATA TRANSFERS (READ
AND WRITE CYCLES) ACCORDING
TO THE SAME RULES THE PRO CESSOR USES
RELEASE BUS MASTERSHIP
REARBITRATE OR RESUME
PROCESSOR OPERATION
1) NEGATE BGACK
Figure 5-13. 3-Wire Bus Arbitration Cycle Flowchart
(Not Applicable to 48-Pin MC68008 or MC68EC000)
5-12 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA
GRANT BUS ARBITRATION
PROCESSOR
CLK
FC2–FC0
A23–A1
AS
LDS/ UDS
R/W
DTACK
D15–D0
PROCESSOR
DMA DEVICE
PROCESSOR
DMA DEVICE
BRBGBGACK
1) ASSERT BUS GRANT (BG)
REQUESTING DEVICE
REQUEST THE BUS
1) ASSERT BUS REQUEST (BR)
OPERATE AS BUS MASTER
1) EXTERNAL ARBITRATION DETER MINES NEXT BUS MASTER
2) NEXT BUS MASTER WAITS FOR
CURRENT CYCLE TO COMPLETE
ACKNOWLEDGE RELEASE OF
BUS MASTERSHIP
1) NEGATE BUS GRANT (BG)
REARBITRATE OR RESUME
PROCESSOR OPERATION
RELEASE BUS MASTERSHIP
1) NEGATE BUS REQUEST (BR)
Figure 5-14. 2-Wire Bus Arbitration Cycle Flowchart
Figure 5-15. 3-Wire Bus Arbitration Timing Diagram
(Not Applicable to 48-Pin MC68008 or MC68EC000)
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 5-13
CLK
S0S6S2
S0 S2 S4 S6
FC2–FC0
A19–A0
AS
DS
R/W
DTACK
D7–D0
BR
BG
S4 S0 S2 S4 S6
S0 S2 S4 S6
PROCESSOR
DMA DEVICE PROCESSOR DMA DEVICE
Figure 5-16. 2-Wire Bus Arbitration Timing Diagram
The timing diagram in Figure 5-15 shows that the bus request is negated at the time that
an acknowledge is asserted. This type of operation applies to a system consisting of a
processor and one other device capable of becoming bus master. In systems having
several devices that can be bus masters, bus request lines from these devices can be
wire-ORed at the processor, and more than one bus request signal could occur.
The bus grant signal is negated a few clock cycles after the assertion of the bus grant
acknowledge signal. However, if bus requests are pending, the processor reasserts bus
grant for another request a few clock cycles after bus grant (for the previous request) is
negated. In response to this additional assertion of bus grant, external arbitration circuitry
selects the next bus master before the current bus master has completed the bus activity.
The timing diagram in Figure 5-15 also applies to a system consisting of a processor and
one other device capable of becoming bus master. Since the 48-pin version of the
MC68008 and the MC68EC000 does not recognize a bus grant acknowledge signal, this
processor does not negate bus grant until the current bus master has completed the bus
activity.
5.2.1 Requesting The Bus
External devices capable of becoming bus masters assert BR to request the bus. This
signal can be wire-ORed (not necessarily constructed from open-collector devices) from
any of the devices in the system that can become bus master. The processor, which is at
a lower bus priority level than the external devices, relinquishes the bus after it completes
the current bus cycle.
The bus grant acknowledge signal on all the processors except the 48-pin MC68008 and
MC68EC000 helps to prevent the bus arbitration circuitry from responding to noise on the
5-14 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA
bus request signal. When no acknowledge is received before the bus request signal is
negated, the processor continues the use of the bus.
5.2.2 Receiving The Bus Grant
The processor asserts BG as soon as possible. Normally, this process immediately follows
internal synchronization, except when the processor has made an internal decision to
execute the next bus cycle but has not yet asserted AS for that cycle. In this case, BG is
delayed until AS is asserted to indicate to external devices that a bus cycle is in progress.
BG can be routed through a daisy-chained network or through a specific priority-encoded
network. Any method of external arbitration that observes the protocol can be used.
5.2.3 Acknowledgment Of Mastership (3-Wire Bus Arbitration Only)
Upon receiving BG, the requesting device waits until AS, DTACK, and BGACK are negated
before asserting BGACK. The negation of AS indicates that the previous bus master has
completed its cycle. (No device is allowed to assume bus mastership while AS is
asserted.) The negation of BGACK indicates that the previous master has released the
bus. The negation of DTACK indicates that the previous slave has terminated the
connection to the previous master. (In some applications, DTACK might not be included in
this function; general-purpose devices would be connected using AS only.) When BGACK
is asserted, the asserting device is bus master until it negates BGACK. BGACK should not
be negated until after the bus cycle(s) is complete. A device relinquishes control of the bus
by negating BGACK.
The bus request from the granted device should be negated after BGACK is asserted. If
another bus request is pending, BG is reasserted within a few clocks, as described in 5.3
Bus Arbitration Control. The processor does not perform any external bus cycles before
reasserting BG.
5.3 BUS ARBITRATION CONTROL
All asynchronous bus arbitration signals to the processor are synchronized before being
used internally. As shown in Figure 5-17, synchronization requires a maximum of one
cycle of the system clock, assuming that the asynchronous input setup time (#47, defined
in Section 10 Electrical Characteristic) has been met. The input asynchronous signal is
sampled on the falling edge of the clock and is valid internally after the next falling edge.
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 5-15
INTERNAL SIGNAL VALID
EXTERNAL SIGNAL SAMPLED
CLK
BR (EXTERNAL)
47
BR (iNTERNAL)
Figure 5-17. External Asynchronous Signal Synchronization
Bus arbitration control is implemented with a finite-state machine. State diagram (a) in
Figure 5-18 applies to all processors using 3-wire bus arbitration and state diagram (b)
applies to processors using 2-wire bus arbitration, in which BGACK is permanently
negated internally or externally. The same finite-state machine is used, but it is effectively
a two-state machine because BGACK is always negated.
In Figure 5-18, input signals R and A are the internally synchronized versions of BR and
BGACK. The BG output is shown as G, and the internal three-state control signal is shown
as T. If T is true, the address, data, and control buses are placed in the high-impedance
state when AS is negated. All signals are shown in positive logic (active high), regardless
of their true active voltage level. State changes (valid outputs) occur on the next rising
edge of the clock after the internal signal is valid.
A timing diagram of the bus arbitration sequence during a processor bus cycle is shown in
Figure 5-19. The bus arbitration timing while the bus is inactive (e.g., the processor is
performing internal operations for a multiply instruction) is shown in Figure 5-20.
When a bus request is made after the MPU has begun a bus cycle and before AS has
been asserted (S0), the special sequence shown in Figure 5-21 applies. Instead of being
asserted on the next rising edge of clock, BG is delayed until the second rising edge
following its internal assertion.
5-16 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA
RA
RA
XX
GT
GT
RA
XA
RA
RA
1
GT
RA
GT
RA
RA
GT
RA
(a) 3-Wire Bus Arbitration
R
RA
R+A
XA
1
RA
GT
RX
GT
XX
GT
STATE 1
X
GT
STATE 2
R
R = Bus Request Internal
A = Bus Grant Acknowledge Internal
G = Bus Grant
T = Three-state Control to Bus Control Logic
X = Don't Care
Figure 5-18. Bus Arbitration Unit State Diagrams
R
R
GT
STATE 0
R
GT
STATE 3
R
X
(b) 2-Wire Bus Arbitration
GT
STATE 4
Notes:
1. State machine will not change if
the bus is S0 or S1. Refer to
BUS ARBITRATION CONTROL.
2. The address bus will be placed in
the high-impedance state if T is
asserted and AS is negated.
5.2.3.
Figures 5-19, 5-20, and 5-21 applies to all processors using 3-wire bus arbitration. Figures
5-22, 5-23, and 5-24 applies to all processors using 2-wire bus arbitration.
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 5-17
S0S1S2S3S4S5S6S7S0S1S2S3S4S5S6S7S0S1CLK
BUS THREE-STATED
B
G ASSERTED
B
L
B
B
BUS RELEASED FROM THREE STATE AND
P
B
B
B
BRBGBGACK
FC2–FC0
A23–A1
AS
UDS
LDS
R/W
DTACK
D15–D0
PROCESSOR
ALTERNATE BUS MASTER
PROCESSOR
R VALID INTERNA
R SAMPLED
R ASSERTED
ROCESSOR STARTS NEXT BUS CYCLE
GACK NEGATED INTERNAL
GACK SAMPLED
GACK NEGATED
Figure 5-19. 3-Wire Bus Arbitration Timing Diagram—Processor Active
5-18 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA
S0S1S2S3S4S5S6S7S0S1S2S3S4
CLK
BGACK NEGATED
B
G ASSERTED AND BUS THREE STATED
B
B
B
BRBGBGACK
FC2–FC0
A23–A1
AS
UDS
LDS
R/W
DTACK
D15–D0
PROCESSOR
BUS RELEASED FROM THREE STATE AND PROCESSOR STARTS NEXT BUS CYCLE
PROCESSOR
BUS
I
ALTERNATE BUS MASTER
R VALID INTERNAL
R SAMPLED
R ASSERTED
NACTIVE
Figure 5-20. 3-Wire Bus Arbitration Timing Diagram—Bus Inactive
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 5-19
BUS THREE-STATED
B
G ASSERTED
B
L
B
B
BUS RELEASED FROM THREE STATE AND
P
B
B
B
BRBGBGACK
AS
UDS
LDS
R/W
DTACK
D15–D0
PROCESSOR
ALTERNATE BUS MASTER
PROCESSOR
S0S2S4S6S0S2S4S6S0
CLK
FC2–FC0
A23–A1
R VALID INTERNA
R SAMPLED
R ASSERTED
ROCESSOR STARTS NEXT BUS CYCLE
GACK NEGATED INTERNAL
GACK SAMPLED
GACK NEGATED
Figure 5-21. 3-Wire Bus Arbitration Timing Diagram—Special Case
5-20 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA
BUS THREE-STATED
BG ASSERTED
BR VALID INTERNAL
BR SAMPLED
BR ASSERTED
BUS RELEASED FROM THREE STATE AND
PROCESSOR STARTS NEXT BUS CYCLE
BR NEGATED INTERNAL
BR SAMPLED
BR NEGATED
CLK
BR
BG
BGACK
FC2–FC0
A23–A1
AS
UDS
LDS
R/W
DTACK
D15–D0
S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7 S0 S1
PROCESSOR
ALTERNATE BUS MASTER PROCESSOR
Figure 5-22. 2-Wire Bus Arbitration Timing Diagram—Processor Active
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 5-21
CLK
BUS RELEASED FROM THREE STATE AND PROCESSOR STARTS NEXT BUS CYCLE
BR
BG
BGACK
FC2–FC0
A23–A1
AS
UDS
LDS
R/W
BR NEGATED
BG ASSERTED AND BUS THREE STATED
BR VALID INTERNAL
BR SAMPLED
BR ASSERTED
S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4
DTACK
D15–D0
PROCESSOR
BUS
INACTIVE
ALTERNATE BUS MASTER
PROCESSOR
Figure 5-23. 2-Wire Bus Arbitration Timing Diagram—Bus Inactive
5-22 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA
CLK
BR
BG
BGACK
FC2–FC0
A23–A1
AS
UDS
LDS
BUS THREE-STATED
BG ASSERTED
BR VALID INTERNAL
BR SAMPLED
BR ASSERTED
S0 S2 S4 S6 S0 S2 S4 S6 S0
BUS RELEASED FROM THREE STATE AND
PROCESSOR STARTS NEXT BUS CYCLE
BR NEGATED INTERNAL
BR SAMPLED
BR NEGATED
R/W
DTACK
D15–D0
PROCESSOR
ALTERNATE BUS MASTER PROCESSOR
Figure 5-24. 2-Wire Bus Arbitration Timing Diagram—Special Case
5.4. BUS ERROR AND HALT OPERATION
In a bus architecture that requires a handshake from an external device, such as the
asynchronous bus used in the M68000 Family, the handshake may not always occur. A
bus error input is provided to terminate a bus cycle in error when the expected signal is
not asserted. Different systems and different devices within the same system require
different maximum-response times. External circuitry can be provided to assert the bus
error signal after the appropriate delay following the assertion of address strobe.
In a virtual memory system, the bus error signal can be used to indicate either a page fault
or a bus timeout. An external memory management unit asserts bus error when the page
that contains the required data is not resident in memory. The processor suspends
execution of the current instruction while the page is loaded into memory. The MC68010
pushes enough information on the stack to be able to resume execution of the instruction
following return from the bus error exception handler.
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 5-23
The MC68010 also differs from the other microprocessors described in this manual
regarding bus errors. The MC68010 can detect a late bus error signal asserted within one
clock cycle after the assertion of data transfer acknowledge. When receiving a bus error
signal, the processor can either initiate a bus error exception sequence or try running the
cycle again.
5.4.1 Bus Error Operation
In all the microprocessors described in this manual, a bus error is recognized when
DTACK and HALT are negated and BERR is asserted. In the MC68010, a late bus error is
also recognized when HALT is negated, and DTACK and BERR are asserted within one
clock cycle.
When the bus error condition is recognized, the current bus cycle is terminated in S9 for a
read cycle, a write cycle, or the read portion of a read-modify-write cycle. For the write
portion of a read-modify-write cycle, the current bus cycle is terminated in S21. As long as
BERR remains asserted, the data and address buses are in the high-impedance state.
Figure 5-25 shows the timing for the normal bus error, and Figure 5-26 shows the timing
for the MC68010 late bus error.
S0 S2 S4
CLK
FC2–FC0
A23–A1
AS
LDS/UDS
R/W
DTACK
D15–D0
BERR
HALT
INITIATE
READ
ww
RESPONSE
FAILURE
w
w
S6
BUS ERROR
DETECTION
S8
INITIATE BUS
ERROR STACKING
Figure 5-25. Bus Error Timing Diagram
5-24 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA
S0 S2 S4 S6
CLK
FC2–FC0
A23–A1
AS
UDS/LDS
R/W
DTACK
D15–D0
BERR
HALT
READ CYCLE
BUS ERROR
DETECTION
INITIATE BUS
ERROR STACKING
Figure 5-26. Delayed Bus Error Timing Diagram (MC68010)
After the aborted bus cycle is terminated and BERR is negated, the processor enters
exception processing for the bus error exception. During the exception processing
sequence, the following information is placed on the supervisor stack:
1. Status register
2. Program counter (two words, which may be up to five words past the instruction
being executed)
3. Error information
The first two items are identical to the information stacked by any other exception. The
error information differs for the MC68010. The MC68000, MC68HC000, MC68HC001,
MC68EC000, and MC68008 stack bus error information to help determine and to correct
the error. The MC68010 stacks the frame format and the vector offset followed by 22
words of internal register information. The return from exception (RTE) instruction restores
the internal register information so that the MC68010 can continue execution of the
instruction after the error handler routine completes.
After the processor has placed the required information on the stack, the bus error
exception vector is read from vector table entry 2 (offset $08) and placed in the program
counter. The processor resumes execution at the address in the vector, which is the first
instruction in the bus error handler routine.
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 5-25
NOTE
In the MC68010, if a read-modify-write operation terminates in
a bus error, the processor reruns the entire read-modify-write
operation when the RTE instruction at the end of the bus error
handler returns control to the instruction in error. The
processor reruns the entire operation whether the error
occurred during the read or write portion.
5.4.2 Retrying The Bus Cycle
The assertion of the bus error signal during a bus cycle in which HALT is also asserted by
an external device initiates a retry operation. Figure 5-27 is a timing diagram of the retry
operation. The delayed BERR signal in the MC68010 also initiates a retry operation when
HALT is asserted by an external device. Figure 5-28 shows the timing of the delayed
operation.
CLK
FC2-FC0
A23–A1
LDS/UDS
R/W
DTACK
D15–D0
BERR
HALT
S0 S2 S4 S6
AS
READ
S8 S0 S2 S4 S6
1 CLOCK PERIOD≥
HALT
RETRY
Figure 5-27. Retry Bus Cycle Timing Diagram
5-26 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA
S0S2S4S6CLK
FC2–FC0
A23–A1
S0S2S4S6AS
R/W
DTACK
D0–D15
BERR
HALT
UDS
LDS
RETRY
HALT
READ
Figure 5-28. Delayed Retry Bus Cycle Timing Diagram
HALT)
The processor terminates the bus cycle, then puts the address and data lines in the highimpedance state. The processor remains in this state until HALT is negated. Then the
processor retries the preceding cycle using the same function codes, address, and data
(for a write operation). BERR should be negated at least one clock cycle before HALT is
negated.
NOTE
To guarantee that the entire read-modify-write cycle runs
correctly and that the write portion of the operation is
performed without negating the address strobe, the processor
does not retry a read-modify-write cycle. When a bus error
occurs during a read-modify-write operation, a bus error
operation is performed whether or not HALT is asserted.
5.4.3 Halt Operation (
HALT performs a halt/run/single-step operation similar to the halt operation of an
MC68000. When HALT is asserted by an external device, the processor halts and remains
halted as long as the signal remains asserted, as shown in Figure 5-29.
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 5-27
S0 S2 S4 S6
CLK
S0 S2 S4 S6
FC2–FC0
A23–A1
AS
UDS
LDS
R/W
DTACK
D0–D15
BERR
HALT
READ HALT
RETRY
Figure 5-29. Halt Operation Timing Diagram
While the processor is halted, the address bus and the data bus signals are placed in the
high-impedance state. Bus arbitration is performed as usual. Should a bus error occur
while HALT is asserted, the processor performs the retry operation previously described.
The single-step mode is derived from correctly timed transitions of HALT. HALT is negated
to allow the processor to begin a bus cycle, then asserted to enter the halt mode when the
cycle completes. The single-step mode proceeds through a program one bus cycle at a
time for debugging purposes. The halt operation and the hardware trace capability allow
tracing of either bus cycles or instructions one at a time. These capabilities and a software
debugging package provide total debugging flexibility.
5.4.4 Double Bus Fault
When a bus error exception occurs, the processor begins exception processing by
stacking information on the supervisor stack. If another bus error occurs during exception
processing (i.e., before execution of another instruction begins) the processor halts and
asserts HALT. This is called a double bus fault. Only an external reset operation can
restart a processor halted due to a double bus fault.
A retry operation does not initiate exception processing; a bus error during a retry
operation does not cause a double bus fault. The processor can continue to retry a bus
cycle indefinitely if external hardware requests.
5-28 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA
A double bus fault occurs during a reset operation when a bus error occurs while the
processor is reading the vector table (before the first instruction is executed). The reset
operation is described in the following paragraph.
5.5 RESET OPERATION
RESET is asserted externally for the initial processor reset. Subsequently, the signal can
be asserted either externally or internally (executing a RESET instruction). For proper
external reset operation, HALT must also be asserted.
When RESET and HALT are driven by an external device, the entire system, including the
processor, is reset. Resetting the processor initializes the internal state. The processor
reads the reset vector table entry (address $00000) and loads the contents into the
supervisor stack pointer (SSP). Next, the processor loads the contents of address $00004
(vector table entry 1) into the program counter. Then the processor initializes the interrupt
level in the status register to a value of seven. In the MC68010, the processor also clears
the vector base register to $00000. No other register is affected by the reset sequence.
Figure 5-30 shows the timing of the reset operation.
CLK
+ 5 VOLTS
V
CC
RESET
HALT
BUS CYCLES
NOTES:
1. Internal start-up time
2. SSP high read in here
3. SSP low read in here
4. PC High read in here
5. PC Low read in here
6. First instruction fetched here
Figure 5-30. Reset Operation Timing Diagram
T 100 MILLISECONDS
≥
<
T 4 CLOCKS
1
23456
Bus State Unknown:
All Control Signals Inactive.
Data Bus in Read Mode:
The RESET instruction causes the processor to assert RESET for 124 clock periods to
reset the external devices of the system. The internal state of the processor is not
affected. Neither the status register nor any of the internal registers is affected by an
internal reset operation. All external devices in the system should be reset at the
completion of the RESET instruction.
For the initial reset, RESET and HALT must be asserted for at least 100 ms. For a
subsequent external reset, asserting these signals for 10 clock cycles or longer resets the
processor. However, an external reset signal that is asserted while the processor is
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 5-29
executing a reset instruction is ignored. Since the processor asserts the RESET signal for
DTACK, BERR
HALT
124 clock cycles during execution of a reset instruction, an external reset should assert
RESET for at least 132 clock periods.
5.6 THE RELATIONSHIP OF
To properly control termination of a bus cycle for a retry or a bus error condition, DTACK,
BERR, and HALT should be asserted and negated on the rising edge of the processor
clock. This relationship assures that when two signals are asserted simultaneously, the
required setup time (specification #47, Section 9 Electrical Characteristics) for both of
them is met during the same bus state. External circuitry should be designed to
incorporate this precaution. A related specification, #48, can be ignored when DTACK,
BERR, and HALT are asserted and negated on the rising edge of the processor clock.
The possible bus cycle termination can be summarized as follows (case numbers refer to
Table 5-5).
Normal Termination: DTACK is asserted. BERR and HALT remain negated (case 1).
Halt Termination: HALT is asserted coincident with or preceding DTACK, and
Bus Error Termination: BERR is asserted in lieu of, coincident with, or preceding
BERR remains negated (case 2).
DTACK (case 3). In the MC68010, the late bus error also,
BERR is asserted following DTACK (case 4). HALT remains
negated and BERR is negated coincident with or after DTACK.
, AND
Retry Termination: HALT and BERR asserted in lieu of, coincident with, or before
DTACK (case 5). In the MC68010, the late retry also, BERR
and HALT are asserted following DTACK (case 6). BERR is
negated coincident with or after DTACK. HALT must be held at
least one cycle after BERR.
Table 5-1 shows the details of the resulting bus cycle termination in the M68000
microprocessors for various combinations of signal sequences.
5-30 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA
Table 5-1.
DTACK, BERR
HALT
Asserted on
Case
No.
LEGEND:
N — The number of the current even bus state (e.g., S4, S6, etc.)
A — Signal asserted in this bus state
NA — Signal not asserted in this bus state
X — Don't care
S — Signal asserted in preceding bus state and remains asserted in this state
Control
Signal
1 DTACK
BERR
HALT
2 DTACK
BERR
HALT
3 DTACK
BERR
HALT
4 DTACK
BERR
HALT
5 DTACK
BERR
HALT
6 DTACK
BERR
HALT
Rising Edge
of State
N N+2
A
NA
NA
A
NA
A/S
X
A
NA
A
NA
NA
X
A
A/S
A
NA
NA
S
NA
X
S
NA
S
X
S
NA
S
A
NA
X
S
S
S
A
A
MC68000/MC68HC000/001
EC000/MC68008 Results
Normal cycle terminate and continue. Normal cycle terminate and continue.
Normal cycle terminate and halt.
Continue when HALT negated.
Terminate and take bus error trap. Terminate and take bus error trap.
Normal cycle terminate and continue. Terminate and take bus error trap.
Terminate and retry when HALT
removed.
Normal cycle terminate and continue. Terminate and retry when HALT
, and
Assertion Results
MC68010 Results
Normal cycle terminate and halt.
Continue when HALT negated.
Terminate and retry when HALT
removed.
removed.
NOTE: All operations are subject to relevant setup and hold times.
The negation of BERR and HALT under several conditions is shown in Table 5-6. (DTACK
is assumed to be negated normally in all cases; for reliable operation, both DTACK and
BERR should be negated when address strobe is negated).
EXAMPLE A:
A system uses a watchdog timer to terminate accesses to unused address space. The
timer asserts BERR after timeout (case 3).
EXAMPLE B:
A system uses error detection on random-access memory (RAM) contents. The system
designer may:
1. Delay DTACK until the data is verified. If data is invalid, return BERR and HALT
simultaneously to retry the error cycle (case 5).
2. Delay DTACK until the data is verified. If data is invalid, return BERR at the same
time as DTACK (case 3).
3. For an MC68010, return DTACK before data verification. If data is invalid, assert
BERR and HALT to retry the error cycle (case 6).
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 5-31
4. For an MC68010, return DTACK before data verification. If data is invalid, assert
BERR
HALT
AS
R/W
DTACK
UDS/LDS
DATA
ADDR
BERR on the next clock cycle (case 4).
Table 5-6.
Conditions of
Termination in
Table 4-4
Bus Error BERR
Rerun BERR
Rerun BERR
Normal BERR
Normal BERR
• = Signal is negated in this bus state.
Control Signal N N+2 Results—Next Cycle
HALT
HALT
HALT
HALT
HALT •or
Negated on Rising
and
Edge of State
•
•
•
•
•
•
•or•
or
or
or • Illegal sequence; usually traps to vector number 0.
Negation Results
•
Takes bus error trap.
•
Reruns the bus cycle.
•
May lengthen next cycle.
•
If next cycle is started, it will be terminated as a bus
none
error.
5.7 ASYNCHRONOUS OPERATION
To achieve clock frequency independence at a system level, the bus can be operated in
an asynchronous manner. Asynchronous bus operation uses the bus handshake signals
to control the transfer of data. The handshake signals are AS, UDS, LDS, DS (MC68008
only), DTACK, BERR, HALT, AVEC (MC68EC000 only), and VPA (only for M6800
peripheral cycles). AS indicates the start of the bus cycle, and UDS, LDS, and DS signal
valid data for a write cycle. After placing the requested data on the data bus (read cycle)
or latching the data (write cycle), the slave device (memory or peripheral) asserts DTACK
to terminate the bus cycle. If no device responds or if the access is invalid, external control
logic asserts BERR, or BERR and HALT, to abort or retry the cycle. Figure 5-31 shows the
use of the bus handshake signals in a fully asynchronous read cycle. Figure 5-32 shows a
fully asynchronous write cycle.
Figure 5-31. Fully Asynchronous Read Cycle
5-32 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA
ADDR
AS
R/W
UDS/LDS
DATA
DTACK
Figure 5-32. Fully Asynchronous Write Cycle
In the asynchronous mode, the accessed device operates independently of the frequency
and phase of the system clock. For example, the MC68681 dual universal asynchronous
receiver/transmitter (DUART) does not require any clock-related information from the bus
master during a bus transfer. Asynchronous devices are designed to operate correctly
with processors at any clock frequency when relevant timing requirements are observed.
A device can use a clock at the same frequency as the system clock (e.g., 8, 10, or 12.5,
16, and 20MHz), but without a defined phase relationship to the system clock. This mode
of operation is pseudo-asynchronous; it increases performance by observing timing
parameters related to the system clock frequency without being completely synchronous
with that clock. A memory array designed to operate with a particular frequency processor
but not driven by the processor clock is a common example of a pseudo-asynchronous
device.
The designer of a fully asynchronous system can make no assumptions about address
setup time, which could be used to improve performance. With the system clock frequency
known, the slave device can be designed to decode the address bus before recognizing
an address strobe. Parameter #11 (refer to Section 10 Electrical Characteristics )
specifies the minimum time before address strobe during which the address is valid.
In a pseudo-asynchronous system, timing specifications allow DTACK to be asserted for a
read cycle before the data from a slave device is valid. The length of time that DTACK
may precede data is specified as parameter #31. This parameter must be met to ensure
the validity of the data latched into the processor. No maximum time is specified from the
assertion of AS to the assertion of DTACK. During this unlimited time, the processor
inserts wait cycles in one-clock-period increments until DTACK is recognized. Figure 5-33
shows the important timing parameters for a pseudo-asynchronous read cycle.
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 5-33
ADDR
11
AS
17
R/W
UDS/LDS
28
29
DATA
31
DTACK
Figure 5-33. Pseudo-Asynchronous Read Cycle
During a write cycle, after the processor asserts AS but before driving the data bus, the
processor drives R/ W low. Parameter #55 specifies the minimum time between the
transition of R/W and the driving of the data bus, which is effectively the maximum turnoff
time for any device driving the data bus.
After the processor places valid data on the bus, it asserts the data strobe signal(s). A
data setup time, similar to the address setup time previously discussed, can be used to
improve performance. Parameter #29 is the minimum time a slave device can accept valid
data before recognizing a data strobe. The slave device asserts DTACK after it accepts
the data. Parameter #25 is the minimum time after negation of the strobes during which
the valid data remains on the address bus. Parameter #28 is the maximum time between
the negation of the strobes by the processor and the negation of DTACK by the slave
device. If DTACK remains asserted past the time specified by parameter #28, the
processor may recognize it as being asserted early in the next bus cycle and may
terminate that cycle prematurely. Figure 5-34 shows the important timing specifications for
a pseudo-asynchronous write cycle.
5-34 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA
ADDR
11
AS
20A
R/W
22
UDS/LDS
28
29
DATA
DTACK
55
26
Figure 5-34. Pseudo-Asynchronous Write Cycle
In the MC68010, the BERR signal can be delayed after the assertion of DTACK.
Specification #48 is the maximum time between assertion of DTACK and assertion of
BERR. If this maximum delay is exceeded, operation of the processor may be erratic.
5.8 SYNCHRONOUS OPERATION
In some systems, external devices use the system clock to generate DTACK and other
asynchronous input signals. This synchronous operation provides a closely coupled
design with maximum performance, appropriate for frequently accessed parts of the
system. For example, memory can operate in the synchronous mode, but peripheral
devices operate asynchronously. For a synchronous device, the designer uses explicit
timing information shown in Section 10 Electrical Characteristics. These specifications
define the state of all bus signals relative to a specific state of the processor clock.
The standard M68000 bus cycle consists of four clock periods (eight bus cycle states)
and, optionally, an integral number of clock cycles inserted as wait states. Wait states are
inserted as required to allow sufficient response time for the external device. The following
state-by-state description of the bus cycle differs from those descriptions in 5.1.1 READ
CYCLE and 5.1.2 WRITE CYCLE by including information about the important timing
parameters that apply in the bus cycle states.
STATE 0 The bus cycle starts in S0, during which the clock is high. At the rising edge
of S0, the function code for the access is driven externally. Parameter #6A
defines the delay from this rising edge until the function codes are valid.
Also, the R/ W signal is driven high; parameter #18 defines the delay from
the same rising edge to the transition of R/W . The minimum value for
parameter #18 applies to a read cycle preceded by a write cycle; this value
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 5-35
is the maximum hold time for a low on R/ W beyond the initiation of the read
cycle.
STATE 1 Entering S1, a low period of the clock, the address of the accessed device
is driven externally with an assertion delay defined by parameter #6.
STATE 2 On the rising edge of S2, a high period of the clock, AS is asserted. During
a read cycle, UDS, LDS, and/or DS is also asserted at this time. Parameter
#9 defines the assertion delay for these signals. For a write cycle, the R/W
signal is driven low with a delay defined by parameter #20.
STATE 3 On the falling edge of the clock entering S3, the data bus is driven out of
the high-impedance state with the data being written to the accessed
device (in a write cycle). Parameter #23 specifies the data assertion delay.
In a read cycle, no signal is altered in S3.
STATE 4 Entering the high clock period of S4, UDS, LDS, and/or DS is asserted
(during a write cycle) on the rising edge of the clock. As in S2 for a read
cycle, parameter #9 defines the assertion delay from the rising edge of S4
for UDS, LDS, and/or DS . In a read cycle, no signal is altered by the
processor during S4.
Until the falling edge of the clock at the end of S4 (beginning of S5), no
response from any external device except RESET is acknowledged by the
processor. If either DTACK or BERR is asserted before the falling edge of
S4 and satisfies the input setup time defined by parameter #47, the
processor enters S5 and the bus cycle continues. If either DTACK or BERR
is asserted but without meeting the setup time defined by parameter #47,
the processor may recognize the signal and continue the bus cycle; the
result is unpredictable. If neither DTACK nor BERR is asserted before the
next rise of clock, the bus cycle remains in S4, and wait states (complete
clock cycles) are inserted until one of the bus cycle termination is met.
STATE 5 S5 is a low period of the clock, during which the processor does not alter
any signal.
STATE 6 S6 is a high period of the clock, during which data for a read operation is
set up relative to the falling edge (entering S7). Parameter #27 defines the
minimum period by which the data must precede the falling edge. For a
write operation, the processor changes no signal during S6.
STATE 7 On the falling edge of the clock entering S7, the processor latches data
and negates AS and UDS, LDS, and/or DS during a read cycle. The hold
time for these strobes from this falling edge is specified by parameter #12.
The hold time for data relative to the negation of AS and UDS, LDS, and/or
DS is specified by parameter #29. For a write cycle, only AS and UDS, LDS,
and/or DS are negated; timing parameter #12 also applies.
5-36 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA
On the rising edge of the clock, at the end of S7 (which may be the start of
S0 for the next bus cycle), the processor places the address bus in the
high-impedance state. During a write cycle, the processor also places the
data bus in the high-impedance state and drives R/ W high. External logic
circuitry should respond to the negation of the AS and UDS, LDS, and/or DS
by negating DTACK and/or BERR. Parameter #28 is the hold time for
DTACK, and parameter #30 is the hold time for BERR.
Figure 5-35 shows a synchronous read cycle and the important timing parameters that
apply. The timing for a synchronous read cycle, including relevant timing parameters, is
shown in Figure 5-36.
S0 S1 S2 S3 S4 S5 S6 S7 S0
CLOCK
6
ADDR
9
AS
UDS/LDS
18
R/W
47
DTACK
27
DATA
Figure 5-35. Synchronous Read Cycle
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 5-37
CLOCK
S0 S1 S2 S3 S4 S5 S6 S7 S0
DQG
EXT
S
L
DQGDQGCLK
CLK
INT
S
L
6
ADDR
AS
UDS/LDS
18
R/W
DTACK
DATA
.
9
47
23 53
Figure 5-36. Synchronous Write Cycle
A key consideration when designing in a synchronous environment is the timing for the
assertion of DTACK and BERR by an external device. To properly use external inputs, the
processor must synchronize these signals to the internal clock. The processor must
sample the external signal, which has no defined phase relationship to the CPU clock,
which may be changing at sampling time, and must determine whether to consider the
signal high or low during the succeeding clock period. Successful synchronization requires
that the internal machine receives a valid logic level (not a metastable signal), whether the
input is high, low, or in transition. Metastable signals propagating through synchronous
machines can produce unpredictable operation.
Figure 5-37 is a conceptual representation of the input synchronizers used by the M68000
Family processors. The input latches allow the input to propagate through to the output
when E is high. When low, E latches the input. The three latches require one cycle of CLK
to synchronize an external signal. The high-gain characteristics of the devices comprising
the latches quickly resolve a marginal signal into a valid state.
IGNA
IGNA
Figure 5-37. Input Synchronizers
5-38 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA
Parameter #47 of Section 10 Electrical Characteristics is the asynchronous input setup
time. Signals that meet parameter #47 are guaranteed to be recognized at the next falling
edge of the system clock. However, signals that do not meet parameter #47 are not
guaranteed to be recognized. In addition, if DTACK is recognized on a falling edge, valid
data is latched into the processor (during a read cycle) on the next falling edge, provided
the data meets the setup time required (parameter #27). When parameter #27 has been
met, parameter #31 may be ignored. If DTACK is asserted with the required setup time
before the falling edge of S4, no wait states are incurred, and the bus cycle runs at its
maximum speed of four clock periods.
The late BERR in an MC68010 that is operating in a synchronous mode must meet setup
time parameter #27A. That is, when BERR is asserted after DTACK, BERR must be
asserted before the falling edge of the clock, one clock cycle after DTACK is recognized.
Violating this requirement may cause the MC68010 to operate erratically.
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 5-39
SECTION 6
EXCEPTION PROCESSING
This section describes operations of the processor outside the normal processing
associated with the execution of instructions. The functions of the bits in the supervisor
portion of the status register are described: the supervisor/user bit, the trace enable bit,
and the interrupt priority mask. Finally, the sequence of memory references and actions
taken by the processor for exception conditions are described in detail.
The processor is always in one of three processing states: normal, exception, or halted.
The normal processing state is associated with instruction execution; the memory
references are to fetch instructions and operands and to store results. A special case of
the normal state is the stopped state, resulting from execution of a STOP instruction. In
this state, no further memory references are made.
An additional, special case of the normal state is the loop mode of the MC68010,
optionally entered when a test condition, decrement, and branch (DBcc) instruction is
executed. In the loop mode, only operand fetches occur. See Appendix A MC68010
Loop Mode Operation.
The exception processing state is associated with interrupts, trap instructions, tracing, and
other exceptional conditions. The exception may be internally generated by an instruction
or by an unusual condition arising during the execution of an instruction. Externally,
exception processing can be forced by an interrupt, by a bus error, or by a reset.
Exception processing provides an efficient context switch so that the processor can
handle unusual conditions.
The halted processing state is an indication of catastrophic hardware failure. For example,
if during the exception processing of a bus error another bus error occurs, the processor
assumes the system is unusable and halts. Only an external reset can restart a halted
processor. Note that a processor in the stopped state is not in the halted state, nor vice
versa.
6.1 PRIVILEGE MODES
The processor operates in one of two levels of privilege: the supervisor mode or the user
mode. The privilege mode determines which operations are legal. The mode is optionally
used by an external memory management device to control and translate accesses. The
mode is also used to choose between the supervisor stack pointer (SSP) and the user
stack pointer (USP) in instruction references.
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL 6-1
The privilege mode is a mechanism for providing security in a computer system. Programs
should access only their own code and data areas and should be restricted from
accessing information that they do not need and must not modify. The operating system
executes in the supervisor mode, allowing it to access all resources required to perform
the overhead tasks for the user mode programs. Most programs execute in user mode, in
which the accesses are controlled and the effects on other parts of the system are limited.
6.1.1 Supervisor Mode
The supervisor mode has the higher level of privilege. The mode of the processor is
determined by the S bit of the status register; if the S bit is set, the processor is in the
supervisor mode. All instructions can be executed in the supervisor mode. The bus cycles
generated by instructions executed in the supervisor mode are classified as supervisor
references. While the processor is in the supervisor mode, those instructions that use
either the system stack pointer implicitly or address register seven explicitly access the
SSP.
6.1.2 User Mode
The user mode has the lower level of privilege. If the S bit of the status register is clear,
the processor is executing instructions in the user mode.
Most instructions execute identically in either mode. However, some instructions having
important system effects are designated privileged. For example, user programs are not
permitted to execute the STOP instruction or the RESET instruction. To ensure that a user
program cannot enter the supervisor mode except in a controlled manner, the instructions
that modify the entire status register are privileged. To aid in debugging systems software,
the move to user stack pointer (MOVE to USP) and move from user stack pointer (MOVE
from USP) instructions are privileged.
NOTE
To implement virtual machine concepts in the MC68010, the
move from status register (MOVE from SR), move to/from
control register (MOVEC), and move alternate address space
(MOVES) instructions are also privileged.
The bus cycles generated by an instruction executed in user mode are classified as user
references. Classifying a bus cycle as a user reference allows an external memory
management device to translate the addresses of and control access to protected portions
of the address space. While the processor is in the user mode, those instructions that use
either the system stack pointer implicitly or address register seven explicitly access the
USP.
6.1.3 Privilege Mode Changes
Once the processor is in the user mode and executing instructions, only exception
processing can change the privilege mode. During exception processing, the current state
of the S bit of the status register is saved, and the S bit is set, putting the processor in the
6-2 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA
supervisor mode. Therefore, when instruction execution resumes at the address specified
to process the exception, the processor is in the supervisor privilege mode.
NOTE
The transition from supervisor to user mode can be
accomplished by any of four instructions: return from exception
(RTE) (MC68010 only), move to status register (MOVE to SR),
AND immediate to status register (ANDI to SR), and exclusive
OR immediate to status register (EORI to SR). The RTE
instruction in the MC68010 fetches the new status register and
program counter from the supervisor stack and loads each into
its respective register. Next, it begins the instruction fetch at
the new program counter address in the privilege mode
determined by the S bit of the new contents of the status
register.
The MOVE to SR, ANDI to SR , and EORI to SR instructions fetch all operands in the
supervisor mode, perform the appropriate update to the status register, and then fetch the
next instruction at the next sequential program counter address in the privilege mode
determined by the new S bit.
6.1.4 Reference Classification
When the processor makes a reference, it classifies the reference according to the
encoding of the three function code output lines. This classification allows external
translation of addresses, control of access, and differentiation of special processor states,
such as CPU space (used by interrupt acknowledge cycles). Table 6-1 lists the
classification of references.
Table 6-1. Reference Classification
Function Code Output
FC2 FC1 FC0 Address Space
0 0 0 (Undefined, Reserved)*
0 0 1 User Data
0 1 0 User Program
0 1 1 (Undefined, Reserved)*
1 0 0 (Undefined, Reserved)*
1 0 1 Supervisor Data
1 1 0 Supervisor Program
1 1 1 CPU Space
*Address space 3 is reserved for user definition, while 0 and
4 are reserved for future use by Motorola.
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL 6-3
6.2 EXCEPTION PROCESSING
NEW PROGRAM COUNTER (HIGH)
NEW PROGRAM COUNTER (LOW)
A1=0
A1=1
WORD 0
WORD 1
EVEN BYTE (A0=0)
EVEN BYTE (A0=0)
The processing of an exception occurs in four steps, with variations for different exception
causes:
1. Make a temporary copy of the status register and set the status register for
exception processing.
2. Obtain the exception vector.
3. Save the current processor context.
4. Obtain a new context and resume instruction processing.
6.2.1 Exception Vectors
An exception vector is a memory location from which the processor fetches the address of
a routine to handle an exception. Each exception type requires a handler routine and a
unique vector. All exception vectors are two words in length (see Figure 6-1), except for
the reset vector, which is four words long. All exception vectors reside in the supervisor
data space, except for the reset vector, which is in the supervisor program space. A vector
number is an 8-bit number that is multiplied by four to obtain the offset of an exception
vector. Vector numbers are generated internally or externally, depending on the cause of
the exception. For interrupts, during the interrupt acknowledge bus cycle , a peripheral
provides an 8-bit vector number (see Figure 6-2) to the processor on data bus lines D7–
D0.
The processor forms the vector offset by left-shifting the vector number two bit positions
and zero-filling the upper-order bits to obtain a 32-bit long-word vector offset. In the
MC68000, the MC68HC000, MC68HC001, MC68EC000, and the MC68008, this offset is
used as the absolute address to obtain the exception vector itself, which is shown in
Figure 6-3.
NOTE
In the MC68010, the vector offset is added to the 32-bit vector
base register (VBR) to obtain the 32-bit absolute address of
the exception vector (see Figure 6-4). Since the VBR is set to
zero upon reset, the MC68010 functions identically to the
MC68000, MC68HC000, MC68HC001, MC68EC000, and
MC68008 until the VBR is changed via the move control
register MOVEC instruction.
6-4 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA
Figure 6-1. Exception Vector Format
D15 D8 D7 D0
31310010
ALL ZEROES
CONTENTS OF VECTOR BASE REGISTER
v7v6v5v4v3v2v1v00
0
EXCEPTION VECTOR
+
IGNORED v7 v6 v5 v 4 v 3 v 2 v1 v0
Where:
v7 is the MSB of the vector number
v0 is the LSB of the vector number
Figure 6-2. Peripheral Vector Number Format
A31 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
ALL ZEROES v 7 v6 v5 v4 v3 v2 v1 v0 0 0
Figure 6-3. Address Translated from 8-Bit Vector Number
(MC68000, MC68HC000, MC68HC001, MC68EC000, and MC68008)
ADDRESS
Figure 6-4. Exception Vector Address Calculation (MC68010)
The actual address on the address bus is truncated to the number of address bits
available on the bus of the particular implementation of the M68000 architecture. In all
processors except the MC68008, this is 24 address bits. (A0 is implicitly encoded in the
data strobes.) In the MC68008, the address is 20 or 22 bits in length. The memory map for
exception vectors is shown in Table 6-2.
The vector table, Table 6-2, is 512 words long (1024 bytes), starting at address 0
(decimal) and proceeding through address 1023 (decimal). The vector table provides 255
unique vectors, some of which are reserved for trap and other system function vectors. Of
the 255, 192 are reserved for user interrupt vectors. However, the first 64 entries are not
protected, so user interrupt vectors may overlap at the discretion of the systems designer.
6.2.2 Kinds of Exceptions
Exceptions can be generated by either internal or external causes. The externally
generated exceptions are the interrupts, the bus error, and reset. The interrupts are
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL 6-5
requests from peripheral devices for processor action; the bus error and reset inputs are
used for access control and processor restart. The internal exceptions are generated by
instructions, address errors, or tracing. The trap (TRAP), trap on overflow (TRAPV), check
register against bounds (CHK), and divide (DIV) instructions can generate exceptions as
part of their instruction execution. In addition, illegal instructions, word fetches from odd
addresses, and privilege violations cause exceptions. Tracing is similar to a very high
priority, internally generated interrupt following each instruction.
6-6 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA
Table 6-2. Exception Vector Assignment
Vectors Numbers Address
Hex Decimal Dec Hex Space
0 0 0 000 SP
1 1 4 004 SP
2 2 8 008 SD Bus Error
3 3 12 00C SD Address Error
4 4 16 010 SD Illegal Instruction
5 5 20 014 S D Zero Divide
6 6 24 018 SD CHK Instruction
7 7 28 01C SD TRAPV Instruction
8 8 32 020 SD Privilege Violation
9 9 36 024 SD Trace
A 10 40 028 SD Line 1010 Emulator
B 11 44 02C SD Line 1111 Emulator
C
D
E 14 56 038 SD
F 15 60 03C SD Uninitialized Interrupt Vector
10–17
18 24 96 060 SD
19 25 100 064 SD Level 1 Interrupt Autovector
1A 26 104 068 SD Level 2 Interrupt Autovector
1B 27 108 06C SD Level 3 Interrupt Autovector
1C 28 112 070 SD Level 4 Interrupt Autovector
1D 29 116 074 SD Level 5 Interrupt Autovector
1E 30 120 078 SD Level 6 Interrupt Autovector
1F 31 124 07C SD Level 7 Interrupt Autovector
20–2F 32–47 128 080 SD
30–3F
40–FF 64–255 256 100 SD User Interrupt Vectors
NOTES:
1. Vector numbers 12, 13, 16–23, and 48–63 are reserved for future
2. Reset vector (0) requires four words, unlike the other vectors which only
3. The spurious interrupt vector is taken when there is a bus error
4. TRAP #n uses vector number 32+ n.
5. MC68010 only. This vector is unassigned, reserved on the MC68000
6. SP denotes supervisor program space, and SD denotes
1
12
1
13
16–23
48–63
enhancements by Motorola. No user peripheral devices should be
assigned these numbers.
require two words, and is located in the supervisor program space.
indication during interrupt processing.
and MC68008.
supervisor data space.
48 030 SD (Unassigned, Reserved)
52 034 SD (Unassigned, Reserved)
1
64 040 SD (Unassigned, Reserved)
92 05C —
188 0BC —
1
192 0C0 SD (Unassigned, Reserved)
255 0FF —
1020 3FC —
6
Reset: Initial SSP
Reset: Initial PC
Format Error
Spurious Interrupt
TRAP Instruction Vectors
Assignment
5
2
2
3
4
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL 6-7
6.2.3 Multiple Exceptions
These paragraphs describe the processing that occurs when multiple exceptions arise
simultaneously. Exceptions can be grouped by their occurrence and priority. The group 0
exceptions are reset, bus error, and address error. These exceptions cause the instruction
currently being executed to abort and the exception processing to commence within two
clock cycles. The group 1 exceptions are trace and interrupt, privilege violations, and
illegal instructions. Trace and interrupt exceptions allow the current instruction to execute
to completion, but pre-empt the execution of the next instruction by forcing exception
processing to occur. A privilege-violating instruction or an illegal instruction is detected
when it is the next instruction to be executed. The group 2 exceptions occur as part of the
normal processing of instructions. The TRAP, TRAPV, CHK, and zero divide exceptions
are in this group. For these exceptions, the normal execution of an instruction may lead to
exception processing.
Group 0 exceptions have highest priority, whereas group 2 exceptions have lowest
priority. Within group 0, reset has highest priority, followed by address error and then bus
error. Within group 1, trace has priority over external interrupts, which in turn takes priority
over illegal instruction and privilege violation. Since only one instruction can be executed
at a time, no priority relationship applies within group 2.
The priority relationship between two exceptions determines which is taken, or taken first,
if the conditions for both arise simultaneously. Therefore, if a bus error occurs during a
TRAP instruction, the bus error takes precedence, and the TRAP instruction processing is
aborted. In another example, if an interrupt request occurs during the execution of an
instruction while the T bit is asserted, the trace exception has priority and is processed
first. Before instruction execution resumes, however, the interrupt exception is also
processed, and instruction processing finally commences in the interrupt handler routine.
A summary of exception grouping and priority is given in Table 6-3.
As a general rule, the lower the priority of an exception, the sooner the handler routine for
that exception executes. For example, if simultaneous trap, trace, and interrupt exceptions
are pending, the exception processing for the trap occurs first, followed immediately by
exception processing for the trace and then for the interrupt. When the processor resumes
normal instruction execution, it is in the interrupt handler, which returns to the trace
handler, which returns to the trap execution handler. This rule does not apply to the reset
exception; its handler is executed first even though it has the highest priority, because the
reset operation clears all other exceptions.
6-8 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA
Table 6-3. Exception Grouping and Priority
Group Exception Processing
0 Reset
Address Error
Bus Error
1 Trace
Interrupt
Illegal
Privilege
2 TRAP, TRAPV,
CHK
Zero Divide
Exception Processing Begins within Two Clock Cycles
Exception Processing Begins before the Next Instruction
Exception Processing Is Started by Normal Instruction Execution
6.2.4 Exception Stack Frames
Exception processing saves the most volatile portion of the current processor context on
the top of the supervisor stack. This context is organized in a format called the exception
stack frame. Although this information varies with the particular processor and type of
exception, it always includes the status register and program counter of the processor
when the exception occurred.
The amount and type of information saved on the stack are determined by the processor
type and exception type. Exceptions are grouped by type according to priority of the
exception.
Of the group 0 exceptions, the reset exception does not stack any information. The
information stacked by a bus error or address error exception in the MC68000,
MC68HC000, MC68HC001, MC68EC000, or MC68008 is described in 6.3.9.1 Bus Error
and shown in Figure 6-7.
The MC68000, MC68HC000, MC68HC001, MC68EC000, and MC68008 group 1 and 2
exception stack frame is shown in Figure 6-5. Only the program counter and status
register are saved. The program counter points to the next instruction to be executed after
exception processing.
The MC68010 exception stack frame is shown in Figure 5-6. The number of words
actually stacked depends on the exception type. Group 0 exceptions (except reset) stack
29 words and group 1 and 2 exceptions stack four words. To support generic exception
handlers, the processor also places the vector offset in the exception stack frame. The
format code field allows the return from exception (RTE) instruction to identify what
information is on the stack so that it can be properly restored. Table 6-4 lists the MC68010
format codes. Although some formats are specific to a particular M68000 Family
processor, the format 0000 is always legal and indicates that just the first four words of the
frame are present.
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL 6-9
EVEN BYTE
ODD BYTE
PROGRAM COUNTER LOW
PROGRAM COUNTER HIGH
SSP7070015
STATUS REGISTER
HIGHER
A
DDRES
S
PROGRAM COUNTER LOW
PROGRAM COUNTER HIGH
SP015
STATUS REGISTER
HIGHER
A
S
VECTOR OFFSET
FORMAT
OTHER INFORMATION
DEPENDING ON EXCEPTION
Figure 6-5. Group 1 and 2 Exception Stack Frame
(MC68000, MC68HC000, MC68HC001, MC68EC000, and MC68008)
DDRES
Figure 6-6. MC68010 Stack Frame
6-10 M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL MOTOROLA
Table 6-4. MC68010 Format Codes
Format Code Stacked Information
0000 Short Format (4 Words)
1000 Long Format (29 Words)
All Others Unassigned, Reserved
6.2.5 Exception Processing Sequence
In the first step of exception processing , an internal copy is made of the status register.
After the copy is made, the S bit of the status register is set, putting the processor into the
supervisor mode. Also, the T bit is cleared, which allows the exception handler to execute
unhindered by tracing. For the reset and interrupt exceptions, the interrupt priority mask is
also updated appropriately.
In the second step, the vector number of the exception is determined. For interrupts, the
vector number is obtained by a processor bus cycle classified as an interrupt acknowledge
cycle. For all other exceptions, internal logic provides the vector number. This vector
number is then used to calculate the address of the exception vector.
The third step, except for the reset exception, is to save the current processor status. (The
reset exception does not save the context and skips this step.) The current program
counter value and the saved copy of the status register are stacked using the SSP. The
stacked program counter value usually points to the next unexecuted instruction.
However, for bus error and address error, the value stacked for the program counter is
unpredictable and may be incremented from the address of the instruction that caused the
error. Group 1 and 2 exceptions use a short format exception stack frame (format = 0000
on the MC68010). Additional information defining the current context is stacked for the bus
error and address error exceptions.
The last step is the same for all exceptions. The new program counter value is fetched
from the exception vector. The processor then resumes instruction execution. The
instruction at the address in the exception vector is fetched, and normal instruction
decoding and execution is started.
6.3 PROCESSING OF SPECIFIC EXCEPTIONS
The exceptions are classified according to their sources, and each type is processed
differently. The following paragraphs describe in detail the types of exceptions and the
processing of each type.
6.3.1 Reset
The reset exception corresponds to the highest exception level. The processing of the
reset exception is performed for system initiation and recovery from catastrophic failure.
Any processing in progress at the time of the reset is aborted and cannot be recovered.
The processor is forced into the supervisor state, and the trace state is forced off. The
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL 6- 11
interrupt priority mask is set at level 7. In the MC68010, the VBR is forced to zero. The
vector number is internally generated to reference the reset exception vector at location 0
in the supervisor program space. Because no assumptions can be made about the validity
of register contents, in particular the SSP, neither the program counter nor the status
register is saved. The address in the first two words of the reset exception vector is
fetched as the initial SSP, and the address in the last two words of the reset exception
vector is fetched as the initial program counter. Finally, instruction execution is started at
the address in the program counter. The initial program counter should point to the powerup/restart code.
The RESET instruction does not cause a reset exception; it asserts the RESET signal to
reset external devices, which allows the software to reset the system to a known state and
continue processing with the next instruction.
6.3.2 Interrupts
Seven levels of interrupt priorities are provided, numbered from 1–7. All seven levels are
available except for the 48-pin version for the MC68008.
NOTE
The MC68008 48-pin version supports only three interrupt
levels: 2, 5, and 7. Level 7 has the highest priority.
Devices can be chained externally within interrupt priority levels, allowing an unlimited
number of peripheral devices to interrupt the processor. The status register contains a 3bit mask indicating the current interrupt priority, and interrupts are inhibited for all priority
levels less than or equal to the current priority.
An interrupt request is made to the processor by encoding the interrupt request levels 1–7
on the three interrupt request lines; all lines negated indicates no interrupt request.
Interrupt requests arriving at the processor do not force immediate exception processing,
but the requests are made pending. Pending interrupts are detected between instruction
executions. If the priority of the pending interrupt is lower than or equal to the current
processor priority, execution continues with the next instruction, and the interrupt
exception processing is postponed until the priority of the pending interrupt becomes
greater than the current processor priority.
If the priority of the pending interrupt is greater than the current processor priority, the
exception processing sequence is started. A copy of the status register is saved; the
privilege mode is set to supervisor mode; tracing is suppressed; and the processor priority
level is set to the level of the interrupt being acknowledged. The processor fetches the
vector number from the interrupting device by executing an interrupt acknowledge cycle,
which displays the level number of the interrupt being acknowledged on the address bus.
If external logic requests an automatic vector, the processor internally generates a vector
number corresponding to the interrupt level number. If external logic indicates a bus error,
the interrupt is considered spurious, and the generated vector number references the
spurious interrupt vector. The processor then proceeds with the usual exception
processing, saving the format/offset word (MC68010 only), program counter, and status
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register on the supervisor stack. The offset value in the format/offset word on the
MC68010 is the vector number multiplied by four. The format is all zeros. The saved value
of the program counter is the address of the instruction that would have been executed
had the interrupt not been taken. The appropriate interrupt vector is fetched and loaded
into the program counter, and normal instruction execution commences in the interrupt
handling routine. Priority level 7 is a special case. Level 7 interrupts cannot be inhibited by
the interrupt priority mask, thus providing a "nonmaskable interrupt" capability. An interrupt
is generated each time the interrupt request level changes from some lower level to level
7. A level 7 interrupt may still be caused by the level comparison if the request level is a 7
and the processor priority is set to a lower level by an instruction.
6.3.3 Uninitialized Interrupt
An interrupting device provides an M68000 interrupt vector number and asserts data
transfer acknowledge (DTACK) , or asserts valid peripheral address (VPA) , or auto vector
(AVEC), or bus error (BERR) during an interrupt acknowledge cycle by the MC68000. If
the vector register has not been initialized, the responding M68000 Family peripheral
provides vector number 15, the uninitialized interrupt vector. This response conforms to a
uniform way to recover from a programming error.
6.3.4 Spurious Interrupt
During the interrupt acknowledge cycle, if no device responds by asserting DTACK or
AVEC, VPA, BERR should be asserted to terminate the vector acquisition. The processor
separates the processing of this error from bus error by forming a short format exception
stack and fetching the spurious interrupt vector instead of the bus error vector. The
processor then proceeds with the usual exception processing.
6.3.5 Instruction Traps
Traps are exceptions caused by instructions; they occur when a processor recognizes an
abnormal condition during instruction execution or when an instruction is executed that
normally traps during execution.
Exception processing for traps is straightforward. The status register is copied; the
supervisor mode is entered; and tracing is turned off. The vector number is internally
generated; for the TRAP instruction, part of the vector number comes from the instruction
itself. The format/offset word (MC68010 only), the program counter, and the copy of the
status register are saved on the supervisor stack. The offset value in the format/offset
word on the MC68010 is the vector number multiplied by four. The saved value of the
program counter is the address of the instruction following the instruction that generated
the trap. Finally, instruction execution commences at the address in the exception vector.
Some instructions are used specifically to generate traps. The TRAP instruction always
forces an exception and is useful for implementing system calls for user programs. The
TRAPV and CHK instructions force an exception if the user program detects a run-time
error, which may be an arithmetic overflow or a subscript out of bounds.
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL 6- 13
A signed divide (DIVS) or unsigned divide (DIVU ) instruction forces an exception if a
division operation is attempted with a divisor of zero.
6.3.6 Illegal and Unimplemented Instructions
Illegal instruction is the term used to refer to any of the word bit patterns that do not match
the bit pattern of the first word of a legal M68000 instruction. If such an instruction is
fetched, an illegal instruction exception occurs. Motorola reserves the right to define
instructions using the opcodes of any of the illegal instructions. Three bit patterns always
force an illegal instruction trap on all M68000-Family-compatible microprocessors. The
patterns are: $4AFA, $4AFB, and $4AFC. Two of the patterns, $4AFA and $4AFB, are
reserved for Motorola system products. The third pattern, $4AFC, is reserved for customer
use (as the take illegal instruction trap (ILLEGAL) instruction).
NOTE
In addition to the previously defined illegal instruction opcodes,
the MC68010 defines eight breakpoint (BKPT) instructions with
the bit patterns $4848–$484F. These instructions cause the
processor to enter illegal instruction exception processing as
usual. However, a breakpoint acknowledge bus cycle, in which
the function code lines (FC2–FC0) are high and the address
lines are all low, is also executed before the stacking
operations are performed. The processor does not accept or
send any data during this cycle. Whether the breakpoint
acknowledge cycle is terminated with a DTACK, BERR, or VPA
signal, the processor continues with the illegal instruction
processing. The purpose of this cycle is to provide a software
breakpoint that signals to external hardware when it is
executed.
Word patterns with bits 15–12 equaling 1010 or 1111 are distinguished as unimplemented
instructions, and separate exception vectors are assigned to these patterns to permit
efficient emulation. Opcodes beginning with bit patterns equaling 1111 (line F) are
implemented in the MC68020 and beyond as coprocessor instructions. These separate
vectors allow the operating system to emulate unimplemented instructions in software.
Exception processing for illegal instructions is similar to that for traps. After the instruction
is fetched and decoding is attempted, the processor determines that execution of an illegal
instruction is being attempted and starts exception processing. The exception stack frame
for group 2 is then pushed on the supervisor stack, and the illegal instruction vector is
fetched.
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6.3.7 Privilege Violations
To provide system security, various instructions are privileged. An attempt to execute one
of the privileged instructions while in the user mode causes an exception. The privileged
instructions are as follows:
AND Immediate to SR MOVE USP
EOR Immediate to SR OR Immediate to SR
MOVE to SR (68010 only) RESET
MOVE from SR (68010 only) RTE
MOVEC (68010 only) STOP
MOVES (68010 only)
Exception processing for privilege violations is nearly identical to that for illegal
instructions. After the instruction is fetched and decoded and the processor determines
that a privilege violation is being attempted, the processor starts exception processing.
The status register is copied; the supervisor mode is entered; and tracing is turned off.
The vector number is generated to reference the privilege violation vector, and the current
program counter and the copy of the status register are saved on the supervisor stack. If
the processor is an MC68010, the format/offset word is also saved. The saved value of
the program counter is the address of the first word of the instruction causing the privilege
violation. Finally, instruction execution commences at the address in the privilege violation
exception vector.
6.3.8 Tracing
To aid in program development, the M68000 Family includes a facility to allow tracing
following each instruction. When tracing is enabled, an exception is forced after each
instruction is executed. Thus, a debugging program can monitor the execution of the
program under test.
The trace facility is controlled by the T bit in the supervisor portion of the status register. If
the T bit is cleared (off), tracing is disabled and instruction execution proceeds from
instruction to instruction as normal. If the T bit is set (on) at the beginning of the execution
of an instruction, a trace exception is generated after the instruction is completed. If the
instruction is not executed because an interrupt is taken or because the instruction is
illegal or privileged, the trace exception does not occur. The trace exception also does not
occur if the instruction is aborted by a reset, bus error, or address error exception. If the
instruction is executed and an interrupt is pending on completion, the trace exception is
processed before the interrupt exception. During the execution of the instruction, if an
exception is forced by that instruction, the exception processing for the instruction
exception occurs before that of the trace exception.
As an extreme illustration of these rules, consider the arrival of an interrupt during the
execution of a TRAP instruction while tracing is enabled. First, the trap exception is
processed, then the trace exception, and finally the interrupt exception. Instruction
execution resumes in the interrupt handler routine.
MOTOROLA M68000 8-/16-/32-BIT MICROPROCESSORS USER’S MANUAL 6- 15
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