MOTOROLA LP2951CDMR2, LP2951CP1-005, LP2951CN-3.3, LP2951CN-3.0, LP2951CN Datasheet

 Semiconductor Components Industries, LLC, 1999

October, 1999 – Rev. 5

1 Publication Order Number:

LP2950/D

LP2950

Micropower V oltage
Regulators

The LP2950 and LP2951 are micropower voltage regulators that are
specifically designed to maintain proper regulation with an extremely
low input–to–output voltage differential. These devices feature a very
low quiescent bias current of 75 µA and are capable of supplying
output currents in excess of 100 mA. Internal current and thermal
limiting protection is provided.

The LP2951 has three additional features. The first is the Error
Output that can be used to signal external circuitry of an out of
regulation condition, or as a microprocessor power–on reset. The
second feature allows the output voltage to be preset to 5.0 V, 3.3 V or

3.0 V output (depending on the version) or programmed from 1.25 V
to 29 V. It consists of a pinned out resistor divider along with direct
access to the Error Amplifier feedback input. The third feature is a
Shutdown input that allows a logic level signal to turn–off or turn–on
the regulator output.

Due to the low input–to–output voltage differential and bias current
specifications, these devices are ideally suited for battery powered
computer, consumer , and industrial equipment where an extension of
useful battery life is desirable. The LP2950 is available in the three
pin case 29 and DPAK packages, and the LP2951 is available in the
eight pin dual–in–line, SO–8 and Micro–8 surface mount packages.
The ‘A’ suffix devices feature an initial output voltage tolerance
±0.5%.

LP2950 and LP2951 Features:

• Low Quiescent Bias Current of 75 µA

• Low Input–to–Output Voltage Differential of 50 mV at 100 µA and

380 mV at 100 mA

• 5.0 V, 3.3 V or 3.0 V ±0.5% Allows Use as a Regulator or Reference

• Extremely Tight Line and Load Regulation

• Requires Only a 1.0 µF Output Capacitor for Stability

• Internal Current and Thermal Limiting

LP2951 Additional Features:

• Error Output Signals an Out of Regulation Condition

• Output Programmable from 1.25 V to 29 V

• Logic Level Shutdown Input

(See Following Page for Device Information.)

TO–92

Z SUFFIX

CASE 29

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See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.

ORDERING INFORMATION

PIN CONNECTIONS

2

3

1

Pin: 1. Output

2. Ground

3. Input

DPAK

DT SUFFIX

CASE 369A

3

1

Heatsink surface (shown as terminal 4 in

case outline drawing) is connected to Pin 2.

123

(Top View)

Pin: 1. Input

2. Ground

3. Output

8

1

8

1

8

1

PIN CONNECTIONS

18

7
6
5

2
3
4

(Top View)

Output

Sense

Shutdown

Input
Feedback

Error

Output

VO Tap

Gnd

SO–8

D SUFFIX

CASE 751

N SUFFIX

CASE 626

Micro–8
DM SUFFIX
CASE 846A

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DEVICE INFORMATION

Output Voltage

Operating Junction

Package

3.0V 3.3V 5.0V Adjustable

Operating Junction

Temperature Range

TO–92
Suffix Z

LP2950CZ–3.0
LP2950ACZ–3.0

LP2950CZ–3.3
LP2950ACZ–3.3

LP2950CZ–5.0
LP2950ACZ–5.0

Not
Available

TJ = –40° to +125°C

DPAK
Suffix DT

LP2950CDT–3.0
LP2950ACDT–3.0

LP2950CDT–3.3
LP2950ACDT–3.3

LP2950CDT–5.0
LP2950ACDT–5.0

Not
Available

TJ = –40° to +125°C

SO–8
Suffix D

LP2951CD–3.0
LP2951ACD–3.0

LP2951CD–3.3
LP2951ACD–3.3

LP2951CD
LP2951ACD

LP2951CD
LP2951ACD

TJ = –40° to +125°C

Micro–8
Suffix DM

LP2951CDM–3.0
LP2951ACDM–3.0

LP2951CDM–3.3
LP2951ACDM–3.3

LP2951CDM
LP2951ACDM

LP2951CDM
LP2951ACDM

TJ = –40° to +125°C

DIP–8
Suffix N

LP2951CN–3.0
LP2951ACN–3.0

LP2951CN–3.3
LP2951ACN–3.3

LP2951CN
LP2951ACN

LP2951CN
LP2951ACN

TJ = –40° to +125°C

LP2950Cx–xx / LP2951Cxx–xx 1% Output Voltage Precision at TJ = 25°C
LP2950ACx–xx / LP2951ACxx–xx 0.5% Output Voltage Precision at TJ = 25°C

From
CMOS/TTL

3

Representative Block Diagrams

This device contains 34 active transistors.

LP2950CZ–5.0

Battery or

Unregulated DC

Gnd 2

Output

5.0 V/100 mA

1

Input

3

1.23 V

Reference

Error Amplifier

182 k

60 k

1.0 µF

Gnd 4

182 k

60 k

1.23 V

Reference

1.0 µF

LP2951CD or CN

Error

Amplifier

Battery or

Unregulated DC

Shutdown

Error
Output

5

VO Tap

Feedback

6

7

Input 8 Output

1

Sense 2

5.0 V/100 mA

330 k

T o CMOS/TTL

75 mV/

60 mV

Error Detection

Comparator

50 k

60 k

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MAXIMUM RATINGS (T

A

= 25°C, unless otherwise noted.)

Rating Symbol Value Unit

Input Voltage

V

CC

30

Vdc

Power Dissipation and Thermal Characteristics

Maximum Power Dissipation P

D

Internally Limited W

Case 751(SO–8) D Suffix

Thermal Resistance, Junction–to–Ambient R

θJA

180 °C/W

Thermal Resistance, Junction–to–Case R

θJC

45 °C/W

Case 369A (DPAK) DT Suf fix [Note 1]

Thermal Resistance, Junction–to–Ambient R

θJA

92 °C/W

Thermal Resistance, Junction–to–Case R

θJC

6.0 °C/W

Case 29 (TO–226AA/TO–92) Z Suffix

Thermal Resistance, Junction–to–Ambient R

θJA

160 °C/W

Thermal Resistance, Junction–to–Case R

θJC

83 °C/W

Case 626 N Suffix

Thermal Resistance, Junction–to–Ambient R

θJA

105 °C/W

Case 846A (Micro–8) DM Suffix

Thermal Resistance, Junction–to–Ambient R

θJA

240 °C/W

Feedback Input Voltage

V

fb

–1.5 to +30

Vdc

Shutdown Input Voltage

V

sd

–0.3 to +30

Vdc

Error Comparator Output Voltage

V

err

–0.3 to +30

Vdc

Operating Junction Temperature

T

J

–40 to +125

°C

Storage Temperature Range

T

stg

–65 to +150

°C

NOTE: 1.The Junction–to–Ambient Thermal Resistance is determined by PC board copper area per Figure 26.

2.ESD data available upon request.

ELECTRICAL CHARACTERISTICS (V

in

= VO + 1.0 V, IO = 100 µA, CO = 1.0 µF, TJ = 25°C [Note 1], unless

otherwise noted.)

Characteristic

Symbol Min Typ Max Unit

Output Voltage, 5.0 V Versions V

O

V

Vin = 6.0 V, IO = 100 µA, TJ = 25°C

LP2950C–5.0/LP2951C 4.950 5.000 5.050
LP2950AC–5.0/LP2951AC 4.975 5.000 5.025

TJ = –40 to +125°C

LP2950C–5.0/LP2951C 4.900 – 5.100
LP2950AC–5.0/LP2951AC 4.940 – 5.060

Vin = 6.0 to 30 V, IO = 100 µA to 100 mA, TJ = –40 to +125°C

LP2950C–5.0/LP2951C 4.880 – 5.120
LP2950AC–5.0/LP2951AC 4.925 – 5.075

Output Voltage, 3.3 V Versions V

O

V

Vin = 4.3 V, IO = 100 µA, TJ = 25°C

LP2950C–3.3/LP2951C–3.3 3.267 3.300 3.333
LP2950AC–3.3/LP2951AC–3.3 3.284 3.300 3.317

TJ = –40 to +125°C

LP2950C–3.3/LP2951C–3.3 3.234 – 3.366
LP2950AC–3.3/LP2951AC–3.3 3.260 – 3.340

Vin = 4.3 to 30 V, IO = 100 µA to 100 mA, TJ = –40 to +125°C

LP2950C–3.3/LP2951C–3.3 3.221 – 3.379
LP2950AC–3.3/LP2951AC–3.3 3.254 – 3.346

Output Voltage, 3.0 V Versions V

O

V

Vin = 4.0 V, IO = 100 µA, TJ = 25°C

LP2950C–3.0/LP2951C–3.0 2.970 3.000 3.030
LP2950AC–3.0/LP2951AC–3.0 2.985 3.000 3.015

TJ = –40 to +125°C

LP2950C–3.0/LP2951C–3.0 2.940 – 3.060
LP2950AC–3.0/LP2951AC–3.0 2.964 – 3.036

Vin = 4.0 to 30 V, IO = 100 µA to 100 mA, TJ = –40 to +125°C

LP2950C–3.0/LP2951C–3.0 2.928 – 3.072
LP2950AC–3.0/LP2951AC–3.0 2.958 – 3.042

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ELECTRICAL CHARACTERISTICS (continued) (V

in

= VO + 1.0 V, IO = 100 µA, CO = 1.0 µF, TJ = 25°C [Note 1], unless

otherwise noted.)

Characteristic UnitMaxTypMinSymbol

Line Regulation (Vin = V

O(nom)

+1.0 V to 30 V) [Note 2] Reg

line

%
LP2950C–XX/LP2951C/LP2951C–XX – 0.08 0.20
LP2950AC–XX/LP2951AC/LP2951AC–XX – 0.04 0.10

Load Regulation (IO = 100 µA to 100 mA) Reg

load

%
LP2950C–XX/LP2951C/LP2951C–XX – 0.13 0.20
LP2950AC–XX/LP2951AC/LP2951AC–XX – 0.05 0.10

Dropout Voltage VI – V

O

mV
IO = 100 µA – 30 80
IO = 100 mA – 350 450

Supply Bias Current I

CC

IO = 100 µA – 93 120 µA
IO = 100 mA – 4.0 12 mA

Dropout Supply Bias Current (Vin = V

O(nom)

– 0.5 V,

IO = 100 µA) [Note 2]

I

CCdropout

– 110 170 µA

Current Limit (VO Shorted to Ground) I

Limit

– 220 300 mA

Thermal Regulation Reg

thermal

– 0.05 0.20 %/W

Output Noise Voltage (10 Hz to 100 kHz) [Note 3] V

n

µVrms
CL = 1.0 µF – 126 –
CL = 100 µF – 56 –

LP2951A/LP2951AC ONL Y

Reference Voltage (TJ = 25°C) V

ref

V
LP2951C/LP2951C–XX 1.210 1.235 1.260
LP2951AC/LP2951AC–XX 1.220 1.235 1.250

Reference Voltage (TJ = –40 to +125°C) V

ref

V
LP2951C/LP2951C–XX 1.200 – 1.270
LP2951AC/LP2951AC–XX 1.200 – 1.260

Reference Voltage (TJ = –40 to +125°C) V

ref

V
IO = 100 µA to 100 mA, Vin = 23 to 30 V

LP2951C/LP2951C–XX 1.185 – 1.285
LP2951AC/LP2951AC–XX 1.190 – 1.270

Feedback Pin Bias Current I

FB

– 15 40 nA

ERROR COMPARATOR

Output Leakage Current (VOH = 30 V) I

lkg

– 0.01 1.0 µA

Output Low Voltage (Vin = 4.5 V, IOL = 400 µA) V

OL

– 150 250 mV

Upper Threshold Voltage (Vin = 6.0 V) V

thu

40 45 – mV

Lower Threshold Voltage (Vin = 6.0 V) V

thl

– 60 95 mV

Hysteresis (Vin = 6.0 V) V

hy

– 15 – mV

SHUTDOWN INPUT

Input Logic Voltage V

shtdn

V
Logic “0” (Regulator “On”) 0 – 0.7
Logic “1” (Regulator “Off”) 2.0 – 30

Shutdown Pin Input Current I

shtdn

µA

V

shtdn

= 2.4 V – 35 50

V

shtdn

= 30 V – 450 600

Regulator Output Current in Shutdown Mode I

off

– 3.0 10 µA

(Vin = 30 V, V

shtdn

= 2.0 V, VO = 0, Pin 6 Connected to Pin 7)

NOTES: 1.Low duty pulse techniques are used during test to maintain junction temperature as close to ambient as possible.

2.V

O(nom)

is the part number voltage option.

3.

Noise tests on the LP2951 are made with a 0.01 µF capacitor connected across Pins 7 and 1.

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DEFINITIONS

Dropout Voltage – The input/output voltage differential

at which the regulator output no longer maintains regulation
against further reductions in input voltage. Measured when
the output drops 100 mV below its nominal value (which is
measured at 1.0 V differential), dropout voltage is affected
by junction temperature, load current and minimum input
supply requirements.

Line Regulation – The change in output voltage for a

change in input voltage. The measurement is made under
conditions of low dissipation or by using pulse techniques
such that average chip temperature is not significantly
affected.

Load Regulation – The change in output voltage for a

change in load current at constant chip temperature.

Maximum Power Dissipation – The maximum total

device dissipation for which the regulator will operate
within specifications.

Bias Current – Current which is used to operate the

regulator chip and is not delivered to the load.

Output Noise V oltage – The rms ac voltage at the output,

with constant load and no input ripple, measured over a
specified frequency range.

Leakage Current – Current drawn through a bipolar

transistor collector–base junction, under a specified
collector voltage, when the transistor is “off”.

Upper Threshold Voltage – Voltage applied to the

comparator input terminal, below the reference voltage
which is applied to the other comparator input terminal,
which causes the comparator output to change state from a
logic “0” to “1”.

Lower Threshold Voltage – Voltage applied to the

comparator input terminal, below the reference voltage
which is applied to the other comparator input terminal,
which causes the comparator output to change state from a
logic “1” to “0”.

Hysteresis – The difference between Lower Threshold

voltage and Upper Threshold voltage.

Figure 1. Quiescent Current

, OUTPUT VOLTAGE (V)
V

out

, OUTPUT VOLTAGE (V)

V

out

–50

5.00

0

6.0

0

250

0.1

10

TA, AMBIENT TEMPERATURE (°C)

Vin, INPUT VOLTAGE (V)

B

IA

S

C

U

RRE

N

T

( A)µ

Vin, INPUT VOLTAGE (V)

LP

29

5

0

/LP

29

51

B

IA

S

C

U

RRE

N

T

(mA)

IL, LOAD CURRENT (mA)

Figure 2. Dropout Characteristics

Figure 3. Input Current Figure 4. Output Voltage versus Temperature

1.0 10 100 1.0 2.0 3.0 4.0 5.0 6.0

5.0 10 15 20 25 0 50 100 150

1.0

0.1

0.01

5.0

4.0

3.0

2.0

1.0

0

4.99

4.98

4.97

4.96

4.95

200

150

100

50

0

RL = 50 k

RL = 50 Ω

0.1 mA Load Current

No Load

LP2951C

TA = 25°C

LP2951C

200

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R

L

DROPOUT VOLTAGE (mV) = 50

T , TEMPERATURE (°C)

0

200

0

8.0

–50

550

–100

7.0

4.70

5.0

0.1

400

LOAD CURRENT (mA)

t, TIME (ms)

, INPUT VOLTAGE (V)

t, TIME (µs)

SHUTDOWN AND OUTPUT VOLT AGE (V)

t, TIME (µs)

, OUTPUT VOLTAGE (V)

Vin, INPUT VOLTAGE (V)

DROPOUT VOLTAGE (mV)

Figure 5. Dropout Voltage versus

Output Current

IO, OUTPUT CURRENT (mA)

Figure 6. Dropout Voltage versus Temperature

Figure 7. Error Comparator Output Figure 8. Line Transient Response

Figure 9. LP2951 Enable Transient Figure 10. Load Transient Response

1.0 10 100 0 50 100 150

4.74 4.78 4.82 4.86 100 200 3004.90 400 500 600 700 800

0 100 200 300 400 40025050 150 200 300 350100

300

200

0

500

450

400

300

7.5

7.0

6.5

6.0

5.5

4.0

3.0

1.0

0

5.0

3.0

1.0

–1.0

150

100

0

–50

50

RL = 50

Vin Decreasing

Vin Increasing

V

in

V

out

RL = 50 k

TA = 25°C
CL = 1.0 µF
IL = 1.0 mA
VO = 5.0 V

CL = 1.0 µF
V

out

= 5.0 V

TA = 25°C

V

out

I

Load

TA = 25°C
IL = 10 mA
Vin = 8.0 V
V

out

= 5.0 V

CL = 10 µF

Shutdown Input

350

R

L

DROPOUT VOLTAGE (mV) = 50 k

55

50

45

40

30

35

350

250

150
100

2.0

OUTPUT VOLTAGE CHANGE (mV)

4.0

2.0

0

– 2.0

– 6.0

– 4.0

OUTPUT VOLTAGE CHANGE (mV)

0

– 200

200

400

– 400

6.0

4.0

2.0

0

50

V

in

V

out

CL = 1.0 µF

TA = 25°C

LP2951C
RL = 330 k
TA = 25°C

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0

100

100

4.0

–40

1.8

1.0

80

V

out

, OUTPUT CURRENT (mA)

Vin, INPUT VOLTAGE (V)

VOLTAGE NOISE ( V/ Hz)√

f, FREQUENCY (Hz)

SH

U

T

DOWN

THRESH

O

L

D VO

LT

AG

E

(V)

t, TEMPERATURE (°C)

R

I

PPLE

RE

J

ECT

ION (d

B

)

Figure 11. Ripple Rejection

f, FREQUENCY (Hz)

Figure 12. Output Noise

Figure 13. Shutdown Threshold Voltage

versus Temperature

Figure 14. Maximum Rated

Output Current

TA = 25°C
CL = 1.0 µF
Vin = 6.0 V
V

out

= 5.0 V

CL = 1.0 µF

µ

CL = 100 µF

IL= 0.1 mA

IL= 100 mA
TA = 25°C
VO = 5.0 V
LP2951C

Output “Off”

Output “On”

TA = 25°C

LP2951CN

60

40

20

0

3.0

2.0

1.0

0

80

60

40

20

0

1.4

1.0

0.8

1.2

1.6

10 100

1.0 k

10 k 100 k

1.0 k

10 k 100 k

– 20 40 80 120 160 5.0 15 25 35 4010 20 3060 100 140200

TA = 75°C

4.0

2.0

0

– 2.0

– 4.0

– 6.0

OU

TP

U

T

VO

LT

AG

E

CH

ANG

E

(mV)

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APPLICATIONS INFORMATION

Introduction

The LP2950/LP2951 regulators are designed with
internal current limiting and thermal shutdown making them
user–friendly. Typical application circuits for the LP2950
and LP2951 are shown in Figures 17 through 25.

These regulators are not internally compensated and thus
require a 1.0 µF (or greater) capacitance between the
LP2950/LP2951 output terminal and ground for stability.
Most types of aluminum, tantalum or multilayer ceramic
will perform adequately. Solid tantalums or appropriate
multilayer ceramic capacitors are recommended for
operation below 25°C.

At lower values of output current, less output capacitance
is required for output stability. The capacitor can be reduced
to 0.33 µF for currents less than 10 mA, or 0.1 µF for currents
below 1.0 mA. Using the 8–pin versions at voltages less than

5.0 V operates the error amplifier at lower values of gain, so
that more output capacitance is needed for stability . For the
worst case operating condition of a 100 mA load at 1.23 V
output (Output Pin 1 connected to the feedback Pin 7) a
minimum capacitance of 3.3 µF is recommended.

The LP2950 will remain stable and in regulation when
operated with no output load. When setting the output
voltage of the LP2951 with external resistors, the resistance
values should be chosen to draw a minimum of 1.0 µA.

A bypass capacitor is recommended across the
LP2950/LP2951 input to ground if more than 4 inches of
wire connects the input to either a battery or power supply
filter capacitor.

Input capacitance at the LP2951 Feedback Pin 7 can
create a pole, causing instability if high value external
resistors are used to set the output voltage. Adding a 100 pF
capacitor between the Output Pin 1 and the Feedback Pin 7
and increasing the output filter capacitor to at least 3.3 µF
will stabilize the feedback loop.

Error Detection Comparator

The comparator switches to a positive logic low whenever
the LP2951 output voltage falls more than approximately

5.0% out of regulation. This value is the comparator’s
designed–in offset voltage of 60 mV divided by the 1.235 V
internal reference. As shown in the representative block
diagram. This trip level remains 5.0% below normal
regardless of the value of regulated output voltage. For
example, the error flag trip level is 4.75 V for a normal 5.0
V regulated output, or 9.50 V for a 10 V output voltage.

Figure 1 is a timing diagram which shows the ERROR
signal and the regulated output voltage as the input voltage

to the LP2951 is ramped up and down. The ERROR signal
becomes valid (low) at about 1.3 V input. It goes high when
the input reaches about 5.0 V (V

out

exceeds about 4.75 V).
Since the LP2951’s dropout voltage is dependent upon the
load current (refer to the curve in the Typical Performance
Characteristics), the input voltage trip point will vary with
load current. The output voltage trip point does not vary
with load.

The error comparator output is an open collector which
requires an external pull–up resistor. This resistor may be
returned to the output or some other voltage within the
system. The resistance value should be chosen to be
consistent with the 400 µA sink capability of the error
comparator. A value between 100 k and 1.0 MΩ is
suggested. No pull–up resistance is required if this output is
unused.

When operated in the shutdown mode, the error
comparator output will go high if it has been pulled up to an
external supply. To avoid this invalid response, the error
comparator output should be pulled up to V

out

(see

Figure 15).

Figure 15. ERROR Output Timing

5.0 V

4.75 V

4.70 V

4.75 V + V

dropout

4.70 V + V

dropout

1.3 V

1.3 V

Not
Valid

Pull–Up
to V

out

Pull–Up
to Ext

Output

Voltage

ERROR

Input

Voltage

Not

Valid

Programming the Output Voltage (LP2951)

The LP2951CX may be pin–strapped for 5.0 V using its
internal voltage divider by tying Pin 1 (output) to Pin 2
(sense) and Pin 7 (feedback) to Pin 6 (5.0 V tap).
Alternatively , it may be programmed for any output voltage
between its 1.235 reference voltage and its 30 V maximum
rating. An external pair of resistors is required, as shown in
Figure 16.

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Figure 16. Adjustable Regulator

Error

Output

Shutdown

Input

V

in

V

out

1.23 to 30 V

3.3 µF

0.01 µF

NC

NC

R

2

R1

100 k

5

3

Error

SD

Gnd FB

47

6

VO T

SNS

2

V

out

V

in

8

1

The complete equation for the output voltage is:

V

out

+

V

ref

(

1)R1ńR2))

IFBR1

where V

ref

is the nominal 1.235 V reference voltage and I

FB

is the feedback pin bias current, nominally – 20 nA. The
minimum recommended load current of 1.0 µA forces an
upper limit of 1.2 MΩ on the value of R2, if the regulator
must work with no load. IFB will produce a 2% typical error
in V

out

which may be eliminated at room temperature by
adjusting R1. For better accuracy, choosing R2 = 100 k
reduces this error to 0.17% while increasing the resistor
program current to 12 µA. Since the LP2951 typically draws
75 µA at no load with Pin 2 open circuited, the extra 12 µA
of current drawn is often a worthwhile tradeoff for
eliminating the need to set output voltage in test.

Output Noise

In many applications it is desirable to reduce the noise
present at the output. Reducing the regulator bandwidth by
increasing the size of the output capacitor is the only method
for reducing noise on the 3 lead LP2950. However,
increasing the capacitor from 1.0 µF to 220 µF only

decreases the noise from 430 µV to 160 µV rms for a 100 kHz
bandwidth at the 5.0 V output.

Noise can be reduced fourfold by a bypass capacitor
across R1, since it reduces the high frequency gain from 4
to unity. Pick

C

Bypass

[

1

2pR1 x 200 Hz

or about 0.01 µF . When doing this, the output capacitor must
be increased to 3.3 µF to maintain stability. These changes
reduce the output noise from 430 µV to 126 µVrms for a
100 kHz bandwidth at 5.0 V output. With bypass
capacitor added, noise no longer scales with output voltage
so that improvements are more dramatic at higher output
voltages.

Figure 17. 1.0 A Regulator with 1.2 V Dropout

0.01 µF

10 k

MTB23P06E

1.0 µF

Unregulated

Input

Error

Output

Shutdown

Input

V

out

5.0 V ±1.0%
0 to 1.0 A

220 µF

2.0 k

5

3

Error

SD

Gnd FB

47

6

VO T

SNS

2

V

out

V

in

8

1

0.002 µF

1.0 M

LP2951CN

LP2950

http://onsemi.com

10

TYPICAL APPLICATIONS

Figure 18. Lithium Ion Battery Cell Charger

1N4001

Gnd

4.2 V ± 0.025 V

NC

NC

50 k

5

3

Error

SD

Gnd FB

47

6

VO T

SNS

2

V

out

V

in

8

1

0.1 µF

NC

LP2951CN

2.2 µF

330 pF

806 k

1.0%

2.0 M

1.0%

Lithium Ion
Rechargeable
Cell

Unregulated Input

6.0 to 10 Vdc

Figure 19. Low Drift Current Sink

Error

Output

Shutdown

Input

+V = 2.0 to 30 V

1.0 µF

R

5

3

Error

SD

Gnd FB

47

6

VO T

SNS

2

V

out

V

in

8

1

0.1 µF

Load

IL = 1.23/R

I

L

Figure 20. Latch Off When Error Flag Occurs

Reset

+V

in

V

out

1.0 µF

NC

NC

R2

R1

470 k

5

3

Error

SD

Gnd FB

47

6

VO T

SNS

2

V

out

V

in

8

1

LP2951CN

470 k

Error flag occurs when Vin is too low to
maintain V

out

, or if V

out

is reduced by

excessive load current.

Normally

Closed

2N3906

Figure 21. 5.0 V Regulator with 2.5 V Sleep Function

*Sleep

Input

+V

in

V

out

3.3 µF

NC

NC

100 k

100 k

470 k

5

3

Error

SD

Gnd FB

47

6

VO T

SNS

2

V

out

V

in

8

1

LP2951CN

200 k

100 pF

2N3906

47 k

CMOS
Gate

Error

Output

Shutdown

Input

LP2951CN

LP2950

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11

330 k

Figure 22. Regulator with Early Warning and Auxiliary Output

+V

in

Memory
V+

1.0 µF

20

5

3

Error

SD

Gnd FB

47

6

VO T

SNS

2

V

out

V

in

8

1

LP2951CN

#1

1.0 µF

5

3

Error

SD

Gnd FB

47

6

VO T

SNS

2

V

out

V

in

8

1

LP2951CN

#2

NC

Reset

V

DD

µP

Early Warning

All diodes are 1N4148.
Early Warning flag on low input voltage.
Main output latches off at lower input

voltages.
Battery backup on auxiliary output.
Operation: Regulator #1’s V

out

is
programmed one diode drop above 5.0 V.
Its error flag becomes active when Vin <

5.7
V. When Vin drops below 5.3 V, the error
flag of regulator #2 becomes active and via
Q1 latches the main output “off”. When V

in

again exceeds 5.7 V, regulator #1 is back in
regulation and the early warning signal
rises, unlatching regulator #2 via D3.

D4

2.7 M

Q1

2N3906

D2

D1

D3

27 k

3.6 V
NiCad

Main
Output

Figure 23. 2.0 A Low Dropout Regulator

+V

in

V

out

@ 2.0 A

100 µF

NC

NC

R2

R1

470

5

3

Error

SD

Gnd FB

47

6

VO T

SNS

2

V

out

V

in

8

1

LP2951CN

MJE2955

4.7 M

Error

Flag

V

out

= 1.25V (1.0 + R1/R2)

For 5.0 V output, use internal resistors. Wire Pin 6 to 7,
and wire Pin 2 to +V

out

Bus.

20 k

47

4.7 µF
Tant

0.05

680

0.033 µF

2N3906

10 k

Current Limit
Section

220

1000 µF

.33 µF

.01 µF

2N3906

LP2950

http://onsemi.com

12

Figure 24. Open Circuit Detector for 4.0 to 20 mA Current Loop

5

3

Error

SD

Gnd FB

47

6

VO T

SNS

2

V

out

V

in

8

1

LP2951CN

NC

Output*

0.1 µF

NC

NC

NC

1N457

1N457

360

1N457

1N4001

24

+5.0 V

4.7 k

15

20 mA4

* High for
IL < 3.5 mA

Figure 25. Low Battery Disconnect

2N3906

5

3

Error

SD

Gnd FB

47

6

VO T

SNS

2

V

out

V

in

8

1

LP2951CN

NC

1.0 µF

NC

2

3

1

20

Main V+

Memory V+

6.0 V Lead–Acid
Battery

NiCad Backup
Battery

100 k

31.6 k

MC34164P–5

NC

R , THERMAL RESISTANCE

JAθ

JUNCTION-TO-AIR ( C/W)°

40

50

60

70

80

90

100

0

0.4

0.8

1.2

1.6

2.0

2.4

010203025155.0
L, LENGTH OF COPPER (mm)

P

D(max)

for TA = 50°C

Minimum
Size Pad

P

D

L

L

, MAXIMUM POWER DISSIPATION (W)

Free Air
Mounted
Vertically

R

θJA

2.0 oz. Copper

Figure 26. DPAK Thermal Resistance and Maximum

Power Dissipation versus P.C.B. Copper Length

LP2950

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13

ORDERING INFORMATION

Part Number Package Shipping

LP2950CZ–3.0RA TO–92 2000 units / Tape & Reel
LP2950ACZ–3.0RA TO–92 2000 units / Tape & Reel
LP2950CZ–3.3RA TO–92 2000 units / Tape & Reel
LP2950ACZ–3.3RA TO–92 2000 units / Tape & Reel
LP2950CZ–5.0RA TO–92 2000 units / Tape & Reel
LP2950ACZ–5.0RA TO–92 2000 units / Tape & Reel
LP2950CDT–3.0 DPAK 75 units / Rail
LP2950CDT–3.0RK DPAK 2500 units / Tape & Reel
LP2950ACDT–3.0 DPAK 75 units / Rail
LP2950ACDT–3.0RK DPAK 2500 units / Tape & Reel
LP2950CDT–3.3 DPAK 75 units / Rail
LP2950CDT–3.3RK DPAK 2500 units / Tape & Reel
LP2950ACDT–3.3 DPAK 75 units / Rail
LP2950ACDT–3.3RK DPAK 2500 units / Tape & Reel
LP2950CDT–5.0 DPAK 75 units / Rail
LP2950CDT–5.0RK DPAK 2500 units / Tape & Reel
LP2950ACDT–5.0 DPAK 75 units / Rail
LP2950ACDT–5.0RK DPAK 2500 units / Tape & Reel

LP2951CD–3.0 SO–8 98 units / Rail
LP2951CD–3.0R2 SO–8 2500 units / Tape & Reel
LP2951ACD–3.0 SO–8 98 units / Rail
LP2951ACD–3.0R2 SO–8 2500 units / Tape & Reel
LP2951CD–3.3 SO–8 98 units / Rail
LP2951CD–3.3R2 SO–8 2500 units / Tape & Reel
LP2951ACD–3.3 SO–8 98 units / Rail
LP2951ACD–3.3R2 SO–8 2500 units / Tape & Reel
LP2951CD SO–8 98 units / Rail
LP2951CDR2 SO–8 2500 units / Tape & Reel
LP2951ACD SO–8 98 units / Rail
LP2951ACDR2 SO–8 2500 units / Tape & Reel
LP2951CDM–3.0R2 Micro–8 2500 units / Tape & Reel
LP2951ACDM–3.0R2 Micro–8 2500 units / Tape & Reel
LP2951CDM–3.3R2 Micro–8 2500 units / Tape & Reel
LP2951ACDM–3.3R2 Micro–8 2500 units / Tape & Reel
LP2951CDMR2 Micro–8 2500 units / Tape & Reel
LP2951ACDMR2 Micro–8 2500 units / Tape & Reel
LP2951CN–3.0 DIP–8 50 units / Rail
LP2951ACN–3.0 DIP–8 50 units / Rail
LP2951CN–3.3 DIP–8 50 units / Rail
LP2951ACN–3.3 DIP–8 50 units / Rail
LP2951CN DIP–8 50 units / Rail
LP2951ACN DIP–8 50 units / Rail

LP2950

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14

P ACKAGE DIMENSIONS

Z SUFFIX

(TO–226AA/TO–92)

PLASTIC PACKAGE

CASE 29–04

ISSUE AD

DT SUFFIX

(DPAK)

PLASTIC PACKAGE

CASE 369A–13

ISSUE Y

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. CONTOUR OF PACKAGE BEYOND DIMENSION R
IS UNCONTROLLED.

4. DIMENSION F APPLIES BETWEEN P AND L.
DIMENSION D AND J APPLY BETWEEN L AND K
MINIMUM. LEAD DIMENSION IS UNCONTROLLED
IN P AND BEYOND DIMENSION K MINIMUM.

R

A

P

J

L

F

B

K

G

H

SECTION X–X

C

V

D

N

N

XX

SEATING
PLANE

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.175 0.205 4.45 5.20
B 0.170 0.210 4.32 5.33
C 0.125 0.165 3.18 4.19
D 0.016 0.022 0.41 0.55

F 0.016 0.019 0.41 0.48
G 0.045 0.055 1.15 1.39
H 0.095 0.105 2.42 2.66

J 0.015 0.020 0.39 0.50
K 0.500 ––– 12.70 –––

L 0.250 ––– 6.35 –––
N 0.080 0.105 2.04 2.66

P ––– 0.100 ––– 2.54
R 0.115 ––– 2.93 –––

V 0.135 ––– 3.43 –––

1

D

A

K

B
R

V

S

F

L

G

2 PL

M

0.13 (0.005) T

E

C

U

J

H

–T–

SEATING
PLANE

Z

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.235 0.250 5.97 6.35
B 0.250 0.265 6.35 6.73
C 0.086 0.094 2.19 2.38
D 0.027 0.035 0.69 0.88
E 0.033 0.040 0.84 1.01
F 0.037 0.047 0.94 1.19
G 0.180 BSC 4.58 BSC
H 0.034 0.040 0.87 1.01
J 0.018 0.023 0.46 0.58
K 0.102 0.114 2.60 2.89
L 0.090 BSC 2.29 BSC
R 0.175 0.215 4.45 5.46
S 0.020 0.050 0.51 1.27
U 0.020 ––– 0.51 –––
V 0.030 0.050 0.77 1.27
Z 0.138 ––– 3.51 –––

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

123

4

LP2950

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15

P ACKAGE DIMENSIONS

N SUFFIX

PLASTIC PACKAGE

CASE 626–05

ISSUE K

D SUFFIX

(SO–8)

PLASTIC PACKAGE

CASE 751–05

ISSUE R

NOTES:

1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.

2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).

3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

MIN MINMAX MAX

MILLIMETERS INCHES

DIM

9.40

6.10

3.94

0.38

1.02

0.76

0.20

2.92
–

0.76

10.16

6.60

4.45

0.51

1.78

1.27

0.30

3.43

0.370

0.240

0.155

0.015

0.040

0.030

0.008

0.115
–

0.030

0.400

0.260

0.175

0.020

0.070

0.050

0.012

0.135

10°

1.01

2.54 BSC

7.62 BSC

0.100 BSC

0.300 BSC

A
B
C
D
F
G
H
J
K
L
M
N

10°

0.040

F

H

G

D

N

C

K

M

J

L

NOTE 2

1

4

58

T

0.13 (0.005)

AB

M M M

–A–

–B–

–T–

SEATING

PLANE

SEATING
PLANE

1

4

58

A0.25MCB

SS

0.25MB

M

h

q

C

X 45

_

L

DIM MIN MAX

MILLIMETERS

A 1.35 1.75

A1 0.10 0.25

B 0.35 0.49
C 0.18 0.25
D 4.80 5.00
E

1.27 BSCe

3.80 4.00

H 5.80 6.20

h

0 7

L 0.40 1.25

q

0.25 0.50

__

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.

2. DIMENSIONS ARE IN MILLIMETERS.

3. DIMENSION D AND E DO NOT INCLUDE MOLD
PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.

D

E

H

A

B

e

B

A1

C

A

0.10

LP2950

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16

P ACKAGE DIMENSIONS

DM SUFFIX

(Micro–8)

PLASTIC PACKAGE

CASE 846A–02

ISSUE C

S

B

M

0.08 (0.003) A

S

T

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 2.90 3.10 0.114 0.122
B 2.90 3.10 0.114 0.122
C ––– 1.10 ––– 0.043
D 0.25 0.40 0.010 0.016

G 0.65 BSC 0.026 BSC

H 0.05 0.15 0.002 0.006
J 0.13 0.23 0.005 0.009
K 4.75 5.05 0.187 0.199
L 0.40 0.70 0.016 0.028

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.

–B–

–A–

D

K

G

PIN 1 ID

8 PL

0.038 (0.0015)

–T–

SEATING
PLANE

C

H

J

L

USA/EUROPE Literature Fulfillment:

Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA

Phone: [phone] or 800–344–3860 T oll Free USA/Canada
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*To receive a Fax of our publications

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ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes

without further notice to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability ,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer .

PUBLICATION ORDERING INFORMATION

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Phone: [phone] (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)
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Phone: [phone]
Email: [e-mail]

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For additional information, please contact your local Sales Representative.

LP2950/D