Motorola MCM6729DWJ10R, MCM6729DWJ12, MCM6729DWJ8, MCM6729DWJ12R, MCM6729DWJ8R Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

256K x 4 Bit Fast Static Random
Access Memory

The MCM6729D is a 1,048,576 bit static random access memory organized
as 262,144 words of 4 bits. Static design eliminates the need for external clocks
or timing strobes.

Output enable (G
flexibility and eliminates bus contention problems.

This device meets JEDEC standards for functionality and revolutionary pinout,
and is available in a 400 mil plastic small–outline J–leaded package.

• Single 5 V ± 10% Power Supply

• Fully Static — No Clock or Timing Strobes Necessary

• All Inputs and Outputs Are TTL Compatible

• Three State Outputs

• Fast Access Times: 8, 10, 12 ns

• Center Power and I/O Pins for Reduced Noise

A
A
A
A
A
A
A
A
A

) is a special control feature that provides increased system

BLOCK DIAGRAM

V

CC

VSS

ROW

DECODER

MEMORY

MATRIX

512 ROWS x 512 x 4

COLUMNS

Order this document

by MCM6729D/D

MCM6729D

WJ PACKAGE

400 MIL SOJ

CASE 857A–02

PIN ASSIGNMENT

NC A

1

A

2

A

3

A

4

A

5

E

6

DQ

7

V

8

CC

V

9

SS

DQ

10

W

11

A

12

A

13

A

14

A

15

NC NC

16

32
31
30

29
28
27

26
25
24
23

22
21
20
19
18
17

A
A
A
A
G
DQ
VSS
VCC
DQ
A
A

A
A
A

DQ

INPUT

DATA

CONTROL

DQ

E

W

G

10/9/96

 Motorola, Inc. 1996

MOTOROLA FAST SRAM

COLUMN I/O

COLUMN DECODER

AA A A A

A A A A

PIN NAMES

A Address Input. . . . . . . . . . . . . . . . . . . . .

E
W
G

DQ Data Input/Output. . . . . . . . . . . . . . .

V

CC

V

SS

NC No Connection. . . . . . . . . . . . . . . . . .

+ 5 V Power Supply. . . . . . . . . . . .

Chip Enable. . . . . . . . . . . . . . . . . . . . . .

Write Enable. . . . . . . . . . . . . . . . . . . .

Output Enable. . . . . . . . . . . . . . . . . . .

Ground. . . . . . . . . . . . . . . . . . . . . . .

MCM6729D

1

TRUTH TABLE (X = Don’t Care)

G W Mode VCC Current Output Cycle

E

H X X Not Selected I
L H H Output Disabled I
L L H Read I
L X L Write I

SB1

, I

CCA
CCA
CCA

SB2

High–Z —
High–Z —

D

out

High–Z Write Cycle

Read Cycle

ABSOLUTE MAXIMUM RATINGS (See Note)

Rating

Power Supply Voltage V
Voltage Relative to VSS for Any Pin Except

V

CC

Output Current I
Power Dissipation P
Temperature Under Bias T
Operating Temperature T
Storage Temperature — Plastic T

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are

exceeded. Functional operation should be restricted to RECOMMENDED OPER­ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.

Symbol Value Unit

CC

Vin, V

out

bias

stg

out

D

A

– 0.5 to + 7.0 V

– 0.5 to VCC + 0.5 V

±30 mA

1.2 W

– 10 to + 85 °C

0 to + 70 °C

– 55 to + 125 °C

This device contains circuitry to protect the in­puts against damage due to high static voltages
or electric fields; however, it is advised that nor­mal precautions be taken to avoid application of
any voltage higher than maximum rated volt­ages to these high–impedance circuits.
This BiCMOS memory circuit has been de­signed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board
and transverse air flow of at least 500 linear feet
per minute is maintained.

DC OPERA TING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Typ Max Unit

Supply Voltage (Operating Voltage Range) V
Input High Voltage V

Input Low Voltage V

*VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 2.0 ns) for I ≤ 20.0 mA.

**VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2 V ac (pulse width ≤ 2.0 ns) for I ≤ 20.0 mA.

CC

IH

IL

DC CHARACTERISTICS

Parameter Symbol Min Max Unit

Input Leakage Current (All Inputs, Vin = 0 to VCC) I
Output Leakage Current (E = VIH, V
Output Low Voltage (IOL = + 8.0 mA) V
Output High Voltage (IOH = – 4.0 mA) V

= 0 to VCC) I

out

POWER SUPPLY CURRENTS

Parameter Symbol 6729D–8 6729D–10 6729D–12 Unit Notes

AC Active Supply Current (I
Active Quiescent Current (E = VIL, VCC = max, f = 0 MHz) I
AC Standby Current (E = VIH, VCC = max, f = f
CMOS Standby Current (VCC = max, f = 0 MHz, E ≥ VCC – 0.2 V,

Vin ≤ VSS + 0.2 V, or ≥ VCC – 0.2 V)

NOTES:

1. Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3.0 V, VIH = 3.0 V).

2. All addresses transition simultaneously low (LSB) and then high (MSB).

3. Data states are all zero.

= 0 mA) (VCC = max, f = f

out

max

) I

max

) I

CCA

CC2
SB1

I

SB2

4.5 5.0 5.5 V

2.2 —

– 0.5*

lkg(I)

lkg(O)

OL

OH

195 165 155 mA 1, 2, 3

90 90 90 mA
60 60 60 mA 1, 2, 3
20 20 20 mA

— 0.8 V

— ± 1.0 µA
— ± 1.0 µA
— 0.4 V

2.4 — V

VCC + 0.3**

V

MCM6729D
2

MOTOROLA FAST SRAM

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T

Address Input Capacitance C
Control Pin Input Capacitance C
Input/Output Capacitance C

= 25°C, Periodically Sampled Rather Than 100% Tested)

A

Parameter

AC OPERA TING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ±10%, TA = 0 to +70°C, Unless Otherwise Noted)

Symbol Typ Max Unit

in
in

I/O

— 6 pF
— 6 pF
— 8 pF

Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .

Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time 2 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . .

Output Load See Figure 1a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

READ CYCLE TIMING (See Notes 1 and 2)

6729D–8 6729D–10 6729D–12

Parameter Symbol Min Max Min Max Min Max Unit Notes

Read Cycle Time t
Address Access Time t
Enable Access Time t
Output Enable Access Time t
Output Hold from Address Change t
Enable Low to Output Active t
Output Enable Low to Output Active t
Enable High to Output High–Z t
Output Enable High to Output High–Z t

NOTES:

1. W

is high for read cycle.

2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.

3. All read cycle timings are referenced from the last valid address to the first transitioning address.

4. At any given voltage and temperature, t
device to device.

5. Transition is measured 200 mV from steady–state voltage with load of Figure 1b.

6. This parameter is sampled and not 100% tested.

7. Device is continuously selected (E

8. Addresses valid prior to or coincident with E

= VIL, G = VIL).

EHQZ

going low.

(max) < t

AVAV
AVQV
ELQV
GLQV
AXQX
ELQX
GLQX
EHQZ

GHQZ

ELQX

(min), and t

8 — 10 — 12 — ns 3
— 8 — 10 — 12 ns
— 8 — 10 — 12 ns
— 4 — 5 — 6 ns

3 — 3 — 3 — ns

3 — 3 — 3 — ns 4,5,6

0 — 0 — 0 — ns 4,5,6
— 4 — 5 — 6 ns 4,5,6
— 4 — 5 — 6 ns 4,5,6

GHQZ

(max) < t

(min), both for a given device and from

GLQX

OUTPUT

Z0 = 50

Ω

(a) (b)

MOTOROLA FAST SRAM

RL = 50

VL = 1.5 V

Ω

+5 V

OUTPUT

255

Ω

Figure 1. AC Test Loads

480

5 pF

Ω

TIMING LIMITS

The table of timing values shows either a
minimum or a maximum limit for each param­eter. Input requirements are specified from
the external system point of view. Thus, ad­dress setup time is shown as a minimum
since the system must supply at least that
much time. On the other hand, responses
from the memory are specified from the de­vice point of view. Thus, the access time is
shown as a maximum since the device never
provides data later than that time.

MCM6729D

3