MOTOROLA HC05J5AGRS, HC05J5AGRH User Manual
查询68HC05J5A供应商
HC05J5AGRS/H
REV 2.1
68HC05J5A
68HRC05J5A
68HC705J5A
68HRC705J5A
SPECIFICATION
(General Release)
July 16, 1999
Semiconductor Products Sector
Motorola reserves the right to make changes without further notice to any products herein
to improve reliability, function or design. Motorola does not assume any liability arising out
of the application or use of any product or circuit described herein; neither does it convey
any license under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems intended for surgical
implant into the body, or other applications intended to support or sustain life, or for any
other application in which the failure of the Motorola product could create a situation
where personal injury or death may occur. Should Buyer purchase or use Motorola
products for any such unintended or unauthorized application, Buyer shall indemnify and
hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs, damages, and expenses, and reasonable attorney
fees arising out of, directly or indirectly, any claim of personal injury or death associated
with such unintended or unauthorized use, even if such claim alleges that Motorola was
negligent regarding the design or manufacture of the part.
Motorola, Inc., 1999
July 16, 1999 GENERAL RELEASE SPECIFICATION
TABLE OF CONTENTS
Section Page
SECTION 1
GENERAL DESCRIPTION
1.1 FEATURES...................................................................................................... 1-1
1.2 MASK OPTIONS..............................................................................................1-2
1.3 MCU STRUCTURE..........................................................................................1-2
1.4 PIN ASSIGNMENTS........................................................................................ 1-4
1.5 FUNCTIONAL PIN DESCRIPTION..................................................................1-4
1.5.1 V
AND V
DD
..............................................................................................1-4
SS
1.5.2 OSC1, OSC2/R............................................................................................1-4
1.5.3 RESET
1.5.4 IRQ
.........................................................................................................1-6
(MASKABLE INTERRUPT REQUEST)................................................1-6
1.5.5 PA0-PA7......................................................................................................1-6
1.5.6 PB0-PB5......................................................................................................1-7
SECTION 2
MEMORY
2.1 I/O AND CONTROL REGISTERS ...................................................................2-2
2.2 RAM.................................................................................................................2-2
2.3 ROM.................................................................................................................2-2
2.4 I/O REGISTERS SUMMARY...........................................................................2-3
SECTION 3
CENTRAL PROCESSING UNIT
3.1 REGISTERS ....................................................................................................3-1
3.2 ACCUMULATOR (A)........................................................................................3-2
3.3 INDEX REGISTER (X)..................................................................................... 3-2
3.4 STACK POINTER (SP).................................................................................... 3-2
3.5 PROGRAM COUNTER (PC) ...........................................................................3-2
3.6 CONDITION CODE REGISTER (CCR)...........................................................3-3
3.6.1 Half Carry Bit (H-Bit)....................................................................................3-3
3.6.2 Interrupt Mask (I-Bit)....................................................................................3-3
3.6.3 Negative Bit (N-Bit)......................................................................................3-3
3.6.4 Zero Bit (Z-Bit).............................................................................................3-3
3.6.5 Carry/Borrow Bit (C-Bit)...............................................................................3-4
SECTION 4
INTERRUPTS
4.1 CPU INTERRUPT PROCESSING...................................................................4-1
4.2 RESET INTERRUPT SEQUENCE ..................................................................4-2
4.3 SOFTWARE INTERRUPT (SWI).....................................................................4-3
4.4 HARDWARE INTERRUPTS............................................................................4-3
4.5 EXTERNAL INTERRUPT (IRQ).......................................................................4-3
4.5.1 IRQ CONTROL/STATUS REGISTER (ICSR) $0A......................................4-5
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TABLE OF CONTENTS
Section Page
4.5.2 OPTIONAL EXTERNAL INTERRUPTS (PA0-PA3) ....................................4-6
4.5.3 TIMER INTERRUPT (MFT).........................................................................4-7
4.5.4 TIMER1 INTERRUPT (16-BIT TIMER)........................................................4-7
SECTION 5
RESETS
5.1 EXTERNAL RESET (RESET)..........................................................................5-2
5.2 INTERNAL RESETS........................................................................................ 5-2
5.2.1 POWER-ON RESET (POR) ........................................................................5-2
5.2.2 COMPUTER OPERATING PROPERLY RESET (COPR)...........................5-2
5.2.3 LOW VOLTAGE RESET (LVR)...................................................................5-3
5.2.4 ILLEGAL ADDRESS RESET (ILADR).........................................................5-3
SECTION 6
LOW POWER MODES
6.1 STOP INSTRUCTION......................................................................................6-2
6.1.1 STOP Mode.................................................................................................6-3
6.1.2 HALT Mode..................................................................................................6-3
6.2 WAIT INSTRUCTION.......................................................................................6-4
6.3 DATA-RETENTION MODE..............................................................................6-4
6.4 COP WATCHDOG TIMER CONSIDERATIONS .............................................6-4
SECTION 7
INPUT/OUTPUT PORTS
7.1 SLOW OUTPUT FALLING-EDGE TRANSITION.............................................7-1
7.2 PORT A............................................................................................................7-1
7.2.1 Port A Data Register....................................................................................7-2
7.2.2 Port A Data Direction Register.....................................................................7-2
7.2.3 Port A Pulldown/up Register........................................................................7-3
7.2.4 Port A Drive Capability.................................................................................7-3
7.2.5 Port A I/O Pin Interrupts...............................................................................7-3
7.3 PORT B............................................................................................................7-4
7.3.1 Port B Data Register....................................................................................7-4
7.3.2 Port B Data Direction Register.....................................................................7-5
7.3.3 Port B Pulldown/up Register........................................................................7-5
7.4 I/O PORT PROGRAMMING ............................................................................7-6
7.4.1 Pin Data Direction........................................................................................7-6
7.4.2 Output Pin....................................................................................................7-6
7.4.3 Input Pin.......................................................................................................7-6
7.4.4 I/O Pin Transitions.......................................................................................7-7
7.4.5 I/O Pin Truth Tables.....................................................................................7-7
MOTOROLA MC68HC05J5A
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TABLE OF CONTENTS
Section Page
SECTION 8
MULTI-FUNCTION TIMER
8.1 OVERVIEW......................................................................................................8-2
8.2 COMPUTER OPERATING PROPERLY (COP) WATCHDOG........................8-2
8.3 MFT REGISTERS............................................................................................ 8-2
8.3.1 Timer Counter Register (TCR) $09..............................................................8-3
8.3.2 Timer Control/Status Register (TCSR) $08.................................................8-3
8.4 OPERATION DURING STOP MODE..............................................................8-5
8.5 OPERATION DURING WAIT/HALT MODE.....................................................8-5
SECTION 9
16-BIT TIMER
9.1 TIMER1 COUNTER REGISTERS (TCNTH, TCNTL)......................................9-2
9.2 ALTERNATE COUNTER REGISTERS (ACNTH, ACNTL)..............................9-3
9.3 INPUT CAPTURE REGISTERS ......................................................................9-5
9.4 TIMER1 CONTROL REGISTER (T1CR).........................................................9-8
9.5 TIMER1 STATUS REGISTER (T1SR).............................................................9-9
9.6 TIMER1 OPERATION DURING WAIT MODE.................................................9-9
9.7 TIMER1 OPERATION DURING STOP MODE................................................9-9
SECTION 10
INSTRUCTION SET
10.1 ADDRESSING MODES.................................................................................10-1
10.1.1 Inherent......................................................................................................10-1
10.1.2 Immediate..................................................................................................10-1
10.1.3 Direct .........................................................................................................10-2
10.1.4 Extended....................................................................................................10-2
10.1.5 Indexed, No Offset.....................................................................................10-2
10.1.6 Indexed, 8-Bit Offset..................................................................................10-2
10.1.7 Indexed, 16-Bit Offset................................................................................10-3
10.1.8 Relative......................................................................................................10-3
10.1.9 Instruction Types .......................................................................................10-3
10.1.10 Register/Memory Instructions....................................................................10-4
10.1.11 Read-Modify-Write Instructions .................................................................10-5
10.1.12 Jump/Branch Instructions..........................................................................10-5
10.1.13 Bit Manipulation Instructions......................................................................10-7
10.1.14 Control Instructions....................................................................................10-7
10.1.15 Instruction Set Summary ...........................................................................10-8
MC68HC05J5A MOTOROLA
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TABLE OF CONTENTS
Section Page
SECTION 11
ELECTRICAL SPECIFICATIONS
11.1 MAXIMUM RATINGS.....................................................................................11-1
11.2 THERMAL CHARACTERISTICS...................................................................11-1
11.3 FUNCTIONAL OPERATING RANGE............................................................11-1
11.4 DC ELECTRICAL CHARACTERISTICS........................................................11-2
11.5 CONTROL TIMING........................................................................................11-5
SECTION 12
MECHANICAL SPECIFICATIONS
12.1 16-PIN PDIP (CASE #648) ............................................................................12-1
12.2 16-PIN SOIC (CASE #751G).........................................................................12-1
12.3 20-PIN PDIP (CASE #738) ............................................................................12-2
12.4 20-PIN SOIC (CASE #751D) .........................................................................12-2
APPENDIX A
MC68HRC05J5A
A.1 INTRODUCTION..............................................................................................A-1
A.2 RC OSCILLATOR CONNECTIONS.................................................................A-1
A.3 ELECTRICAL CHARACTERISTICS................................................................A-2
APPENDIX B
MC68HC705J5A
B.1 INTRODUCTION..............................................................................................B-1
B.2 MEMORY.........................................................................................................B-1
B.3 MASK OPTION REGISTERS (MOR)...............................................................B-1
B.4 BOOTSTRAP MODE.......................................................................................B-4
B.5 EPROM PROGRAMMING...............................................................................B-4
B.5.1 EPROM Program Control Register (PCR)...................................................B-4
B.5.2 Programming Sequence..............................................................................B-5
B.6 ELECTRICAL CHARACTERISTICS................................................................B-6
APPENDIX C
MC68HRC705J5A
C.1 INTRODUCTION..............................................................................................C-1
C.2 RC OSCILLATOR CONNECTIONS.................................................................C-1
C.3 ELECTRICAL CHARACTERISTICS................................................................C-2
APPENDIX D
ORDERING INFORMATION
D.1 MC ORDER NUMBERS...................................................................................D-1
MOTOROLA MC68HC05J5A
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LIST OF FIGURES
Figure Title Page
1-1 MC68HC05J5A Block Diagram........................................................................1-3
1-2 Pin Assignments for 16-Pin and 20-Pin Packages...........................................1-4
1-3 Oscillator Connections..................................................................................... 1-5
2-1 MC68HC05J5A Memory Map..........................................................................2-1
2-2 I/O Registers Memory Map..............................................................................2-2
2-3 I/O Registers $0000-$000F..............................................................................2-3
2-4 I/O Registers $0010-$001F..............................................................................2-4
3-1 MC68HC05 Programming Model.....................................................................3-1
4-1 Interrupt Processing Flowchart........................................................................4-2
4-2 IRQ Function Block Diagram............................................................................4-3
4-3 IRQ Status & Control Register......................................................................... 4-5
5-1 Reset Block Diagram.......................................................................................5-1
6-1 STOP/HALT/WAIT Flowcharts.........................................................................6-2
7-1 Port B Data Direction Register.........................................................................7-1
7-2 Port A I/O Circuitry...........................................................................................7-2
7-3 Port B I/O Circuitry...........................................................................................7-4
8-1 Multi-Function Timer Block Diagram................................................................8-1
8-2 COP Watchdog Timer Location.......................................................................8-2
8-3 Timer Counter Register....................................................................................8-3
8-4 Timer Control/Status Register (TCSR).............................................................8-3
9-1 16-Bit Timer Block Diagram.............................................................................9-1
9-2 16-Bit Timer Counter Block Diagram...............................................................9-2
9-3 16-Bit Timer Counter Registers (TCNTH, TCNTL)..........................................9-3
9-4 Alternate Counter Block Diagram.....................................................................9-4
9-5 Alternate Counter Registers (ACNTH, ACNTL)...............................................9-4
9-6 Timer Input Capture Block Diagram.................................................................9-5
9-7 Timer1 Capture Control Register.....................................................................9-6
9-8 TCAP Input Signal Conditioning.......................................................................9-6
9-9 TCAP Input Comparator Output.......................................................................9-7
9-10 Input Capture Registers (ICH, ICL)..................................................................9-7
9-11 Timer Control Register (T1CR)........................................................................9-8
9-12 Timer Status Registers (T1SR)........................................................................9-9
12-1 16-Pin PDIP Mechanical Dimensions............................................................12-1
12-2 16-Pin SOIC Mechanical Dimensions............................................................12-1
12-3 20-Pin PDIP Mechanical Dimensions............................................................12-2
12-4 20-Pin SOIC Mechanical Dimensions............................................................12-2
A-1 RC Oscillator Connections...............................................................................A-1
A-2 Typical Internal Operating Frequency for RC Oscillator Connections..............A-2
B-1 MC68HC705J5A Memory Map........................................................................B-3
B-2 EPROM Programming Sequence....................................................................B-5
C-1 RC Oscillator Connections...............................................................................C-1
C-2 Typical Internal Operating Frequency for RC Oscillator Connections..............C-2
MC68HC05J5A MOTOROLA
REV 2.1 v
GENERAL RELEASE SPECIFICATION July 16, 1999
LIST OF FIGURES
Figure Title Page
MOTOROLA MC68HC05J5A
vi REV 2.1
July 16, 1999 GENERAL RELEASE SPECIFICATION
LIST OF TABLES
Table Title Page
4-1 Vector Address for Interrupts and Reset..........................................................4-1
6-1 COP Watchdog Timer Recommendations.......................................................6-5
7-1 Port A I/O Pin Functions...................................................................................7-7
7-2 Port B I/O Pin Functions...................................................................................7-7
8-1 RTI Rates and COP Reset Times....................................................................8-5
10-1 Register/Memory Instructions........................................................................10-4
10-2 Read-Modify-Write Instructions .....................................................................10-5
10-3 Jump and Branch Instructions........................................................................10-6
10-4 Bit Manipulation Instructions.......................................................................... 10-7
10-5 Control Instructions........................................................................................ 10-7
10-6 Instruction Set Summary ...............................................................................10-8
10-7 Opcode Map.................................................................................................10-14
11-1 DC Electrical Characteristics, VDD=5 V ........................................................11-2
11-2 DC Electrical Characteristics, VDD=2.2V .....................................................11-3
11-3 Control Timing, VDD=5V...............................................................................11-5
11-4 Control Timing, VDD=2.2V............................................................................11-5
A-1 Functional Operating Range............................................................................A-2
A-2 DC Electrical Characteristics, VDD=5V...........................................................A-2
B-1 Functional Operating Range............................................................................B-6
B-2 EPROM Programming Electrical Characteristics.............................................B-6
B-3 DC Electrical Characteristics, VDD=5V..........................................................B-6
C-1 Functional Operating Range............................................................................C-2
C-2 DC Electrical Characteristics, VDD=5V..........................................................C-2
D-1 MC Order Numbers..........................................................................................D-1
MC68HC05J5A MOTOROLA
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LIST OF TABLES
Table Title Page
MOTOROLA MC68HC05J5A
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July 16, 1999 GENERAL RELEASE SPECIFICATION
SECTION 1
GENERAL DESCRIPTION
The MC68HC05J5A is a member of the low-cost high-performance M68HC05
Family of 8-bit microcontroller units (MCUs). The M68HC05 Family is based on
the customer-specified integrated circuit design strategy. All MCUs in the family
use the popular M68HC05 central processing unit (CPU) and are available with a
variety of subsystems, memory sizes and types, and package types.
The MC68HC05J5A is an enhanced version of the MC68HC05J5, with expanded
RAM, ROM sizes, and an additional 16-bit timer with TCAP. This MCU is available
in 20-pin PDIP, 20-pin SOIC, 16-pin PDIP, and 16-pin SOIC packages. The 16-pin
version has four less I/O lines.
Three variation on the MC68HC05J5A device are available; a summary of their
differences are listed in the following table:
DEVICE ROM TYPE OSCILLATOR OPTION REFERENCE
MC68HC05J5A 2560 bytes ROM Crystal/resonator or external clock oscillator —
MC68HRC05J5A 2560 bytes ROM RC oscillator
MC68HC705J5A 2560 bytes EPROM Crystal/resonator or external clock oscillator
MC68HRC705J5A 2560 bytes EPROM RC oscillator
Appendix A
Appendix B
Appendix C
1.1 FEATURES
The features of the MC68HC05J5A include the following:
• Industry standard M68HC05 CPU core
• Fully static operation with no minimum clock speed
• Power-saving STOP and WAIT modes
• Memory-Mapped Input/Output (I/O) registers
• 2560 Bytes of user ROM with security feature
• 128 Bytes of user RAM
• On-Chip Oscillator:
– Crystal/Resonator oscillator
– External clock oscillator
• 15-Bit Multi-function Timer
• 16-Bit Programmable Timer with Input Capture
MC68HC05J5A
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GENERAL DESCRIPTION
MOTOROLA
GENERAL RELEASE SPECIFICATION July 16, 1999
• 14 Bidirectional I/O pins (10 I/O pins on 16-pin package)
– PA0-PA5, PB0, and PB3-PB5: with software programmable input pull-
down devices
– PB1, PB2, PA6 and PA7: open-drained I/O pins with software
programmable pull-up devices
– PA6, PA7, and PB1: with slow output falling transition feature
– PA7: with falling-edge interrupt capability
– PA0-PA3: with maskable rising-edge only or rising-edge and high
level interrupt capability
– 20-pin package: PB1 and PB2, each with 25mA current sink
capability
– 16-pin package: PB1 with 50mA current sink capability
• Computer Operation Properly (COP) Watchdog
• Low Voltage Reset Circuit
• Illegal Address Reset
• 20-pin PDIP, 20-pin SOIC, 16-pin PDIP, and 16-pin SOIC packages
1.2 MASK OPTIONS
The following mask options are available on the MC68HC05J5A:
STOP instruction convert to WAIT [Enabled] or [Disabled]
External interrupt pins (IRQ, PA0-PA3) [Edge-triggered] or [Edge and level triggered]
Port A and Port B pull-down/pull-up resistors [Enabled] or [Disabled]
PA0-PA3 external interrupt capability [Enabled] or [Disabled]
Oscillator Delay Option (internal clock cycles) [224] or [4064]
Low Voltage Reset [Enabled] or [Disabled]
COP Watchdog Timer [Enabled] or [Disabled]
MASK OPTION
1.3 MCU STRUCTURE
Figure 1-1 shows the structure of MC68HC05J5A MCU.
MOTOROLA
1-2 REV 2.1
GENERAL DESCRIPTION
MC68HC05J5A
July 16, 1999 GENERAL RELEASE SPECIFICATION
PA0①
PA1①
PA2①
PA3①
PA4②
PA5②
PA6③
PA7④
PB0⑤
PB1⑥
PB2⑥⑦
PB3⑦
PB4⑦
PB5⑦
①
: External edge interrupt capability
②
: 8 mA current sink
③
: Open-drained with internal pull-up and
8 mA current sink
④
: External interrupt capability, open-drained
with internal pull-up and 8 mA current sink
⑤
: Shared pin: PB0/TCAP
⑥
: 25 mA current sink open-drained with
internal pull-up
⑦
: not bonded out in 16-pin package
PORT
REG
PORT
REG
DATA
A
B
DIR
REG
DATA
DIR
REG
OSC1
OSC2/R
OSCILLATOR
AND DIVIDE
BY 2
COND CODE REG 1 1 1 I N Z CH
2560 BYTES
CPU CONTROL
68HC05 CPU
CPU REGISERS
0 0 0 1100000
PROGRAM COUNTER
ROM
CORE
TIMER
(COP)
16-BIT
TIMER
INDEX REG
RESET
IRQ
LOW
VOLTAGE
RESET
TCAP⑤
ALU
VDD
VSS
ACCUM
STK PTR
128 BYTES
RAM
Figure 1-1. MC68HC05J5A Block Diagram
MC68HC05J5A
REV 2.1 1-3
GENERAL DESCRIPTION
MOTOROLA
GENERAL RELEASE SPECIFICATION July 16, 1999
1.4 PIN ASSIGNMENTS
OSC2/R
OSC1
RESET
PA7
PA6
PA5
PA4
PB0/TCAP
IRQ/VPP: VPP is only available on EPROM parts
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
PB1
VDD
VSS
/VPP
IRQ
PA0
PA1
PA2
9
PA3
PB3
OSC2/R
OSC1
RESET
PA7
PA6
PA5
PA4
PB0/TCAP
PB4
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
1110
PB2
PB1
VDD
VSS
IRQ/VPP
PA0
PA1
PA2
PA3
PB5
Figure 1-2. Pin Assignments for 16-Pin and 20-Pin Packages
1.5 FUNCTIONAL PIN DESCRIPTION
The following paragraphs give a description of the general function of each pin
assigned in Figure 1-2 .
1.5.1 V
AND V
DD
SS
Power is supplied to the MCU through V
and V
is ground. The MCU operates from a single power supply.
SS
Very fast signal transitions occur on the MCU pins. The short rise and fall times
place very high short-duration current demands on the power supply. To prevent
noise problems, special care should be taken to provide good power supply
bypassing at the MCU by using b ypass capacitors with good high-frequency characteristics that are positioned as close to the MCU as possible. Bypassing
requirements vary, depending on how heavily the MCU pins are loaded.
1.5.2 OSC1, OSC2/R
The OSC1 and OSC2/R pins are the connections for the on-chip oscillator. The
OSC1 and OSC2/R pins can accept the following sets of components:
and V
DD
SS
. V
is the positive supply,
DD
MOTOROLA
1-4 REV 2.1
GENERAL DESCRIPTION
MC68HC05J5A
.
July 16, 1999 GENERAL RELEASE SPECIFICATION
1. A crystal as shown in Figure 1-3 (a)
2. A ceramic resonator as shown in Figure 1-3 (a)
3. An external clock signal as shown in Figure 1-3 (b)
The frequency, f
produce the internal operating frequency, f
, of the oscillator or external clock source is divided by two to
OSC
OP
Crystal Oscillator
The circuit in Figure 1-3 (a) shows a typical oscillator circuit for an AT-cut, parallel
resonant crystal. The crystal manufacturer’s recommendations should be followed, as the crystal parameters determine the external component values
required to provide maximum stability and reliable start-up. The load capacitance
values used in the oscillator circuit design should include all stray capacitances.
The crystal and components should be mounted as close as possible to the pins
for start-up stabilization and to minimize output distortion. An internal start-up
resistor is provided between OSC1 and OSC2/R for the crystal type oscillator.
OSC1
37 pF
MCU
R
OSC
OSC2/R
37pF
OSC1
MCU
OSC2/R
unconnected
External Clock
(a) Crystal or ceramic
resonator connection
R
: see Section 11. Electrical Specifications.
OSC
(b) External clock source
connection
Figure 1-3. Oscillator Connections
Ceramic Resonator Oscillator
In cost-sensitive applications, a ceramic resonator can be used in place of the
crystal. The circuit in Figure 1-3 (a) can be used for a ceramic resonator. The resonator manufacturer’s recommendations should be followed, as the resonator
parameters determine the external component values required for maximum stability and reliable starting. The load capacitance values used in the oscillator circuit design should include all stray capacitances. The ceramic resonator and
components should be mounted as close as possible to the pins for start-up stabilization and to minimize output distortion. An internal start-up resistor is provided
between OSC1 and OSC2/R for the ceramic resonator type oscillator.
External Clock
An external clock from another CMOS-compatible device can be connected to the
OSC1 input, with the OSC2/R input not connected, as shown in Figure 1-3 (b).
MC68HC05J5A
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GENERAL DESCRIPTION
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GENERAL RELEASE SPECIFICATION July 16, 1999
1.5.3 RESET
This is an I/O pin. This pin can be used as an input to reset the MCU to a known
start-up state by pulling it to the low state. The RESET pin contains a steering
diode to discharge any voltage on the pin to V
internal pull-up is also connected between this pin and V
, when the power is removed. An
DD
. The RESET
DD
pin contains an internal Schmitt trigger to improve its noise immunity as an input. This pin
is an output pin if LVR triggers an internal reset.
1.5.4 IRQ (MASKABLE INTERRUPT REQUEST)
This input pin drives the asynchronous IRQ interrupt function of the CPU. The IRQ
interrupt function has a mask option to provide either only negative edge-sensitive
triggering or both negative edge-sensitive and low level-sensitive triggering. If the
option is selected to include level-sensitive triggering, the IRQ
external resistor to V
for "wired-OR" operation, if desired. The IRQ
DD
input requires an
pin contains
an internal Schmitt trigger as part of its input to improve noise immunity.
Each of the PA0 through PA3 I/O pins may be connected as an OR function with
the IRQ interrupt function by a mask option. This capability allows keyboard scan
applications where the transitions or levels on the I/O pins will behave the same
as the IRQ
selected by a separate mask option for the IRQ
OR’ed to create the IRQ signal. Besides, PA7 also has falling-edge only interrupt
capability whose functionality is controlled by another set of register bits.
1.5.5 PA0-PA7
These eight I/O lines comprise Port A. PA6 and PA7 are open-drained pins with
pull-up devices whereas PA0 to PA5 are push-pull pins with pull-down devices.
PA4 to PA7 are also capable of sinking 8mA.
The state of any pin is software programmable and all Port A lines are configured
as inputs during power-on or reset. The lower four I/O pins (PA0 to PA3) can be
connected via an internal OR gate to the IRQ interrupt function enabled by a mask
option. Another independent interrupt source comes from the falling-edge on PA7.
PA7 interrupt source is associated with a second set of interrupt control/status
bits. All Port A pins except PA6 and PA7 have software programmable pull-down
devices also provided by a mask option. PA6 and PA7 pins have software
programmable pull-up devices also provided by the same mask option. Pull-up
devices on PA6 and PA7 once enabled are always enabled regardless of pin
direction configuration, unlike pull-down devices on PA0 to PA5 which are
activated only when these pins are configured as input pins.
pin, except for the inverted phase. The edge or level sensitivity
pin also applies to the I/O pins
PA6 and PA7 pins, when configured as output pins, also have slow output fallingedge transition feature to reduce EMI. The falling-edge transition time is set at
250 ns typical at a specified load of 500 pF, assuming the bus rate is 2 MHz. The
slow transition output feature of PA6 and PA7, along with that of PB1 and PB2,
MOTOROLA
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GENERAL DESCRIPTION
MC68HC05J5A
July 16, 1999 GENERAL RELEASE SPECIFICATION
can be enabled or disabled by software. Both PA6 and PA7 pins have Schmitt
trigger input for better noise immunity. V
and V
IH
are specified at 2.4V and 0.8V,
IL
respectively.
The slow transition feature of PA6 and PA7 pins can be enabled or disabled by
software. Once enabled, slow transition feature is applied to both pins while in
output mode.
1.5.6 PB0-PB5
NOTE
I/O lines PB2 to PB5 are not available on the 16-pin package.
These six I/O lines comprise Port B. PB0, PB3 to PB5 are push-pull I/O lines with
pull-down resistor. PB1 and PB2 are open-drain I/O lines with pull-up resistor.
The state of any line is software programmable and is configured as an input
during power-on or reset. I/O lines PB1 and PB2 have software programmable
pull-up device, whereas PB0, PB3 to PB5 have software programmable pull-down
device, provided by mask option. Pull-up devices on PB1 and PB2 lines once
enabled are always enabled regardless of pin direction configuration; unlike pulldown devices on PB0, PB3-PB5 lines, which are activated only when the pin is
configured as input pin.
Similar to PA6 and PA7, PB1 also has a slow output falling transition feature when
configured as an output line. PB1 has 25mA sink capability at 0.5V V
OL
.
PB2 output is one clock cycle (250 ns if bus rate is 2MHz) late than other I/O pins
if slow output transition feature is enabled. PB2 has 25mA sink capability at 0.5V
.
V
OL
NOTE
For the 16-pin package, PB1 and PB2 are bonded to the same pin and is labelled
PB1. This PB1 pin has 50mA sink capability if PB1 and PB2 data register bits they
are written with the same value at the same write cycle. The falling transition time
of PB1 is set at 250ns typical at a specified load of 50pF, assuming that the bus
rate is 2MHz. The slow transition feature on this PB1 pin is longer than PB1 pin for
the 20-pin package.
NOTE
If Port Data Register PB1 and PB2 are not written with the same value, PB1 pin
on the 16-pin package will sink 25 mA only and the output transition time will be
shorter.
MC68HC05J5A
REV 2.1 1-7
GENERAL DESCRIPTION
MOTOROLA
GENERAL RELEASE SPECIFICATION July 16, 1999
MOTOROLA
1-8 REV 2.1
GENERAL DESCRIPTION
MC68HC05J5A
July 16, 1999 GENERAL RELEASE SPECIFICATION
SECTION 2
MEMORY
The MC68HC05J5A has 4K-bytes of addressable memory consisting 32 bytes of
I/O, 128 bytes of user RAM, and 2560 bytes of user ROM, as shown in
Figure 2-1.
$0000
$001F
$0020
$007F
$0080
$00FF
$0100
$02FF
$0300
$0CFF
$0D00
$0DFF
$0E00 3584
$0FEF
$0FF0
$0FF5
$0FF6
$0FFF
Internal Test & Vectors
I/O
32 Bytes
unimplemented
96 Bytes
User RAM 128 Bytes
Stack
unimplemented
512 Bytes
User ROM
2560 Bytes
unimplemented
256 Bytes
496 Bytes ROM
ROM Reserved
6 Bytes
User Vectors ROM
10 Bytes
0000
0031
0032
0127
0128
0192 $00C0
0255
0256
0767
0768
3327
3328
3583
4079
4080
4085
4086
4095
$0000
I/O
Registers
32 bytes
(see Figure 2-2)
$001F
COP Watchdog Timer*
Reserved
Reserved
Reserved
Reserved
Reserved
Timer1 Vector (High Byte)
Timer1 Vector (Low Byte)
MFT Vector (High Byte)
MFT Vector (Low Byte)
IRQ Vector (High Byte)
IRQ Vector (Low Byte)
SWI Vector (High Byte)
SWI Vector (Low Byte)
Reset Vector (High Byte)
Reset Vector (Low Byte)
* Writing a 0 to bit 0 of $0FF0 clears the COP Timer.
Reading $0FF0 returns ROM data.
$0FF0
$0FF1
$0FF2
$0FF3
$0FF4
$0FF5
$0FF6
$0FF7
$0FF8
$0FF9
$0FFA
$0FFB
$0FFC
$0FFD
$0FFE
$0FFF
Figure 2-1. MC68HC05J5A Memory Map
MC68HC05J5A
REV 2.1 2-1
MEMORY
MOTOROLA
GENERAL RELEASE SPECIFICATION July 16, 1999
2.1 I/O AND CONTROL REGISTERS
The I/O and Control Registers reside in locations $0000-$001F. The overall organization of these registers is shown in Figure 2-2. The bit assignments for each
register are shown in Figure 2-3 and Figure 2-4. Reading from unimplemented
bits will return unknown states, and writing to unimplemented bits will be ignored.
Port A Data Register
Port B Data Register
Timer1 Capture Control Register
unimplemented (1)
Port A Data Direction Register
Port B Data Direction Register
unimplemented (2)
MFT Control & Status Register
MFT Counter Register
IRQ Control & Status Register
unimplemented (5)
Port A Pulldown/up Register
Port B Pulldown/up Register
Timer1 Registers (4)
unimplemented (2)
Timer1 Registers (4)
unimplemented (3)
Reserved
Reserved for Test
$0000
$0001
$0002
$0003
$0004
$0005
$0008
$0009
$000A
$0010
$0011
$0012
$0015
$0018
$001B
$001E
$001F
Figure 2-2. I/O Registers Memory Map
2.2 RAM
The total RAM consists of 128 bytes (including the stack) at locations $0080
through $00FF. The stack begins at address $00FF and proceeds down to $00C0.
Using the stack area for data stor age or tempor ary work locations requires care to
prevent it from being overwritten due to stacking from an interrupt or subroutine
call.
2.3 ROM
There are a total of 2570 bytes of user ROM on-chip. This includes 2560 bytes of
user ROM from locations $0300 to $0CFF for user program storage and 10 bytes
for user vectors from locations $0FF6 to $0FFF.
MOTOROLA MEMORY MC68HC05J5A
2-2 REV 2.1
July 16, 1999 GENERAL RELEASE SPECIFICATION
2.4 I/O REGISTERS SUMMARY
ADDR REGISTER R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
$0000
$0001
$0002
$0003 Unimplemented
$0004
$0005
$0006
$0007 Unimplemented
$0008
$0009
$000A
$000B Unimplemented
$000C Unimplemented
$000D Unimplemented
$000E Unimplemented
$000F Unimplemented
Port A Data R
PORTA W
Port B Data R 0 0
PORTB W
Timer1 Capture Control
T1CC W
Port A Data Direction R
DDRA W
Port B Data Direction R
DDRB W
Unimplemented
MFT Ctrl/Status R TOF RTIF
TCSR W
MFT Counter R TMR7 TMR6 TMR5 TMR4 TMR3 TMR2 TMR1 TMR0
TCR W
IRQ Control/Status R
ICSR W
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
PB5 PB4 PB3 PB2 PB1 PB0
R
TCAPS
R
W
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
SLOWE
R
W
R
W
IRQE IRQE1
R
W
R
W
R
W
R
W
R
W
0
DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
TOFE RTIE
0 0 IRQF IRQF1 0 0
R IRQR IRQR1
00
TOFR RTIFR
RT1 RT0
unimplemented bits reserved bits R
Figure 2-3. I/O Registers $0000-$000F
MC68HC05J5A MEMORY MOTOROLA
REV 2.1 2-3
GENERAL RELEASE SPECIFICATION July 16, 1999
ADDR REGISTER R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
$0010
$0011
$0012
$0013
$0014
$0015
$0016 Unimplemented
$0017 Unimplemented
$0018
$0019
$001A
$001B
$001C Unimplemented
$001D Unimplemented
$001E Reserved
$001F Reserved
Port A Pull-down/up R
PDURA W PURA7 PURA6 PDRA5 PDRA4 PDRA3 PDRA2 PDRA1 PDRA0
Port B Pull-down/up R
PDURB W PDRB5 PDRB4 PDRB3 PURB2 PURB1 PDRB0
Timer1 Control R
T1CR W
Timer1 Status R ICF 0 T1OF 00000
T1SR W
Input Capture High R BIT15 BIT14 BIT13 BIT12 BIT11 BIT10 BIT9 BIT8
ICH W
Input Capture Low R BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
ICL W
Timer1 Counter High R BIT15 BIT14 BIT13 BIT12 BIT11 BIT10 BIT9 BIT8
TCNTH W
Timer1 Counter Low R BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
TCNTL W
Alt. Counter High R BIT15 BIT14 BIT13 BIT12 BIT11 BIT10 BIT9 BIT8
ACNTH W
Alt. Counter Low R BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
ACNTL W
W
W
W
W
W
W
ICIE
R
R
R
R
R
R
R R R R R R R R
R R R R R R R R
0
T1OIE
000
IEDGE
0
unimplemented bits reserved bits R
Figure 2-4. I/O Registers $0010-$001F
MOTOROLA MEMORY MC68HC05J5A
2-4 REV 2.1
July 16, 1999 GENERAL RELEASE SPECIFICATION
SECTION 3
CENTRAL PROCESSING UNIT
The MC68HC05J5A has an 4k-bytes memory map. The stack has only 64 bytes.
Therefore, the stack pointer has been reduced to only 6 bits and will only
decrement down to $00C0 and then wrap-around to $00FF. All other instructions
and registers behave as described in this chapter.
3.1 REGISTERS
The MCU contains five registers which are hard-wired within the CPU and are not
part of the memor y map. These five registers are shown in Figure 3-1 and are
described in the following paragraphs.
60
71
14 815 91213 1011
1100000000
PROGRAM COUNTER
CONDITION CODE REGISTER I
HALF-CARRY BIT (FROM BIT 3)
INTERRUPT MASK
NEGATIVE BIT
ZERO BIT
CARRY BIT
4523
ACCUMULATOR
INDEX REGISTER
STACK POINTER SP
H NZC
A
X
PC
CC111
Figure 3-1. MC68HC05 Programming Model
MC68HC05J5A CENTRAL PROCESSING UNIT MOTOROLA
REV 2.1 3-1
GENERAL RELEASE SPECIFICATION July 16, 1999
3.2 ACCUMULATOR (A)
The accumulator is a general purpose 8-bit register as shown in Figure 3-1. The
CPU uses the accumulator to hold operands and results of arithmetic calculations
or non-arithmetic operations. The accumulator is not affected by a reset of the
device.
3.3 INDEX REGISTER (X)
The index register shown in Figure 3-1 is an 8-bit register that can perform two
functions:
• Indexed addressing
• Temporary storage
In indexed addressing with no offset, the index register contains the low byte of
the operand address, and the high byte is assumed to be $00. In indexed
addressing with an 8-bit offset, the CPU finds the operand address by adding the
index register content to an 8-bit immediate value. In indexed addressing with a
16-bit offset, the CPU finds the operand address by adding the index register
content to a 16-bit immediate value.
The index register can also serve as an auxiliary accumulator for temporary
storage. The index register is not affected by a reset of the device.
3.4 STACK POINTER (SP)
The stack pointer shown in Figure 3-1 is a 16-bit register. In MCU devices with
memory space less than 64k-bytes the unimplemented upper address lines are
ignored. The stack pointer contains the address of the next free location on the
stack. During a reset or the reset stack pointer (RSP) instruction, the stack pointer
is set to $00FF. The stack pointer is then decremented as data is pushed onto the
stack and incremented as data is pulled off the stack.
When accessing memory, the ten most significant bits are permanently set to
0000000011. The six least significant register bits are appended to these ten fixed
bits to produce an address within the range of $00FF to $00C0. Subroutines and
interrupts may use up to 64($C0) locations. If 64 locations are exceeded, the
stack pointer wraps around and overwrites the previously stored information. A
subroutine call occupies two locations on the stack and an interrupt uses five
locations.
3.5 PROGRAM COUNTER (PC)
The program counter shown in Figure 3-1 is a 16-bit register. In MCU devices
with memory space less than 64k-bytes the unimplemented upper address lines
are ignored. The program counter contains the address of the next instruction or
operand to be fetched.
MOTOROLA CENTRAL PROCESSING UNIT MC68HC05J5A
3-2 REV 2.1
July 16, 1999 GENERAL RELEASE SPECIFICATION
Normally, the address in the program counter increments to the next sequential
memory location every time an instruction or operand is fetched. Jump, branch,
and interrupt operations load the program counter with an address other than that
of the next sequential location.
3.6 CONDITION CODE REGISTER (CCR)
The CCR shown in Figure 3-1 is a 5-bit register in which four bits are used to
indicate the results of the instruction just executed. The fifth bit is the interrupt
mask. These bits can be individually tested by a program, and specific actions can
be taken as a result of their states. The condition code register should be thought
of as having three additional upper bits that are always ones. Only the interrupt
mask is affected by a reset of the device. The following paragraphs explain the
functions of the lower five bits of the condition code register.
3.6.1 Half Carry Bit (H-Bit)
When the half-carry bit is set, it means that a carry occurred between bits 3 and 4
of the accumulator during the last ADD or ADC (add with carry) operation. The
half-carry bit is required for binary-coded decimal (BCD) arithmetic operations.
3.6.2 Interrupt Mask (I-Bit)
When the interrupt mask is set, the internal and external interrupts are disabled.
Interrupts are enabled when the interrupt mask is cleared. When an interrupt
occurs, the interrupt mask is automatically set after the CPU registers are saved
on the stack, but before the interrupt vector is fetched. If an interrupt request
occurs while the interrupt mask is set, the interrupt request is latched. Normally,
the interrupt is processed as soon as the interrupt mask is cleared.
A return from interrupt (RTI) instruction pulls the CPU registers from the stack,
restoring the interrupt mask to its state before the interrupt was encountered. After
any reset, the interrupt mask is set and can only be cleared by the Clear I-Bit
(CLI), or WAIT instructions.
3.6.3 Negative Bit (N-Bit)
The negative bit is set when the result of the last arithmetic operation, logical
operation, or data manipulation was negative. (Bit 7 of the result was a logical
one.)
The negative bit can also be used to check an often tested flag by assigning the
flag to bit 7 of a register or memory location. Loading the accumulator with the
contents of that register or location then sets or clears the negative bit according
to the state of the flag.
3.6.4 Zero Bit (Z-Bit)
The zero bit is set when the result of the last arithmetic operation, logical
operation, data manipulation, or data load operation was zero.
MC68HC05J5A CENTRAL PROCESSING UNIT MOTOROLA
REV 2.1 3-3
GENERAL RELEASE SPECIFICATION July 16, 1999
3.6.5 Carry/Borrow Bit (C-Bit)
The carry/borrow bit is set when a carry out of bit 7 of the accumulator occurred
during the last arithmetic operation, logical operation, or data manipulation. The
carry/borrow bit is also set or cleared during bit test and branch instructions and
during shifts and rotates. This bit is neither set by an INC nor by a DEC instruction.
MOTOROLA CENTRAL PROCESSING UNIT MC68HC05J5A
3-4 REV 2.1
July 16, 1999 GENERAL RELEASE SPECIFICATION
SECTION 4
INTERRUPTS
The MCU can be interrupted in six different ways:
• Non-maskable Software Interrupt Instruction (SWI)
• External Asynchronous Interrupt (IRQ
• Optional External Interrupt via IRQ on PA0-PA3 (by a mask option)
• External Interrupt via IRQ on PA7
• Multi-Function Timer (MFT)
• 16-Bit Timer Interrupt (Timer1)
4.1 CPU INTERRUPT PROCESSING
Interrupts cause the processor to save register contents on the stack and to set
the interrupt mask (I-bit) to prevent additional interrupts. Unlike RESET, hardware
interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete.
If interrupts are not masked (I-bit in the CCR is clear) and the corresponding interrupt enable bit is set the processor will proceed with interrupt processing. Otherwise, the next instruction is fetched and executed. If an interrupt occurs the
processor completes the current instruction, then stacks the current CPU register
states, sets the I-bit to inhibit further interrupts, and finally checks the pending
hardware interrupts. If more than one interrupt is pending following the stacking
operation, the interrupt with the highest vector location shown in Table 4-1 will be
serviced first. The SWI is executed the same as any other instruction, regardless
of the I-bit state.
)
When an interrupt is to be processed the CPU fetches the address of the appropriate interrupt software service routine from the vector table at locations $0FF6
thru $0FFF as defined in Table 4-1.
Table 4-1. Vector Address for Interrupts and Reset
Flag
Register
N/A
N/A
ICSR
TCSR
TCSR
T1SR
Name
N/A
N/A
IRQF/IRQF1
TOF
RTIF
T1OF, ICF
Interrupts
Reset
Software
External Interrupt
MFT Overflow
Real Time Interrupt
Timer1 Interrupt
MC68HC05J5A INTERRUPTS MOTOROLA
REV 2.1 4-1
CPU
Interrupt
RESET
SWI
IRQ
MFT
MFT
TIMER1
Vector Address
$0FFE-$0FFF
$0FFC-$0FFD
$0FFA-$0FFB
$0FF8-$0FF9
$0FF8-$0FF9
$0FF6-$0FF7
GENERAL RELEASE SPECIFICATION July 16, 1999
An RTI instruction is used to signify when the interrupt software service routine is
completed. The RTI instruction causes the register contents to be recovered from
the stack and normal processing to resume at the next instruction that was to be
executed when the interrupt took place. Figure 4-1 shows the sequence of events
that occur during interrupt processing.
From
RESET
Y
Is
I-Bit
Set?
N
IRQ
External
Interrupt?
N
TIMER
Internal
Interrupt?
N
Fetch Next
Instruction
SWI
Instruction
?
N
RTI
Instruction
?
N
Execute
Instruction
Y
Y
Y
Y
Clear IRQ
Request
Latch if IRQE1 is
cleared
Stack PC, X, A, CC
Set I-Bit in CCR
Load PC From:
SWI: $0FFC, $0FFD
IRQ: $0FFA-$0FFB
TIMER: $0FF8-$0FF9
TIMER1: $0FF6-$0FF7
Restore Registers
from stack
CC, A, X, PC
Figure 4-1. Interrupt Processing Flowchart
4.2 RESET INTERRUPT SEQUENCE
The RESET function is not in the strictest sense an interrupt; however, it is acted
upon in a similar manner as shown in Figure 4-1. A low level input on the RESET
pin or an internally generated RST signal causes the program to vector to its starting address which is specified by the contents of memory locations $0FFE and
$0FFF. The I-bit in the condition code register is also set.
MOTOROLA INTERRUPTS MC68HC05J5A
4-2 REV 2.1
July 16, 1999 GENERAL RELEASE SPECIFICATION
4.3 SOFTWARE INTERRUPT (SWI)
The SWI is an executable instruction and a non-maskable interrupt since it is executed regardless of the state of the I-bit in the CCR. As with any instruction, interrupts pending during the previous instruction will be serviced before the SWI
opcode is fetched. The interrupt service routine address is specified by the contents of memory locations $0FFC and $0FFD.
4.4 HARDWARE INTERRUPTS
All hardware interrupts except RESET are maskable by the I-bit in the CCR. If the
I-bit is set, all hardware interrupts (internal and external) are disabled. Clearing
the I-bit enables the hardware interrupts. There are two types of hardware interrupts which are explained in the following sections.
4.5 EXTERNAL INTERRUPT (IRQ
The IRQ
pin provides an asynchronous interrupt to the CPU. A block diagram of
the IRQ function is shown in Figure 4-2.
IRQ Pin
PA0
PA1
PA2
PA3
Mask Option
(Port A External Int.)
RST
IRQR
Mask Option
(IRQ Level)
IRQ Fetch Vector
IRQE1
IRQE
IRQE1
)
V
DD
IRQ
LATCH
R
to BIH & BIL
instruction
sensing
IRQF
to IRQ
processing
in CPU
V
DD
IRQ1
LATCH
PA7
R
RST
IRQR1
IRQF1
Figure 4-2. IRQ Function Block Diagram
MC68HC05J5A INTERRUPTS MOTOROLA
REV 2.1 4-3
GENERAL RELEASE SPECIFICATION July 16, 1999
The IRQ pin is a source of IRQ interrupts and a mask option can also enable the
other four lower Port A pins (PA0 thru PA3) to act as other IRQ interrupt sources.
The last source of IRQ interrupt comes from PA7 whenever there is a falling edge
on PA7 and IRQE1 is enabled. There is no mask option associated with PA7 interrupt.
Refer to Figure 4-2 for the following descriptions. IRQ interrupt source comes
from IRQ and IRQ1 latches. The IRQ latch will be set on the falling edge of the
pin or on any rising edge of PA0-3 pins if PA0-3 interrupts have been enabled.
IRQ
The IRQ1 latch will be set on the falling edge of PA7 if PA7 interrupt has been
enabled. If "edge-only" sensitivity is chosen by a mask option, only the IRQ latch
output can activate an IRQF flag which creates a request to the CPU to generate
the IRQ interrupt sequence. This makes the IRQ interrupt sensitive to the f ollowing
cases:
1. Falling edge on the IRQ
pin.
2. Rising edge on any PA0-PA3 pin with IRQ enabled (via mask option).
If level sensitivity is chosen, the rising edge signal on the clock input of the IRQ
latch can also activate an IRQF flag which creates an IRQ request to the CPU to
generate the IRQ interrupt sequence. This makes the IRQ interrupt sensitive to
the following cases:
1. Low level on the IRQ
2. Falling edge on the IRQ
pin.
pin.
3. High level on any PA0- PA3 pin with IRQ enabled (via mask option).
4. Rising edge on any PA0- PA3 pin with IRQ enabled (via mask option).
The IRQE enable bit controls whether an active IRQF flag can generate an IRQ
interrupt sequence. This interrupt is serviced by the interrupt service routine
located at the address specified by the contents of $0FFA and $0FFB.
The IRQ latch is automatically cleared by entering the interrupt service routine IF
IRQE1 enable bit is cleared. If IRQE1 enable bit is also set, the only way of clearing IRQF is by writing a logic one to the IRQR acknowledge bit. Writing a logic one
to the IRQR acknowledge bit in the ICSR is the other way of clearing IRQF flag,
regardless of the status of the IRQE1 bit, besides IRQ vector fetch. This conditional reset of IRQF flag provides a way for the user to differentiate the interrupt
sources from IRQ and IRQ1 latches and also to make it J1A compatible if PA7
interrupt is not used. As long as the output state of the IRQF flag bit is active the
CPU will continuously re-enter the IRQ interrupt sequence until the active state is
removed or the IRQE enable bit is cleared.
PA7 interrupt source, if enabled by IRQE1 enable bit, triggers IRQ interrupt on
PA7 f alling edge only. The IRQ1 latch (IRQF1 flag) can ONLY be cleared by writing
a logic one to the IRQR1 acknowledge bit in the ICSR. IRQ vector fetch can NOT
clear IRQF1 flag. IRQ interrupt caused by PA7 falling edge also vectors to $0FFA
and $0FFB.
MOTOROLA INTERRUPTS MC68HC05J5A
4-4 REV 2.1
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