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DSP56303 User’s Manual
24-Bit Digital Signal Processor
DSP56303UM/AD
Revision 1, January 2001
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MOTOROLA INC., 1996, 2001
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1
2
3
5
7
8
A
B
Overview
Signals/Connections
Memory Configuration
Programming the Peripherals
Enhanced Synchronous Ser ial Interface (ESSI)
Serial Communications Interface (SCI)
Bootstrap Program
Programming Reference
9
Triple Timer Module
4
Core Configuration
6
Host Interface (HI08)
Page 4
1
2
3
5
7
8
A
B
Overview
Signals/Connections
Memory Configuration
Programming the Peripherals
Enhanced Synchronous Ser ial Interface (ESSI)
Serial Communications Interface (SCI)
Bootstrap Program
Programming Reference
9
Triple Timer Module
4
Core Configura tio n
6
Host Interface (HI08)
Page 5
Contents v
Contents
Chapter 1
Overview
1.1 Manual Organization .............................................................................................................1-1
1.2 Manual Conventions.............................................................................................................. 1-2
1.3 Features.................................................................................................................................. 1-4
1.4 DSP56300 Core ..................................................................................................................... 1-4
1.5 DSP56300 Core Functional Blocks.......................................................................................1-5
1.5.1 Data ALU............................................................................................................................... 1-6
1.5.1.1 Data ALU Registers......................................................................................................... 1-6
1.5.1.2 Multiplier-Accumulator (MAC) ...................................................................................... 1-6
1.5.2 Address Generation Unit (AGU)........................................................................................... 1-7
1.5.3 Program Control Unit (PCU).................................................................................................1-7
1.5.4 PLL and Clock Oscillator ...................................................................................................... 1-8
1.5.5 JTAG TAP and OnCE Module.............................................................................................. 1-9
1.5.6 On-Chip Memory................................................................................................................... 1-9
1.5.7 Off-Chip Memory Expansion..............................................................................................1-10
1.6 Internal Buses ...................................................................................................................... 1-10
1.7 DMA....................................................................................................................................1-11
1.8 Peripherals ........................................................................................................................... 1-12
1.8.1 GPIO Functionality.............................................................................................................. 1-12
1.8.2 HI08 ..................................................................................................................................... 1-12
1.8.3 ESSI..................................................................................................................................... 1-13
1.8.4 SCI ....................................................................................................................................... 1-13
1.8.5 Timer Module ...................................................................................................................... 1-14
Chapter 2
Signals/Connections
2.1 Power ..................................................................................................................................... 2-3
2.2 Ground ................................................................................................................................... 2-4
2.3 Clock...................................................................................................................................... 2-5
2.4 Phase Lock Loop (PLL).........................................................................................................2-5
2.5 External Memory Expansion Port (Port A) ........................................................................... 2-6
2.5.1 External Address Bus............................................................................................................. 2-6
2.5.2 External Data Bus..................................................................................................................2-6
2.5.3 External Bus Control ............................................................................................................. 2-6
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2.6 Interrupt and Mode Control...................................................................................................2-9
2.7 Host Interface (HI08)........................................................................................................... 2-10
2.7.1 Host Port Usage Considerations .......................................................................................... 2-10
2.7.2 Host Port Configuration....................................................................................................... 2-11
2.8 Enhanced Synchronous Serial Interface 0 (ESSI0) ............................................................. 2-15
2.9 Enhanced Synchronous Serial Interface 1 (ESSI1) ............................................................. 2-17
2.10 Serial Communication Interface (SCI) ................................................................................ 2-19
2.11 Timers..................................................................................................................................2-20
2.12 JTAG/OnCE Interface .........................................................................................................2-21
Chapter 3
Memory Configuration
3.1 Program Memory Space ........................................................................................................ 3-1
3.1.1 Internal Program Memory .................................................................................................... 3-2
3.1.2 Memory Switch Modes—Program Memory.........................................................................3-2
3.1.3 Instruction Cache...................................................................................................................3-2
3.1.4 Program Bootstrap ROM.......................................................................................................3-3
3.2 X Data Memory Space........................................................................................................... 3-3
3.2.1 Internal X Data Memory........................................................................................................ 3-3
3.2.2 Memory Switch Modes—X Data Memory ........................................................................... 3-3
3.2.3 Internal I/O Space—X Data Memory.................................................................................... 3-4
3.3 Y Data Memory Space........................................................................................................... 3-4
3.3.1 Internal Y Data Memory........................................................................................................ 3-4
3.3.2 Memory Switch Modes—Y Data Memory ........................................................................... 3-4
3.3.3 External I/O Space—Y Data Memory................................................................................... 3-5
3.4 Dynamic Memory Configuration Switching ......................................................................... 3-5
3.5 Sixteen-Bit Compatibility Mode Configuration....................................................................3-6
3.6 RAM Configuration Summary .............................................................................................. 3-6
3.7 Memory Maps........................................................................................................................ 3-7
Chapter 4
Core Configuration
4.1 Operating Modes.................................................................................................................... 4-2
4.2 Bootstrap Program.................................................................................................................4-8
4.3 Central Processor Unit (CPU) Registers................................................................................4-9
4.3.1 Status Register (SR)............................................................................................................... 4-9
4.3.2 Operating Mode Register (OMR)........................................................................................4-15
4.4 Configuring Interrupts ......................................................................................................... 4-18
4.4.1 Interrupt Priority Registers (IPRC and IPRP)...................................................................... 4-19
4.4.2 Interrupt Table Memory Map .............................................................................................. 4-20
4.4.3 Processing Interrupt Source Priorities Within an IPL ......................................................... 4-22
4.5 PLL Control Register (PCTL) ............................................................................................. 4-24
4.6 Bus Interface Unit (BIU) Registers ..................................................................................... 4-25
4.6.1 Bus Control Register............................................................................................................ 4-25
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4.6.2 DRAM Control Register (DCR)..........................................................................................4-27
4.6.3 Address Attribute Registers (AAR[0–3]) ............................................................................ 4-30
4.7 DMA Control Registers 5–0 (DCR[5–0]) ........................................................................... 4-32
4.8 Device Identification Register (IDR)................................................................................... 4-37
4.9 JTAG Identification (ID) Register....................................................................................... 4-38
4.10 JTAG Boundary Scan Register (BSR)................................................................................. 4-38
Chapter 5
Programming the Peripherals
5.1 Peripheral Initialization Steps................................................................................................ 5-1
5.2 Mapping the Control Registers.............................................................................................. 5-2
5.3 Reading Status Registers ....................................................................................................... 5-2
5.4 Data Transfer Methods ..........................................................................................................5-3
5.4.1 Polling.................................................................................................................................... 5-3
5.4.2 Interrupts................................................................................................................................ 5-3
5.4.3 DMA......................................................................................................................................5-5
5.4.4 Advantages and Disadvantages ............................................................................................. 5-6
5.5 General-Purpose Input/Output (GPIO).................................................................................. 5-6
5.5.1 Port B Signals and Registers.................................................................................................. 5-7
5.5.2 Port C Signals and Registers.................................................................................................. 5-8
5.5.3 Port D Signals and Registers ................................................................................................. 5-8
5.5.4 Port E Signals and Registers.................................................................................................. 5-9
5.5.5 Triple Timer Signals and Registers ....................................................................................... 5-9
Chapter 6
Host Interface (HI08)
6.1 Features.................................................................................................................................. 6-1
6.1.1 DSP Core Interface................................................................................................................6-1
6.1.2 Host Processor Interface........................................................................................................6-2
6.2 Host Port Signals ................................................................................................................... 6-3
6.3 Overview................................................................................................................................ 6-4
6.4 Operation ............................................................................................................................... 6-6
6.4.1 Software Polling .................................................................................................................... 6-7
6.4.2 Core Interrupts and Host Commands..................................................................................... 6-7
6.4.3 Core DMA Access................................................................................................................. 6-9
6.4.4 Host Requests ........................................................................................................................ 6-9
6.4.5 Endian Modes ...................................................................................................................... 6-11
6.5 Boot-up Using the HI08 Host Port ...................................................................................... 6-12
6.6 DSP Core Programming Model........................................................................................... 6-13
6.6.1 Host Control Register (HCR) .............................................................................................. 6-14
6.6.2 Host Status Register (HSR) .................................................................................................6-15
6.6.3 Host Data Direction Register (HDDR)................................................................................ 6-16
6.6.4 Host Data Register (HDR)...................................................................................................6-16
6.6.5 Host Base Address Register (HBAR).................................................................................. 6-17
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6.6.6 Host Port Control Register (HPCR)..................................................................................... 6-18
6.6.7 Host Transmit (HTX) Register ............................................................................................ 6-21
6.6.8 Host Receive (HRX) Register.............................................................................................. 6-22
6.6.9 DSP-Side Registers After Reset .......................................................................................... 6-22
6.7 Host Programmer Model ..................................................................................................... 6-23
6.7.1 Interface Control Register (ICR) .........................................................................................6-24
6.7.2 Command Vector Register (CVR).......................................................................................6-26
6.7.3 Interface Status Register (ISR) ............................................................................................6-27
6.7.4 Interrupt Vector Register (IVR)...........................................................................................6-29
6.7.5 Receive Data Registers (RXH:RXM:RXL).........................................................................6-30
6.7.6 Transmit Data Registers (TXH:TXM:TXL)........................................................................ 6-30
6.7.7 Host-Side Registers After Reset .......................................................................................... 6-31
6.8 Programming Model Quick Reference................................................................................6-32
Chapter 7
Enhanced Synchronous Serial Interface (ESSI)
7.1 ESSI Enhancements............................................................................................................... 7-2
7.2 ESSI Data and Control Signals.............................................................................................. 7-3
7.2.1 Serial Transmit Data Signal (STD)........................................................................................7-3
7.2.2 Serial Receive Data Signal (SRD).........................................................................................7-3
7.2.3 Serial Clock (SCK)................................................................................................................7-3
7.2.4 Serial Control Signal (SC0)...................................................................................................7-4
7.2.5 Serial Control Signal (SC1)...................................................................................................7-4
7.2.6 Serial Control Signal (SC2)...................................................................................................7-6
7.3 Operation ............................................................................................................................... 7-6
7.3.1 ESSI After Reset.................................................................................................................... 7-6
7.3.2 Initialization...........................................................................................................................7-6
7.3.3 Exceptions.............................................................................................................................. 7-7
7.4 Operating Modes: Normal, Network, and On-Demand....................................................... 7-10
7.4.1 Normal/Network/On-Demand Mode Selection...................................................................7-10
7.4.2 Synchronous/Asynchronous Operating Modes ................................................................... 7-11
7.4.3 Frame Sync Selection .......................................................................................................... 7-11
7.4.4 Frame Sync Signal Format .................................................................................................. 7-11
7.4.5 Frame Sync Length for Multiple Devices............................................................................ 7-12
7.4.6 Word Length Frame Sync and Data Word Timing.............................................................. 7-12
7.4.7 Frame Sync Polarity............................................................................................................. 7-12
7.4.8 Byte Format (LSB/MSB) for the Transmitter......................................................................7-13
7.4.9 Flags..................................................................................................................................... 7-13
7.5 ESSI Programming Model................................................................................................... 7-14
7.5.1 ESSI Control Register A (CRA).......................................................................................... 7-14
7.5.2 ESSI Control Register B (CRB) .......................................................................................... 7-18
7.5.3 ESSI Status Register (SSISR).............................................................................................. 7-28
7.5.4 ESSI Receive Shift Register ................................................................................................7-29
7.5.5 ESSI Receive Data Register (RX) ....................................................................................... 7-30
7.5.6 ESSI Transmit Shift Registers.............................................................................................7-30
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7.5.7 ESSI Transmit Data Registers (TX[2–0])............................................................................7-33
7.5.8 ESSI Time Slot Register (TSR)........................................................................................... 7-33
7.5.9 Transmit Slot Mask Registers (TSMA, TSMB)..................................................................7-33
7.5.10 Receive Slot Mask Registers (RSMA, RSMB)................................................................... 7-35
7.6 GPIO Signals and Registers................................................................................................. 7-36
7.6.1 Port Control Registers (PCRC and PCRD)..........................................................................7-36
7.6.2 Port Direction Registers (PRRC and PRRD)....................................................................... 7-37
7.6.3 Port Data Registers (PDRC and PDRD).............................................................................. 7-38
Chapter 8
Serial Communication Interface (SCI)
8.1 Operating Modes.................................................................................................................... 8-1
8.1.1 Synchronous Mode ................................................................................................................ 8-2
8.1.2 Asynchronous Mode.............................................................................................................. 8-2
8.1.3 Multidrop Mode..................................................................................................................... 8-2
8.1.3.1 Transmitting Data and Address Characters..................................................................... 8-3
8.1.3.2 Wired-OR Mode .............................................................................................................. 8-3
8.1.3.3 Idle Line Wakeup............................................................................................................. 8-3
8.1.3.4 Address Mode Wakeup.................................................................................................... 8-3
8.2 I/O Signals ............................................................................................................................. 8-3
8.2.1 Receive Data (RXD).............................................................................................................. 8-4
8.2.2 Transmit Data (TXD)............................................................................................................. 8-4
8.2.3 SCI Serial Clock (SCLK) ...................................................................................................... 8-4
8.3 SCI After Reset...................................................................................................................... 8-5
8.4 SCI Initialization.................................................................................................................... 8-6
8.4.1 Preamble, Break, and Data Transmission Priority................................................................. 8-7
8.4.2 Bootstrap Loading Through the SCI (Boot Mode 2 or A)..................................................... 8-8
8.5 Exceptions.............................................................................................................................. 8-8
8.6 SCI Programming Model....................................................................................................... 8-9
8.6.1 SCI Control Register (SCR) ................................................................................................ 8-12
8.6.2 SCI Status Register (SSR) ................................................................................................... 8-17
8.6.3 SCI Clock Control Register (SCCR)................................................................................... 8-19
8.6.4 SCI Data Registers............................................................................................................... 8-22
8.6.4.1 SCI Receive Register (SRX).......................................................................................... 8-22
8.6.4.2 SCI Transmit Register (STX) ........................................................................................ 8-23
8.7 GPIO Signals and Registers................................................................................................. 8-24
8.7.1 Port E Control Register (PCRE)..........................................................................................8-24
8.7.2 Port E Direction Register (PRRE) ....................................................................................... 8-25
8.7.3 Port E Data Register (PDRE)............................................................................................... 8-25
Chapter 9
Triple Timer Module
9.1 Overview................................................................................................................................ 9-1
9.1.1 Triple Timer Module Block Diagram.................................................................................... 9-2
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9.1.2 Individual Timer Block Diagram........................................................................................... 9-2
9.2 Operation ............................................................................................................................... 9-3
9.2.1 Timer After Reset ..................................................................................................................9-3
9.2.2 Timer Initialization ................................................................................................................ 9-4
9.2.3 Timer Exceptions................................................................................................................... 9-4
9.3 Operating Modes.................................................................................................................... 9-5
9.3.1 Triple Timer Modes...............................................................................................................9-6
9.3.1.1 Timer GPIO (Mode 0) ..................................................................................................... 9-6
9.3.1.2 Timer Pulse (Mode 1)......................................................................................................9-8
9.3.1.3 Timer Toggle (Mode 2) ................................................................................................. 9-10
9.3.1.4 Timer Event Counter (Mode 3) ..................................................................................... 9-12
9.3.2 Signal Measurement Modes................................................................................................. 9-14
9.3.2.1 Measurement Input Width (Mode 4) ............................................................................. 9-14
9.3.2.2 Measurement Input Period (Mode 5)............................................................................. 9-16
9.3.2.3 Measurement Capture (Mode 6)....................................................................................9-18
9.3.3 Pulse Width Modulation (PWM, Mode 7)........................................................................... 9-19
9.3.4 Watchdog Modes.................................................................................................................9-22
9.3.4.1 Watchdog Pulse (Mode 9) ............................................................................................. 9-22
9.3.4.2 Watchdog Toggle (Mode 10).........................................................................................9-24
9.3.4.3 Reserved Modes............................................................................................................. 9-25
9.3.5 Special Cases ....................................................................................................................... 9-25
9.3.6 DMA Trigger.......................................................................................................................9-25
9.4 Triple Timer Module Programming Model.........................................................................9-25
9.4.1 Prescaler Counter................................................................................................................. 9-25
9.4.2 Timer Prescaler Load Register (TPLR)...............................................................................9-27
9.4.3 Timer Prescaler Count Register (TPCR) ............................................................................. 9-28
9.4.4 Timer Control/Status Register (TCSR)................................................................................ 9-28
9.4.5 Timer Load Register (TLR)................................................................................................. 9-33
9.4.6 Timer Compare Register (TCPR)........................................................................................9-34
9.4.7 Timer Count Register (TCR)...............................................................................................9-34
Appendix A
Bootstrap Program
A.1 Bootstrap Code ..................................................................................................................... A-1
A.2 Equates for I/O Port Programming....................................................................................... A-8
A.3 Host Interface (HI08) Equates .............................................................................................. A-9
A.4 Serial Communications Interface (SCI) Equates................................................................ A-10
A.5 Enhanced Synchronous Serial Interface (ESSI) Equates.................................................... A-11
A.6 Exception Processing Equates ............................................................................................ A-13
A.7 Timer Module Equates........................................................................................................ A-14
A.8 Direct Memory Access (DMA) Equates............................................................................. A-15
A.9 Phase Locked Loop (PLL) equates..................................................................................... A-17
A.10 Bus Interface Unit (BIU) Equates....................................................................................... A-18
A.11 Interrupt Equates................................................................................................................. A-20
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Appendix B
Programming Reference
B.1 Internal I/O Memory Map......................................................................................................B-3
B.2 Interrupt Sources and Priorities .............................................................................................B-8
B.3 Programming Sheets............................................................................................................B-12
Index
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Figures
1-1 DSP56303 Block Diagram....................................................................................... 1-11
2-1 Signals Identified by Functional Group..................................................................... 2-2
3-1 Default Settings (0, 0, 0)............................................................................................ 3-7
3-2 Instruction Cache Enabled (0, 0, 1) ........................................................................... 3-8
3-3 Switched Program RAM (0, 1, 0)..............................................................................3-9
3-4 Switched Program RAM and Instruction Cache Enabled (0, 1, 1).......................... 3-10
3-5 16-bit Space with Default RAM (1, 0, 0) ................................................................ 3-11
3-6 16-bit Space with Instruction Cache Enabled (1, 0, 1)............................................ 3-12
3-7 16-bit Space with Switched Program RAM (1, 1, 0)............................................... 3-13
3-8 16-bit Space, Switched Program RAM, Instruction Cache Enabled (1, 1, 1) ........ 3-14
4-1 Status Register (SR)................................................................................................. 4-10
4-2 Operating Mode Register (OMR)............................................................................4-15
4-4 Interrupt Priority Register-Peripherals (IPRP) (X:$FFFFFE)................................. 4-19
4-3 Interrupt Priority Register-Core (IPRC) (X:$FFFFFF)........................................... 4-19
4-5 PLL Control Register (PCTL) ................................................................................. 4-24
4-6 Bus Control Register (BCR).................................................................................... 4-25
4-7 DRAM Control Register (DCR)..............................................................................4-28
4-8 Address Attribute Registers (AAR[0–3]) (X:$FFFFF9–$FFFFF6) ........................ 4-30
4-9 DMA Control Register (DCR)................................................................................. 4-32
4-10 Identification Register Configuration (Revision E)................................................. 4-37
4-11 JTAG Identification Register Configuration (Revision E)......................................4-38
5-1 Memory Mapping of Peripherals Control Registers.................................................. 5-2
5-2 Port B Signals ............................................................................................................ 5-7
5-3 Port C Signals ............................................................................................................ 5-8
5-4 Port D Signals............................................................................................................5-8
5-5 Port E Signals............................................................................................................. 5-9
5-6 Triple Timer Signals..................................................................................................5-9
6-1 HI08 Block Diagram.................................................................................................. 6-5
6-2 HI08 Core Interrupt Operation .................................................................................. 6-8
6-3 HI08 Host Request Structure...................................................................................6-10
6-4 HI08 Read and Write Operations in Little Endian Mode........................................ 6-11
6-5 HI08 Read and Write Operations in Big Endian Mode...........................................6-12
6-6 Host Control Register (HCR) (X:$FFFFC2)........................................................... 6-14
6-7 Host Status Register (HSR) (X:$FFFFC3)..............................................................6-15
6-8 Host Data Direction Register (HDDR) (X:$FFFFC8)............................................. 6-16
6-9 Host Data Register (HDR) (X:$FFFFC8)................................................................ 6-16
6-10 Host Base Address Register (HBAR) (X:$FFFFC5)............................................... 6-17
6-11 Self Chip-Select Logic............................................................................................. 6-17
6-12 Host Port Control Register (HPCR) (X:$FFFFC4) ................................................. 6-18
6-13 Single-Strobe Mode.................................................................................................6-21
6-14 Dual-Strobe Mode.................................................................................................... 6-21
6-15 Interface Control Register (ICR) .............................................................................6-24
6-16 Command Vector Register (CVR)...........................................................................6-26
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Figures xiii
6-17 Interface Status Register (ISR) ................................................................................ 6-27
6-18 Interrupt Vector Register (IVR)............................................................................... 6-29
7-1 ESSI Block Diagram.................................................................................................. 7-1
7-2 ESSI Control Register A(CRA)............................................................................... 7-14
7-3 ESSI Clock Generator Functional Block Diagram..................................................7-17
7-4 ESSI Frame Sync Generator Functional Block Diagram ........................................ 7-17
7-5 ESSI Control Register B (CRB) .............................................................................. 7-18
7-6 CRB FSL0 and FSL1 Bit Operation (FSR = 0)....................................................... 7-24
7-7 CRB SYN Bit Operation.......................................................................................... 7-25
7-8 CRB MOD Bit Operation........................................................................................ 7-26
7-9 Normal Mode, External Frame Sync (8 Bit, 1 Word in Frame).............................. 7-27
7-10 Network Mode, External Frame Sync (8 Bit, 2 Words in Frame)........................... 7-27
7-11 ESSI Status Register (SSISR)..................................................................................7-28
7-12 ESSI Data Path Programming Model (SHFD = 0).................................................. 7-31
7-13 ESSI Data Path Programming Model (SHFD = 1).................................................. 7-32
7-14 ESSI Transmit Slot Mask Register A (TSMA) ....................................................... 7-33
7-15 ESSI Transmit Slot Mask Register B (TSMB)........................................................ 7-34
7-16 ESSI Receive Slot Mask Register A (RSMA)......................................................... 7-35
7-17 ESSI Receive Slot Mask Register B (RSMB)......................................................... 7-35
7-18 Port Control Registers (PCRC X:$FFFFBF) (PCRD X:$FFFAF)..........................7-36
7-19 Port Direction Registers (PRRC X:$FFFFBE) (PRRD X: $FFFFAE)....................7-37
7-20 Port Data Registers (PDRC X:$FFFFBD) (PDRD X: $FFFFAD).......................... 7-38
8-1 SCI Data Word Formats (SSFTD = 1), 1................................................................. 8-10
8-2 SCI Data Word Formats (SSFTD = 0), 2................................................................. 8-11
8-3 SCI Control Register (SCR) .................................................................................... 8-12
8-4 SCI Clock Control Register (SCCR)....................................................................... 8-19
8-5 SCI Baud Rate Generator ........................................................................................ 8-20
8-6 16 x Serial Clock...................................................................................................... 8-21
8-7 SCI Programming Model—Data Registers ............................................................. 8-22
8-8 Port E Control Register (PCRE X:$FFFF9F).......................................................... 8-24
8-9 Port E Direction Register (PRRE X:$FFFF9E)....................................................... 8-25
8-10 Port Data Registers (PDRE X:$FFFF9D)................................................................ 8-25
9-1 Triple Timer Module Block Diagram........................................................................ 9-2
9-2 Timer Module Block Diagram................................................................................... 9-3
9-3 Timer Mode (TRM = 1)............................................................................................. 9-7
9-4 Timer Mode (TRM = 0)............................................................................................. 9-7
9-5 Pulse Mode (TRM = 1).............................................................................................. 9-8
9-6 Pulse Mode (TRM = 0).............................................................................................. 9-9
9-7 Toggle Mode, TRM = 1........................................................................................... 9-10
9-8 Toggle Mode, TRM = 0........................................................................................... 9-11
9-9 Event Counter Mode, TRM = 1...............................................................................9-12
9-10 Event Counter Mode, TRM = 0...............................................................................9-13
9-11 Pulse Width Measurement Mode, TRM = 1............................................................ 9-15
9-12 Pulse Width Measurement Mode, TRM = 0............................................................ 9-15
9-13 Period Measurement Mode, TRM = 1.....................................................................9-16
9-14 Period Measurement Mode, TRM = 0.....................................................................9-17
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xiv DSP56303 User’s Manual
9-15 Capture Measurement Mode, TRM = 0................................................................... 9-18
9-16 Pulse Width Modulation Toggle Mode, TRM = 1................................................... 9-20
9-17 Pulse Width Modulation Toggle Mode, TRM = 0................................................... 9-21
9-18 Watchdog Pulse Mode.............................................................................................9-23
9-19 Watchdog Toggle Mode .......................................................................................... 9-24
9-20 Timer Module Programmer’s Model....................................................................... 9-26
9-21 Timer Prescaler Load Register (TPLR)...................................................................9-27
9-22 Timer Prescaler Count Register (TPCR) ................................................................. 9-28
9-23 Timer Control/Status Register (TCSR).................................................................... 9-28
B-1 Status Register (SR).................................................................................................B-12
B-2 Operating Mode Register (OMR)............................................................................B-13
B-3 Interrupt Priority Register-Core (IPRC) ..................................................................B-14
B-4 Interrupt Priority Register-Peripherals (IPRP) ........................................................B-15
B-5 Phase-Locked Loop Control Register (PCTL) ........................................................B-16
B-6 Bus Control Register (BCR)....................................................................................B-17
B-7 DRAM Control Register (DCR)..............................................................................B-18
B-8 Address Attribute Registers (AAR[3–0]) ................................................................B-19
B-9 DMA Control Registers 5–0 (DCR[5–0]) ...............................................................B-20
B-10 Host Transmit Data Register....................................................................................B-21
B-11 Host Base Address and Host Port Control Registers...............................................B-22
B-12 Host Control Register ..............................................................................................B-23
B-13 Interrupt Control and Command Vector Registers..................................................B-24
B-14 Interrupt Vector and Host Transmit Data Registers ................................................B-25
B-15 ESSI Control Register A (CRA)..............................................................................B-26
B-16 ESSI Control Register B (CRB) ..............................................................................B-27
B-17 ESSI Transmit and Receive Slot Mask Registers (TSM, RSM)..............................B-28
B-18 SCI Control Register (SCR) ....................................................................................B-29
B-19 SCI Clock Control Registers (SCCR)......................................................................B-30
B-20 Timer Prescaler Load Register (TPLR)...................................................................B-31
B-21 Timer Control/Status Register (TCSR)....................................................................B-32
B-22 Timer Load Registers (TLR) ...................................................................................B-33
B-23 Host Data Direction and Host Data Registers (HDDR, HDR)................................B-34
B-24 Port C Registers (PCRC, PRRC, PDRC).................................................................B-35
B-25 Port D Registers (PCRD, PRRD, PDRD)................................................................B-36
B-26 Port E Registers (PCRE, PRRE, PDRE)..................................................................B-37
Page 15
Tables xv
Tables
1-1 High True/Low True Signal Conventions ................................................................. 1-2
1-2 On-Chip Memory....................................................................................................... 1-9
2-1 DSP56303 Functional Signal Groupings................................................................... 2-1
2-2 Power Inputs .............................................................................................................. 2-3
2-3 Grounds......................................................................................................................2-4
2-4 Clock Signals.............................................................................................................2-5
2-5 Phase Lock Loop Signals........................................................................................... 2-5
2-6 External Address Bus Signals.................................................................................... 2-6
2-7 External Data Bus Signals ......................................................................................... 2-6
2-8 External Bus Control Signals..................................................................................... 2-6
2-9 Interrupt and Mode Control.......................................................................................2-9
2-10 Host Port Usage Considerations .............................................................................. 2-10
2-11 Host Interface...........................................................................................................2-11
2-12 Enhanced Synchronous Serial Interface 0 (ESSI0) ................................................. 2-15
2-13 Enhanced Synchronous Serial Interface 1 (ESSI1) ................................................. 2-17
2-14 Serial Communication Interface (SCI) .................................................................... 2-19
2-15 Triple Timer Signals................................................................................................2-20
2-16 JTAG/OnCE Interface ............................................................................................. 2-21
3-1 DSP56303 RAM Configurations............................................................................... 3-6
3-2 DSP56303 RAM Address Ranges by Configuration................................................. 3-6
4-1 DSP56303 Operating Modes ..................................................................................... 4-2
4-2 Status Register Bit Definitions ................................................................................ 4-10
4-3 Operating Mode Register (OMR) Bit Definitions...................................................4-15
4-4 Interrupt Priority Level Bits..................................................................................... 4-20
4-5 Interrupt Sources...................................................................................................... 4-20
4-6 Interrupt Source Priorities Within an IPL................................................................ 4-22
4-7 PLL Control Register (PCTL) Bit Definitions ........................................................ 4-24
4-8 Bus Control Register (BCR) Bit Definitions...........................................................4-26
4-9 DRAM Control Register (DCR) Bit Definitions.....................................................4-28
4-10 Address Attribute Registers (AAR[0–3]) Bit Definitions ....................................... 4-30
4-11 DMA Control Register (DCR) Bit Definitions....................................................... 4-32
5-1 DMA-Accessible Registers........................................................................................ 5-5
6-1 HI08 Signal Definitions for Operational Modes........................................................ 6-3
6-2 HI08 Data Strobe Signals .......................................................................................... 6-4
6-3 HI08 Host Request Signals........................................................................................ 6-4
6-4 DMA Request Sources............................................................................................... 6-9
6-5 HREQ Pin Operation In Single Request Mode (ICR[2]=HDRQ=0)....................... 6-10
6-6 HTRQ and HRRQ Pin Operation In Double Request Mode (ICR[2]=HDRQ=1) .. 6-10
6-7 HI08 Boot Modes..................................................................................................... 6-12
6-8 Host Control Register (HCR) Bit Definitions.......................................................... 6-14
6-9 Host Status Register (HSR) Bit Definitions ............................................................ 6-15
6-10 HDR and HDDR Functionality................................................................................ 6-16
6-11 Host Base Address Register (HBAR) Bit Definitions.............................................6-17
Page 16
xvi DSP56303 User’s Manual
6-12 Host Port Control Register (HPCR) Bit Definitions................................................ 6-18
6-13 DSP-Side Registers After Reset .............................................................................. 6-22
6-14 Host-Side Register Map........................................................................................... 6-24
6-15 Interface Control Register (ICR) Bit Definitions .................................................... 6-25
6-16 Command Vector Register (CVR) Bit Definitions.................................................. 6-27
6-17 Interface Status Register (ISR) Bit Definitions ....................................................... 6-28
6-18 Host-Side Registers After Reset .............................................................................. 6-31
6-19 HI08 Programming Model, DSP Side ..................................................................... 6-32
6-20 HI08 Programming Model: Host Side.....................................................................6-34
7-1 ESSI Clock Sources...................................................................................................7-3
7-2 Mode and Signal Definitions.....................................................................................7-5
7-3 ESSI Control Register A (CRA) Bit Definitions..................................................... 7-15
7-4 ESSI Control Register B (CRB) Bit Definitions ..................................................... 7-19
7-5 ESSI Status Register (SSISR) Bit Definitions......................................................... 7-28
7-6 ESSI Port Signal Configurations ............................................................................. 7-37
8-1 SCI Registers After Reset..........................................................................................8-5
8-2 SCI Control Register (SCR) Bit Definitions............................................................ 8-12
8-3 SCI Status Register..................................................................................................8-17
8-4 SCI Status Register (SSR) Bit Definitions .............................................................. 8-17
8-5 SCI Clock Control Register (SCCR) Bit Definitions .............................................. 8-19
9-1 Timer Prescaler Load Register (TPLR) Bit Definitions..........................................9-27
9-2 Timer Prescaler Count Register (TPCR) Bit Definitions ........................................ 9-28
9-3 Timer Control/Status Register (TCSR) Bit Definitions........................................... 9-28
9-4 Inverter (INV) Bit Operation................................................................................... 9-32
B-1 Guide to Programming Sheets...................................................................................B-2
B-2 Internal I/O Memory Map (X Data Memory)...........................................................B-3
B-3 Interrupt Sources........................................................................................................B-8
B-4 Interrupt Source Priorities Within an IPL................................................................B-10
Page 17
Overview 1-1
Chapter 1
Overview
This manual describes the DSP56303 24-bit digital signal processor (DSP), its memory,
operating modes, and peripheral modules. The DSP56303 is an implementation of the
DSP56300 core with a unique configuration of on-chip memory, cache, and peripherals.
Use this manual in conjunction with the DSP56300 Family Manual (DSP56300FM/AD),
which describes the CPU, core programming models, and instruction set. The DSP56303
Technical Data (DSP56303/D)—referred to as the data sheet—provides DSP56303 electrical
specifications, timing, pinout, and packaging descriptions.
You can obtain these documents—and the Motorola DSP development tools—through a local
Motorola Semiconductor Sales Office or authorized distributor. To receive the latest
information on this DSP, access the Motorola DSP home page at the address given on the
back cover of this document.
1.1 Manual Organization
This manual contains the following sections and appendices:
■ Chapter 1, Overview—Features list and block diagram, related documentation,
organization of this manual, and the notational conventions used.
■ Chapter 2, Signals/Connections—DSP56303 signals and their functional groupings.
■ Chapter 3, Memory Configuration—DSP56303 memory spaces, RAM configuration,
memory configuration bit settings, memory configurations, and memory maps.
■ Chapter 4, Core Configuration—Registers for configuring the DSP56300 core when
programming the DSP56303, in particular the interrupt vector locations and the
operation of the interrupt priority registers; operating modes and how they affect the
processor’s program and data memories.
■ Chapter 5, Programming the Peripherals—Guidelines on initializing the DSP56303
peripherals, including mapping control registers, specifying a method of transferring
data, and configuring for general-purpose input/output (GPIO).
Page 18
Manual Conventions
1-2 DSP56303 User’s Manual
■ Chapter 6, Host Interface (HI08)—Signals, architecture, programming model, reset,
interrupts, external host programming model, initialization, and a quick reference to
the HI08 programming model.
■ Chapter 7, Enhanced Synchronous Serial Interface (ESSI)—Enhancements, data and
control signals, programming model, operating modes, initialization, exceptions, and
GPIO.
■ Chapter 8, Serial Communication Interface (SCI)—Signals, programming model,
operating modes, reset, initialization, and GPIO.
■ Chapter 9, Triple Timer Module—Architecture, programming model, and operating
modes of three identical timer devices available for use as internals or event counters.
■ Appendix A, Bootstrap Code—Bootstrap code and equates for the DSP56303.
■ Appendix B, Programming Reference—Peripheral addresses, interrupt addresses, and
interrupt priorities for the DSP56303; programming sheets listing the contents of the
major DSP56303 registers for programmer’s reference.
1.2 Manual Conventions
This manual uses the following conventions:
■ Bits within registers are always listed from most significant bit (MSB) to least
significant bit (LSB).
■ Bits within a register are indicated AA[n – m], n > m, when more than one bit is
involved in a description. For purposes of description, the bits are presented as if they
are contiguous within a register. However, this is not always the case. Refer to the
programming model diagrams or to the programming sheets to see the exact location
of bits within a register.
■ When a bit is “set,” its value is 1. When a bit is “cleared,” its value is 0.
■ The word “assert” means that a high true (active high) signal is pulled high to V
CC
or
that a low true (active low) signal is pulled low to ground. The word “deassert” means
that a high true signal is pulled low to ground or that a low true signal is pulled high to
V
CC
. See Table 1-1.
Table 1-1. High True/Low True Signal Conventions
Signal/Symbol Logic State Signal State Voltage
PIN
1
True Asserted Ground
2
PIN False Deasserted V
CC
3
Page 19
Manual Conventions
Overview 1-3
■ Pins or signals that are asserted low (made active when pulled to ground) are indicated
like this:
— In text, they have an overbar: for example,
RESET is asserted low.
— In code examples, they have a tilde in front of their names. In Example 1-1, line 3
refers to the
SS0 signal (shown as ~SS0).
■ Sets of signals are indicated by the first and last signals in the set, for instance
HAD[0–7].
■ “Input/Output” indicates a bidirectional signal. “Input or Output” indicates a signal
that is exclusively one or the other.
■ Code examples are displayed in a monospaced font, as shown in Example 1-1.
■ Hex values are indicated with a $ preceding the hex value, as follows: $FFFFFF is the
X memory address for the core interrupt priority register.
■ The word “reset” is used in four different contexts in this manual:
— the reset signal, written as
RESET
— the reset instruction, written as RESET
— the reset operating state, written as Reset
— the reset function, written as reset
PIN True Asserted V
CC
PIN False Deasserted Ground
Note: 1. PIN is a generic term for any pin on the chip.
2. Ground is an acceptab le low v ol tag e le vel. See the appropri ate dat a s heet for the range of a cceptable low
voltage levels (typically a TTL logic low).
3. VCC is an acceptable high voltage level. See the appropriate data sheet for the range of acceptable high
voltage levels (typically a TTL logic high).
Example 1-1. Sample Code Listing
BFSET #$0007,X:PC C ; Con figure : line 1
; MISO0, MOSI0, SCK0 for SPI master line 2
; ~SS0 as PC3 for GPIO line 3
Table 1-1. High True/Low True Signal Conventions (Continued)
Signal/Symbol Logic State Signal State Voltage
Page 20
Features
1-4 DSP56303 User’s Manual
1.3 Features
The Motorola DSP56303, a member of the DSP56300 core family of programmable DSPs,
supports wireless infrastructure applications with general filtering operations. Like the other
family members, the DSP56303 uses a high-performance, single-clock-cycle- per-instruction
engine (code compatible with Motorola’s popular DSP56000 core family), a barrel shifter,
24-bit addressing, instruction cache, and DMA controller. The DSP56303 offers 100 million
instructions per second (MIPS) performance using an internal 100 MHz clock with 3.3 V core
and input/output (I/O) power.
All DSP56300 core family members contain the DSP56300 core and additional modules. The
modules are chosen from a library of standard predesigned elements, such as memories and
peripherals. New modules can be added to the library to meet customer specifications. A
standard interface between the DSP56300 core and the on-chip memory and peripherals
supports a wide variety of memory and peripheral configurations. In particular, the DSP56303
includes a JTAG port integrated with the Motorola OnCE™ module.
The DSP56303 is intended for use in telecommunication applications, such as multi-line
voice/data/fax processing, video conferencing, audio applications, control, and general digital
signal processing
1.4 DSP56300 Core
Core features are fully described in the DSP56300 Family Manual. This manual, in contrast,
documents pinout, memory, and peripheral features. Core features are as follows:
■ 100 million instructions per second (MIPS) with a 100 MHz clock at 3.0–3.6 V
■ Object code compatible with the DSP56000 core
■ Highly parallel instruction set
■ Data Arithmetic Logic Unit (Data ALU)
— Fully pipelined 24 x 24-bit parallel Multiplier-Accumulator (MAC)
— 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and
parsing)
— Conditional ALU instructions
— 24-bit or 16-bit arithmetic support under software control
■ Program Control Unit (PCU)
— Position Independent Code (PIC) support
— Addressing modes optimized for DSP applications (including immediate offsets)
— On-chip instruction cache controller
Page 21
DSP56300 Core Functional Blocks
Overview 1-5
— On-chip memory-expandable hardware stack
— Nested hardware DO loops
— Fast auto-return interrupts
■ Direct Memory Access (DMA)
— Six DMA channels supporting internal and external accesses
— One-, two-, and three- dimensional transfers (including circular buffering)
— End-of-block-transfer interrupts
— Triggering from interrupt lines and all peripherals
■ Phase Lock Loop (PLL)
— Allows change of low power Divide Factor (DF) without loss of lock
— Output clock with skew elimination
■ Hardware debugging support
— On-Chip Emulation (OnCE) module
— Joint Test Action Group (JTAG) Test Access Port (TAP)
— Address Trace mode reflects internal Program RAM accesses at the external port
■ Reduced power dissipation
— Very low-power CMOS design
— Wait and stop low-power standby modes
— Fully-static design specified to operate down to 0 Hz (dc)
— Optimized power-management circuitry (instruction-dependent,
peripheral-dependent, and mode-dependent)
1.5 DSP56300 Core Functional Blocks
The functional blocks of the DSP56300 core are:
■ Data arithmetic logic unit (ALU)
■ Address generation unit
■ Program control unit
■ PLL and clock oscillator
■ JTAG TAP and OnCE module
■ Memory
In addition, the DSP56303 provides a set of on-chip peripherals, discussed in Section 1.8,
Peripherals, on page 1-12.
Page 22
DSP56300 Core Functional Blocks
1-6 DSP56303 User’s Manual
1.5.1 Data ALU
The data ALU performs all the arithmetic and logical operations on data operands in the
DSP56300 core. These are the components of the data ALU:
■ Fully pipelined 24 × 24-bit parallel multiplier-accumulator
■ Bit field unit, comprising a 56-bit parallel barrel shifter (fast shift and normalization;
bit stream generation and parsing)
■ Conditional ALU instructions
■ Software-controllable 24-bit, 48-bit, or 56-bit arithmetic support
■ Four 24-bit or 48-bit input general-purpose registers: X1, X0, Y1, and Y0
■ Six data ALU registers (A2, A1, A0, B2, B1, and B0) that are concatenated into two
general-purpose, 56-bit accumulators, A and B, accumulator shifters
■ Two data bus shifter/limiter circuits
1.5.1.1 Data ALU Registers
The data ALU registers are read or written over the X data bus and the Y data bus as 16- or
32-bit operands. The source operands for the data ALU can be 16, 32, or 40 bits and always
originate from data ALU registers. The results of all data ALU operations are stored in an
accumulator. Data ALU operations are performed in two clock cycles in a pipeline so that a
new instruction can be initiated in every clock cycle, yielding an effective execution rate of
one instruction per clock cycle. The destination of every arithmetic operation can be a source
operand for the immediately following operation without penalty.
1.5.1.2 Multiplier-Accumulator (MAC)
The MAC unit comprises the main arithmetic processing unit of the DSP56300 core and
performs all of the calculations on data operands. For arithmetic instructions, the unit accepts
as many as three input operands and outputs one 56-bit result of the following form:
extension:most significant product:least significant product (EXT:MSP:LSP).
The multiplier executes 24-bit
× 24-bit parallel, fractional multiplies between
twos-complement signed, unsigned, or mixed operands. The 48-bit product is right-justified
and added to the 56-bit contents of either the A or B accumulator. A 56-bit result can be
stored as a 24-bit operand. The LSP is either truncated or rounded into the MSP. Rounding is
performed if specified.
Page 23
DSP56300 Core Functional Blocks
Overview 1-7
1.5.2 Address Generation Unit (AGU)
The AGU performs the effective address calculations using integer arithmetic necessary to
address data operands in memory and contains the registers that generate the addresses. It
implements four types of arithmetic: linear, modulo, multiple wrap-around modulo, and
reverse-carry. The AGU operates in parallel with other chip resources to minimize
address-generation overhead.
The AGU is divided into halves, each with its own identical address ALU. Each address ALU
has four sets of register triplets, and each register triplet includes an address register, offset
register, and modifier register. Each contains a 24-bit full adder (called an offset adder). A
second full adder (called a modulo adder) adds the summed result of the first full adder to a
modulo value that is stored in its respective modifier register. A third full adder (called a
reverse-carry adder) is also provided. The offset adder and the reverse-carry adder work in
parallel and share common inputs. The only difference between them is that the carry
propagates in opposite directions. Test logic determines which of the three summed results of
the full adders is output.
Each address ALU can update one address register from its own address register file during
one instruction cycle. The contents of the associated modifier register specify the type of
arithmetic used in the address register update calculation. The modifier value is decoded in
the address ALU.
1.5.3 Program Control Unit (PCU)
The PCU fetches and decodes instructions, controls hardware DO loops, and processes
exceptions. Its seven-stage pipeline controls the different processing states of the DSP56300
core. The PCU consists of three hardware blocks:
■ Program decode controller — decodes the 24-bit instruction loaded into the instruction
latch and generates all signals for pipeline control.
■ Program address generator — contains all the hardware needed for program address
generation, system stack, and loop control.
■ Program interrupt controller — arbitrates among all interrupt requests (internal
interrupts, as well as the five external requests
IRQA, IRQB, IRQC, IRQD, and NMI), and
generates the appropriate interrupt vector address.
PCU features include the following:
■ Position-independent code support
■ Addressing modes optimized for DSP applications (including immediate offsets)
■ On-chip instruction cache controller
Page 24
DSP56300 Core Functional Blocks
1-8 DSP56303 User’s Manual
■ On-chip memory-expandable hardware stack
■ Nested hardware DO loops
■ Fast auto-return interrupts
■ Hardware system stack
The PCU uses the following registers:
■ Program counter register
■ Status register
■ Loop address register
■ Loop counter register
■ Vector base address register
■ Size register
■ Stack pointer
■ Operating mode register
■ Stack counter register
1.5.4 PLL and Clock Oscillator
The clock generator in the DSP56300 core comprises two main blocks: the PLL, which
performs clock input division, frequency multiplication, and skew elimination; and the clock
generator, which performs low-power division and clock pulse generation. These features
allow you to:
■ Change the low-power divide factor without losing the lock
■ Output a clock with skew elimination
The PLL allows the processor to operate at a high internal clock frequency using a
low-frequency clock input, a feature that offers two immediate benefits:
■ A lower-frequency clock input reduces the overall electromagnetic interference
generated by a system.
■ The ability to oscillate at different frequencies reduces costs by eliminating the need to
add additional oscillators to a system.
Page 25
DSP56300 Core Functional Blocks
Overview 1-9
1.5.5 JTAG TAP and OnCE Module
In the DSP56300 core is a dedicated user-accessible TAP that is fully compatible with the
IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture
.
Problems with
testing high-density circuit boards led to the development of this standard under the
sponsorship of the Test Technology Committee of IEEE and the JTAG. The DSP56300 core
implementation supports circuit-board test strategies based on this standard. The test logic
includes a TAP with four dedicated signals, a 16-state controller, and three test data registers.
A boundary scan register links all device signals into a single shift register. The test logic,
implemented utilizing static logic design, is independent of the device system logic. For
details on the JTAG port, consult the DSP56300 Family Manual.
The OnCE module interacts with the DSP56300 core and its peripherals nonintrusively so that
you can examine registers, memory, or on-chip peripherals. This facilitates hardware and
software development on the DSP56300 core processor. OnCE module functions are
provided through the JTAG TAP signals. For details on the OnCE module, consult the
DSP56300 Family Manual.
1.5.6 On-Chip Memory
The memory space of the DSP56300 core is partitioned into program, X data, and Y data
memory space. The data memory space is divided into X and Y data memory in order to work
with the two address ALUs and to feed two operands simultaneously to the data ALU.
Memory space includes internal RAM and ROM and can be expanded off-chip under
software control. For details on internal memory, see Chapter 3, Memory Configuration.
Program RAM, instruction cache, X data RAM, and Y data RAM size are programmable, as
shown in Table 1-2.
There is an on-chip 192 x 24-bit bootstrap ROM.
Table 1-2. On-Chip Memory
Instruction
Cache
Switch
Mode
Program RAM
Size
Instruction
Cache Size
X Data RAM Size Y Data RAM Size
disabled disabled 4096 × 24-bit 0 2048 × 24-bit 2048 × 24-bit
enabled disabled 3072 × 24-bit 1024 × 24-bit 2048 × 24-bit 2048 × 24-bit
disabled enabled 2048 × 24-bit 0 3072 × 24-bit 3072 × 24-bit
enabled enabled 1024 × 24-bit 1024 × 24-bit 3072 × 24-bit 3072 × 24-bit
Page 26
Internal Buses
1-10 DSP56303 User’s Manual
1.5.7 Off-Chip Memory Expansion
Memory can be expanded off chip to the following capacities:
■ Data memory expansion to two 256 K × 24-bit word memory spaces using the standard
external address lines
■ Program memory expansion to one 256 K × 24-bit words memory space using the
standard external address lines
Further features of off-chip memory include the following:
■ External memory expansion port
■ Simultaneous glueless interface to static random access memory (SRAM) and dynamic
random access memory (DRAM)
1.6 Internal Buses
To provide data exchange between the blocks, the DSP56303 implements the following
buses:
■ Peripheral I/O expansion bus to peripherals
■ Program memory expansion bus to program ROM
■ X memory expansion bus to X memory
■ Y memory expansion bus to Y memory
■ Global data bus between PCU and other core structures
■ Program data bus for carrying program data throughout the core
■ X memory data bus for carrying X data throughout the core
■ Y memory data bus for carrying Y data throughout the core
■ Program address bus for carrying program memory addresses throughout the core
■ X memory address bus for carrying X memory addresses throughout the core
■ Y memory address bus for carrying Y memory addresses throughout the core.
The block diagram in Figure 1-1 illustrates these buses among other components.
Page 27
DMA
Overview 1-11
All internal buses on the DSP56300 family members are 24-bit buses. The program data bus
is also a 24-bit bus. Figure 1-1 shows a block diagram of the DSP56303.
Note: See Section 1.5.6, On-Chip Memory, on page 1-9 for memory size details.
1.7 DMA
The DMA block has the following features:
■ Six DMA channels supporting internal and external accesses
■ One-, two-, and three-dimensional transfers (including circular buffering)
■ End-of-block-transfer interrupts
■ Triggering from interrupt lines and all peripherals
Figure 1-1. DSP56303 Block Diagram
PLL
OnCE
Clock
Generator
Internal
Data
Bus
Switch
YAB
XAB
PAB
YDB
XDB
PDB
GDB
MODB/IRQB
MODC/IRQC
External
Data Bus
Switch
13
MODD/IRQD
DSP56300
616
24-Bit
24
18
DDB
DAB
Peripheral
Core
YM_EB
XM_EB
PM_EB
PIO_EB
Expansion Area
6
SCI
Interface
JTAG
5
3
RESET
MODA/IRQA
PINIT/NMI
2
Bootstrap
ROM
EXTAL
XTAL
Address
Control
Data
Triple
Timer
Host
Interface
HI08
ESSI
Interface
Address
Generation
Unit
Six-Channel
DMA Unit
Program
Interrupt
Controller
Program
Decode
Controller
Program
Address
Generator
Data ALU
24
× 24
+
56 → 56-bit MAC
Two 56-bit Accumulators
56-bit Barrel Shifter
Power
Management
External
Bus
Interface
and
I-Cache
Control
Extern al
Address
Bus
Switch
Memory
Expansion
Area
DE
Program RAM
4096 × 24 bits
(default)
X Data
RAM
2048 × 24
bits
(default)
Y Data
RAM
2048
× 24
bits
(default)
Page 28
Peripherals
1-12 DSP56303 User’s Manual
1.8 Peripherals
In addition to the core features, the DSP56303 provides the following peripherals:
■ As many as 34 user-configurable GPIO signals
■ HI08 to external hosts
■ Dual ESSI
■ SCI
■ Triple timer module
■ Memory switch mode
■ Four external interrupt/mode control lines
1.8.1 GPIO Functionality
The GPIO port consists of up to 34 programmable signals, also used by the peripherals (HI08,
ESSI, SCI, and timer). There are no dedicated GPIO signals. After a reset, the signals are
automatically configured as GPIO. Three memory-mapped registers per peripheral control
GPIO functionality. Programming techniques for these registers to control GPIO functionality
are detailed in Chapter 5, Programming the Peripherals.
1.8.2 HI08
The HI08 is a byte-wide, full-duplex, double-buffered parallel port that can connect directly
to the data bus of a host processor. The HI08 supports a variety of buses and provides
connection with a number of industry-standard DSPs, microcomputers, and microprocessors
without requiring any additional logic. The DSP core treats the HI08 as a memory-mapped
peripheral occupying eight 24-bit words in data memory space. The DSP can use the HI08 as
a memory-mapped peripheral, using either standard polled or interrupt programming
techniques. Separate double-buffered transmit and receive data registers allow the DSP and
host processor to transfer data efficiently at high speed. Memory mapping allows you to
program DSP core communication with the HI08 registers using standard instructions and
addressing modes.
Page 29
Peripherals
Overview 1-13
1.8.3 ESSI
The DSP56303 provides two independent and identical ESSIs. Each ESSI has a full-duplex
serial port for communication with a variety of serial devices, including one or more
industry-standard codecs, other DSPs, microprocessors, and peripherals that implement the
Motorola SPI. The ESSI consists of independent transmitter and receiver sections and a
common ESSI clock generator. ESSI capabilities include the following:
■ Independent (asynchronous) or shared (synchronous) transmit and receive sections
with separate or shared internal/external clocks and frame syncs
■ Normal mode operation using frame sync
■ Network mode operation with as many as 32 time slots
■ Programmable word length (8, 12, or 16 bits)
■ Program options for frame synchronization and clock generation
■ One receiver and three transmitters per ESSI
1.8.4 SCI
The SCI provides a full-duplex port for serial communication with other DSPs,
microprocessors, or peripherals such as modems. The SCI interfaces without additional logic
to peripherals that use TTL-level signals. With a small amount of additional logic, the SCI can
connect to peripheral interfaces that have non-TTL level signals, such as the RS-232C,
RS-422, etc. This interface uses three dedicated signals: transmit data, receive data, and SCI
serial clock. It supports industry-standard asynchronous bit rates and protocols, as well as
high-speed synchronous data transmission (up to 12.5 Mbps for a 100 MHz clock). SCI
asynchronous protocols include a multidrop mode for master/slave operation with wakeup on
idle line and wakeup on address bit capability. This mode allows the DSP56303 to share a
single serial line efficiently with other peripherals.
Separate SCI transmit and receive sections can operate asynchronously with respect to each
other. A programmable baud-rate generator provides the transmit and receive clocks. An
enable vector and an interrupt vector allow the baud-rate generator to function as a
general-purpose timer when the SCI is not using it or when the interrupt timing is the same as
that used by the SCI.
Page 30
Peripherals
1-14 DSP56303 User’s Manual
1.8.5 Timer Module
The triple timer module is composed of a common 21-bit prescaler and three independent and
identical general-purpose 24-bit timer/event counters, each with its own memory-mapped
register set. Each timer has the following properties:
■ A single signal that can function as a GPIO signal or as a timer signal
■ Uses internal or external clocking and can interrupt the DSP after a specified number
of events (clocks) or signal an external device after counting internal events
■ Connection to the external world through one bidirectional signal. When this signal is
configured as an input, the timer functions as an external event counter or measures
external pulse width/signal period. When the signal is used as an output, the timer
functions as either a timer, a watchdog, or a pulse width modulator.
Page 31
Signals/Connections 2-1
Chapter 2
Signals/Connections
The DSP56303 input and output signals are organized into functional groups, as shown in
Table 2-1 and illustrated in Figure 2-1. The DSP56303 operates from a 3 V supply; however,
some of the inputs can tolerate 5 V. A special notice for this feature is added to the signal
descriptions of those inputs.
Table 2-1. DSP56303 Functional Signal Groupings
Functional Group Number of Signals Description and Page
Power (V
CC
)18Table 2-2 on page 2-3
Ground (GND) 19 Table 2-3 on page 2-4
Clock 2 Table 2-4 on page 2-5
PLL 3 Table 2-5 on page 2-5
Address bus
Port A
1
18 Table 2-6 on page 2-6
Data bus 24 Table 2-7 on page 2-6
Bus control 13 Table 2-8 on page 2-6
Interrupt and mode control 5 Table 2-9 on page 2-9
HI08
Port B
2
16 Table 2-11 on page 2-11
ESSI
Ports C and D
3
12 Table 2-12 on page 2-15
Table 2-13 on page 2-17
SCI
Port E
4
3 Table 2-14 on page 2-19
Timer
5
3 Table 2-15 on page 2-20
OnCE/JTAG Port 6 Table 2-16 on page 2-21
NOTES:
1. Port A signals define the external memory interface port, including the external address bus, data bus, and
control signals. The data bus lines have internal keepers.
2. Port B signals are the HI08 port signals multiplexed with the GPIO signals. All Port B signals have keepers.
3. Port C and D signals are the two ESSI port signals multiplexed with the GPIO signals. All Port C and D
signals have keepers.
4. Port E signals are the SCI port signals multiplexed with the GPIO signals. All Port C signals have keepers.
5. All timer signals have keepers.
Page 32
2-2 DSP56303 User’s Manual
Figure 2-1. Signals Identified by Functional Group
DSP56303
24
18
External
Address Bus
External
Data Bus
External
Bus
Control
Enhanced
Synchronous Serial
Interface Port
0
(ESSI0)
2
Timers
3
PLL
JTAG/OnCE
Port
Power Inputs:
PLL
Internal Logic
Address Bus
Data Bus
Bus Control
HI08
ESSI/SCI/Timer
A[0–17]
D[0–23]
AA0/RAS0
–
AA3/RAS3
RD
WR
TA
BR
BG
BB
CAS
BCLK
BCLK
TCK
TDI
TDO
TMS
TRST
DE
CLKOUT
PCAP
PINIT/NMI
V
CCP
V
CCQ
V
CCA
V
CCD
V
CCC
V
CCH
V
CCS
4
Serial
Communications
Interface (SCI) Port
2
4
2
2
Grounds:
PLL
PLL
Internal Logic
Address Bus
Data Bus
Bus Control
HI08
ESSI/SCI/Timer
GND
P
GND
P1
GND
Q
GND
A
GND
D
GND
C
GND
H
GND
S
4
4
4
2
Interrupt/
Mode
Control
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
RESET
Host
Interface
(HI08) Port
1
Non-Multiplexed
Bus
H[0–7]
HA0
HA1
HA2
HCS/
HCS
Single DS
HRW
HDS
/HDS
Single HR
HREQ
/HREQ
HACK
/HACK
RXD
TXD
SCLK
SC0[0–2]
SCK0
SRD0
STD0
TIO0
TIO1
TIO2
8
3
4
2
EXTAL
XTAL
Clock
Enhanced
Synchronous Serial
Interface Port 1
(ESSI1)
2
SC1[0–2]
SCK1
SRD1
STD1
3
Multiplexed
Bus
HAD[0–7]
HAS
/HAS
HA8
HA9
HA10
Double DS
HRD
/HRD
HWR
/HWR
Double HR
HTRQ
/HTRQ
HRRQ
/HRRQ
Port B
GPIO
PB[0–7]
PB8
PB9
PB10
PB13
PB11
PB12
PB14
PB15
Port E GPIO
PE0
PE1
PE2
Port C GPIO
PC[0–2]
PC3
PC4
PC5
Port D GPIO
PD[0–2]
PD3
PD4
PD5
Timer GPIO
TIO0
TIO1
TIO2
Port A
4
Note: 1. The HI08 port supports a non-multiplexed or a multiplexed bus, single or double Data Strobe (DS), and single or
double Host Request (HR) configurations. Since each mode is configured independently, any combination of these
modes is possible. These HI08 signals can also be configured as GPIO signals (PB[0–15]). Signals with dual
designations (for example, HAS
/HAS) have configurable polarity.
2. The ESSI0, ESSI1, and SCI signals are multiplexed with the Port C GPIO signals (PC[0–5]), Port D GPIO signals
(PD[0–5]), and Port E GPIO signals (PE[0–2]), respectively.
3. TIO[0–2] can be configured as GPIO signals.
Page 33
Power
Signals/Connections 2-3
2.1 Power
Table 2-2. Power Inputs
Power Name Description
V
CCP
PLL Power—VCC dedicated for use with Phase Lock Loop (PLL). The voltage should be
well-regulated and the input should be provided with an extremely low impedance path to the VCC
power rail.
V
CCQ
(4) Quiet Power—An isolated power for the intern al pr ocessin g logic . This inpu t must be tied ex ternall y
to all other chip power inputs, except for V
CCP
. The user must p rovide adequ ate ex ternal deco upling
capacitors.
V
CCA
(4) Address Bus Power—An isolated power for sections of the address bus I/O drivers. This input
must be tied externally to all other chip power inputs, except for V
CCP
. The user must provide
adequate external decoupling capacitors.
V
CCD
(4) Data Bus Power—An isolated power for sections of the data bus I/O drivers. This in put must be tied
externall y to all other chip power in puts, except for V
CCP
. The user must provide adequate external
decoupling capacitors.
V
CCC
(2) Bus Control Power—An isolated power for the bus control I/O drivers. This input must be tied
externall y to all other chip power in puts, except for V
CCP
. The user must provide adequate external
decoupling capacitors.
V
CCH
Host Power—An isolated power for the HI08 I/O drivers. This input must be tied externally to all
other chip power inputs, except for V
CCP
. The user must provide adequate external decoupling
capacitors.
V
CCS
(2) ESSI, SCI, and Timer Power—An i solated powe r for the ESSI, SCI, and ti mer I/O drivers . This inpu t
must be tied externally to all other chip power inputs, except for V
CCP
. The user must provide
adequate external decoupling capacitors.
Note: These designations are package-dependent. Some packages connect all V
CC
inputs except V
CCP
to each
other internally. O n those pac kages, a ll power inpu t except V
CCP
are labeled VCC. The numbers of conne ctions
indicated in this table are minimum values; the total V
CC
connections are package-dependent.
Page 34
Ground
2-4 DSP56303 User’s Manual
2.2 Ground
Table 2-3. Grounds
Ground Name Description
GND
P
PLL Ground—Ground ded icated for PLL use. Th e connection sh ould be provided with an extremely
low-impedance path to ground. V
CCP
should be bypassed to GNDP by a 0.47 µF capacitor located
as close as possible to the chip package.
GND
P1
PLL Ground 1—Ground dedicated for PLL use. The connection should be provided with an
extremely low-impedance path to ground.
GND
Q
(4) Quiet Ground—An isolated ground for the internal processing logic. This connection must be tied
externally to all other chip ground connections, except GND
P
and GNDP1. The user must provide
adequate external decoupling capacitors.
GND
A (4)
Address Bus Ground—An isolated ground for sections of the address bus I/O drivers. This
connection must be tied externally to all other chip ground connections, except GND
P
and GNDP1.
The user must provide adequate external decoupling capacitors.
GND
D
(4) Data Bus Ground—An isolated ground for sections of the data bus I/O drivers. This connection
must be tied externally to all other chip ground connections, except GND
P
and GNDP1. The user
must provide adequate external decoupling capacitors.
GND
C
(2) Bus Control Ground—An isolated ground for the bus control I/O drivers. This connection must be
tied externally to all other chip ground connections, except GND
P
and GNDP1. The user must
provide adequate external decoupling capacitors.
GND
H
Host Ground—An isolated ground for the HI08 I/O drivers. This connection must be tied externally
to all other chip ground connections, except GND
P
and GNDP1. The user must provide adequate
external decoupling capacitors.
GND
S
(2) ESSI, SCI, and Timer Ground—An isolated ground for the ESSI, SCI, and timer I/O drivers. This
connection must be tied externally to all other chip ground connections, except GND
P
and GNDP1.
The user must provide adequate external decoupling capacitors.
Note: These designations are package-dependent. Some packages connect all GND inputs except GND
P
and
GND
P1
to each other internally. On those packages, all ground connections except GNDP and GNDP1 are
labeled GND. The numbers of connections indicated in this table are minimum values; the total GND
connections are package-dependent.
Page 35
Clock
Signals/Connections 2-5
2.3 Clock
2.4 Phase Lock Loop (PLL)
Table 2-4. Clock Signals
Signal
Name
Type
State During
Reset
Signal Description
EXTAL Input Input External Clock/Crystal Input—Interfaces the internal crystal oscillator
input to an external crystal or an external clock.
XTAL Output Chip-driven Crystal Output—Connects the internal crystal oscillator output to an
external crystal. If an external clock is used, leave XTAL unconnected.
Table 2-5. Phase Lock Loop Signals
Signal Name Type
State During
Reset
Signal Description
PCAP Input Input PLL Capacitor—Connects an off-chip capac ito r to t he PL L filter. See
the DSP56303 Technical Data sheet to determine the correct PLL
capacitor value. Connect one capacitor terminal to PCAP and the
other terminal to V
CCP
.
If the PLL is not used, PCAP can be tied to V
CC
, GND, or left floating.
CLKOUT Output Chip-driven Clock Output—Provides an output clock sync hroniz ed to the in ternal
core clock phase.
If the PLL is enabled and both the multiplication and division factors
equal one, then CLKOUT is also synchronized to EXTAL.
If the PLL is disabled, the CLKOUT frequency is half the frequency of
EXTAL.
PINIT/NMI
Input Input PLL Initial/Non-Maskable Interrupt—During assertion of RESET,
the value of PINIT/NMI
is written into the PLL Enable (PEN) bit of the
PLL control register, determining whether the PLL is enabled or
disabled. After RESET
deassertion and during normal instruction
processing, the PINIT/NMI
Schmitt-trigger input is a
negative-edge-trigg ered Non- Ma sk abl e Interr upt (N MI) requ es t
internally synchronized to CLKOUT.
PINIT/NMI
can tolerate 5 V.
Page 36
External Memory Expansion Port (Port A)
2-6 DSP56303 User’s Manual
2.5 External Memory Expansion Port (Port A)
Note: When the DSP56303 enters a low-power standby mode (Stop or Wait), it releases
bus mastership and tri-states the relevant Port A signals: A[0–17], D[0–23],
AA0/RAS0
–AA3/RAS3, RD, WR, BB, CAS, BCLK, BCLK.
2.5.1 External Address Bus
2.5.2 External Data Bus
2.5.3 External Bus Control
Table 2-6. External Address Bus Signals
Signal
Name
Type
State During Reset,
Stop, or Wait
Signal Description
A[0–17] Output Tri-stated Address Bus—When the DSP is the bus master, A[0–17] specify
the address for external program and data memory accesses.
Otherwise, the signals are tri-stated. To minimize power
dissipation, A[0–17] do not change state when external memory
spaces are not being accessed.
Table 2-7. External Data Bus Signals
Signal
Name
Type
State During Reset,
Stop, or Wait
Signal Description
D[0–23] Input/Output Tri-stated Data Bus—When the DSP is the bus master, D[0–23] provide the
bidirectional data bus for external program and data memory
accesses. Otherwise, D[0–23] are tri-stated.
Table 2-8. External Bus Control Signals
Signal
Name
Type
State During Reset,
Stop, or Wait
Signal Description
AA0/RAS0
–
AA3/RAS3
Output Tri-stated Address Attribute or Row Address Strobe—As AA, these signals
function as chip selects or additional address lines. Unlike address
lines, however, the AA lines do not hold their state a fter a read or wr ite
operation. As RAS
, these signals can be used for Dynamic Random
Access Memory (DRAM ) interfac e. These signal s have pr ogrammable
polarity.
RD
Output Tri-stated Read Enable—When the DSP is the bus master, RD is asserted to
read external memory on the data bus (D[0–23]). Otherwise, RD
is
tri-stated.
WR Output Tri-stated Write Enable—When the DSP is the bus master, WR is asserted to
write external memory on the data bus (D[0–23]). Otherwise, WR
is
tri-stated.
Page 37
External Memory Expansion Port (Port A)
Signals/Connections 2-7
TA Input Ignored In put Transfer Acknowledge—If the DSP56303 is the bus master and
there is no external bus activity, or the DSP56303 is not the bus
master, the TA input is ignore d. The TA input is a Data Transfer
Acknowledge (DTACK) fu nction that c an extend an ex ternal bus c ycle
indefinitely. Any number of wait states (1, 2,..., infinity) can be added
to the wait states inserted by the BCR by keeping TA
deasserted. In
typical operation, TA
is deasserted at the start of a bus cycl e, asserted
to enable completion of t he bu s cycle , and dea sserte d before the nex t
bus cycle. The current bus cycle completes one clock period after TA
is asserted synchronous to CLKOUT. The number of wait states is
determined by the TA
input or by the Bus Control Register (BCR),
whichever is longer. The BCR can set the minimum number of wait
states in external bus cycles.
To use the TA functionality, the BCR must be programmed to at least
one wait state. A zero wait state access cannot be extended by TA
deassertion; otherwi se impro per operati on may result. TA
can operate
synchronously or asynchronously, depending on the setting of the
TAS bit in the Operating Mode Register (OMR).
TA functionality cannot be used during DRAM-type accesses;
otherwise improper operation may result.
BR Output Output
(deasserted)
Bus Request—Asserted when the DSP re quests bus masters hip a nd
deasserted when the DSP no longer needs the bus. BR
can be
asserted or deasserted independently of whether the DSP56303 is a
bus master or a bus slave. Bus “parking” allows BR to be deasserted
even though the DSP56303 is the bus master (see the description of
bus “parking” in the BB signal description). The Bus Request Hold
(BRH) bit in the BCR allows BR
to be asserted under software co ntrol,
even though the DSP does not n eed the bus . BR
is typically sent to an
external bus arbitrator that controls the priority, parking and tenure of
each master on the same external bus. BR is affected only by DSP
requests for the external bus, never for the internal bus. During
hardware reset, BR is deasserted and the arbitration is reset to the
bus slave state.
BG Input Ignored Input Bus Grant—Must be asserted/deasserted synchronous to CLKOUT
for proper operation. An external bus arbitration circuit asserts BG
when the DSP56303 becomes the next bus master. When BG
is
asserted, the DSP56303 must wait until BB
is deasserted before
taking bus mastership. When BG
is deasserted, bus mastership is
typically given up at the end of the current bus cycle. This may occur
in the middle of an instruction that requires more than one external
bus cycle fo r execution.
Table 2-8. External Bus Control Signals (Continued)
Signal
Name
Type
State During Reset,
Stop, or Wait
Signal Description
Page 38
External Memory Expansion Port (Port A)
2-8 DSP56303 User’s Manual
BB Input/
Output
Input Bus Busy—Indicates that th e bus is ac tive an d must be a sserte d and
deasserted synchrono us to CL KOUT. On ly after BB
is deasserted can
the pending bus master become the bus master (and then assert the
signal again). The bu s maste r can keep BB asserted after ceasing bus
activity, regardless of whether BR
is asserted or deasserted. This is
called “bus parking” and allows the current bus master to reuse the
bus without re-arbitration until another device requires the bus. BB is
deasserted by an “active pull-up” method (that is, BB
is driven high
and then released and held high by an external pull-up resistor).
BB
requires an external pull-up resistor.
CAS
Output Tri-stated Column Address Strobe—When the DSP is the bus master, DRAM
uses CAS
to strobe the column address. Otherwise, if the Bus
Mastership Enable (BME) bit in t he DRAM C ontrol Regi ster is cleared,
the signal is tri-stated.
BCLK Output Tri-stated Bus Clock—When the DSP is the bus master, BCLK is active when
the OMR[ATE] is set. When BCLK is active and synchronized to
CLKOUT by the internal PLL, BCLK precedes CLKOUT by one-fourth
of a clock cycle.
BCLK
Output Tri-stated Bus Clock Not—When the DSP is the bus master, BCLK is the
inverse of the BCLK signal. Otherwise, the signal is tri-stated.
Table 2-8. External Bus Control Signals (Continued)
Signal
Name
Type
State During Reset,
Stop, or Wait
Signal Description
Page 39
Interrupt and Mode Control
Signals/Connections 2-9
2.6 Interrupt and Mode Control
The interrupt and mode control signals select the chip’s operating mode as it comes out of
hardware reset. After
RESET is deasserted, these inputs are hardware interrupt request lines.
Table 2-9. Interrupt and Mode Control
Signal Name Type
State During
Reset
Signal Description
RESET
Input Input Reset—Deassertion of RESET is internally synchronized to the clock
out (CLKOUT). When asserted, the chip is placed in the Reset state
and the internal phase generator is reset. The Schmitt-trigger input
allows a slowly rising input (such as a capacitor charging) to reset the
chip reliably. If RESET is deasserted synchronous to CLKOUT, exact
start-up timing is gua ran t eed , all owing multiple processo rs to start and
operate synchronously. When the RESET
signal is deasserted, the
initial chip operating mode is latched from the MODA, MODB, MODC,
and MODD inputs. The RESET signal must be asserted after
power-up.
RESET
can tolerate 5 V.
MODA/IRQA
Input Input Mode Select A/External Interrupt Request A—Selects the initial c hip
operating mode during hardware reset and becomes a level-sensitive
or negative-edge-triggered, maskable interrupt request input during
normal instruction processing. MODA/IRQA
MODA, MODB, MODC,
and MODD select one of sixteen initial chip operating modes, latched
into the OMR when the RESET signal is deasserted.
Internally synchronized to CLKOUT. If IRQA
is asserted synchronous
to CLKOUT, multiple processors can be re-synchronized using the
WAIT instruction and asserting IRQA to exit the Wait state. If a STOP
instruction puts the processor is in the Stop standby state and IRQA
is
asserted, the processor exits the Stop state.
MODA/IRQA
can tolerate 5 V.
MODB/IRQB
Input Input Mode Select B/External Interrupt Request B—Selects the initial c hip
operating mode during hardware reset and becomes a level-sensitive
or negative-edge-triggered, maskable interrupt request input during
normal instruction processing. MODA, MODB, MODC, and MODD
select one of sixteen initial chip operating modes, latched into OMR
when the RESET
signal is deasserted.
Internally synchronized to CLKOUT. If IRQB is asserted synchronous
to CLKOUT, multiple processors can be re-synchronized using the
WAIT instruction and asserting IRQB
to exit the Wait state.
MODB/IRQB can tolerate 5 V.
Page 40
Host Interface (HI08)
2-10 DSP56303 User’s Manual
2.7 Host Interface (HI08)
The HI08 provides a fast, parallel data-to-8-bit port that can directly connect to the host bus.
The HI08 supports a variety of standard buses and can directly connect to a number of
industry-standard microcomputers, microprocessors, DSPs, and DMA hardware.
2.7.1 Host Port Usage Considerations
Careful synchronization is required when the system reads multiple-bit registers that are
written by another asynchronous system. This is a common problem when two asynchronous
systems are connected (as they are in the Host port). The considerations for proper operation
are discussed in Table 2-10.
MODC/IRQC Input Input Mode Sele ct C/External Interrupt Requ est C—Selects th e initial chi p
operating mode during hardware reset and becomes a level-sensitive
or negative-edge-triggered, maskable interrupt request input during
normal instruction processing. MODA, MODB, MODC, and MODD
select one of sixteen initial chip operating modes, latched into OMR
when the RESET
signal is deasserted.
Internally synchronized to CLKOUT. If IRQC
is asserted synchronous
to CLKOUT, multiple processors can be re-synchronized using the
WAIT instruction and asserting IRQC to exit the Wait state.
MODC/IRQC can tolerate 5 V.
MODD/IRQD
Input Input Mode Select D/External Interrupt Request D—Selects the initial c hip
operating mode during hardware reset and becomes a level-sensitive
or negative-edge-triggered, maskable interrupt request input during
normal instruction processing. MODA, MODB, MODC, and MODD
select one of sixteen initial chip operating modes, latched into OMR
when the RESET
signal is deasserted.
Internally synchronized to CLKOUT. If IRQD is asserted synchronous
to CLKOUT, multiple processors can be re-synchronized using the
WAIT instruction and asserting IRQD to exit the Wait state.
MODD/IRQD
can tolerate 5 V.
Table 2-10. Host Port Usage Considerations
Action Description
Asynchronous read of receive
byte registers
When reading the receive byte registers, Receive register High (RXH), Receive register
Middle (RXM), or Receive register Low (RXL), the host inte rfac e pro gram m er shoul d us e
interrupts or poll the Receive Register Data Full (RXDF) flag that indicates data is
available. This assures that the data in the receive byte registers is valid.
Table 2-9. Interrupt and Mode Control (Continued)
Signal Name Type
State During
Reset
Signal Description
Page 41
Host Interface (HI08)
Signals/Connections 2-11
2.7.2 Host Port Configuration
HI08 signal functions vary according to the programmed configuration of the interface as
determined by the 16 bits in the HI08 Port Control Register (HPCR). Refer to the Chapter 6,
Host Interface (HI08), for detailed descriptions of HI08 configuration registers.
Asynchronous write to transmit
byte registers
The host interface programmer should not write to the transmit byte registers, Transmit
register High (TXH), Transmit register Middle (TXM), or Transmit register Low (TXL),
unless the Trans mit re gister Data E mpty (TXDE) bit i s set i ndica ting t hat th e trans mit byte
registers are empty . This g uarante es that th e transm it byt e regist ers tr ansfer valid d ata to
the Host Receive (HRX) register.
Asynchronous write to host
vector
The host interfa ce p rogra mmer must change th e Ho st Vector (HV) regist er onl y w hen th e
Host Command bit (HC) is clear. This practice guarantees that the DSP interrupt control
logic receives a stable vector.
Table 2-11. Host Interface
Signal Name Type
State During
Reset or Stop
1
Signal Description
H[0–7]
HAD[0–7]
PB[0–7]
Input/Output
Input/Output
Input or
Output
Disconnected
internally
Host Data—When the HI08 is programmed to interface with a
non-multiplexed host bus and the HI function is selected, these signals
are lines 0–7 of the Data bus.
Host Address—When the HI08 is programmed to interface with a
multiplexed host bus and the HI function is selected, these signals are
lines 0–7 of the Address/Data bus.
Port B 0–7—When the HI08 is confi gure d as G PIO thro ugh the H PCR ,
these signals are individually programmed through the HI08 Data
Direction Register (HDDR).
This input is 5 V tolerant.
HA0
HAS
/HAS
PB8
Input
Input
Input or
Output
Disconnected
internally
Host Address Input 0—When the HI08 is programmed to interface
with a non-multiplexed host bus and the HI function is selected, this
signal is line 0 of the Host Address bus.
Host Address Strobe—When the HI08 is programmed to interface
with a multiplexed host bus and the HI function is selected, this signal is
the Host Address Strobe (HAS) Schmitt-trigg er input. The pol arity of the
address strobe is programmable, but is configured active-low (HAS
)
following reset.
Port B 8—When the HI08 is configured as GPIO through the HPCR,
this signal is individually programmed through the HDDR.
This input is 5 V tolerant.
Table 2-10. Host Port Usage Considerations (Continued)
Action Description
Page 42
Host Interface (HI08)
2-12 DSP56303 User’s Manual
HA1
HA8
PB9
Input
Input
Input or
Output
Disconnected
internally
Host Address Input 1—When the HI08 is programmed to interface
with a non-multiplexed host bus and the HI function is selected, this
signal is line 1 of the Host Address bus.
Host Address 8—When the HI08 is programmed to interface with a
multiplexed host bus an d th e H I func ti on is selected, this signal is line 8
of the Host Address bus.
Port B 9—When the HI08 is configured as GPIO through the HPCR,
this signal is individually programmed through the HDDR.
This input is 5 V tolerant.
HA2
HA9
PB10
Input
Input
Input or
Output
Disconnected
internally
Host Address Input 2—When the HI08 is programmed to interface
with a non-multiplexed host bus and the HI function is selected, this
signal is line 2 of the Host Address bus.
Host Address 9—When the HI08 is programmed to interface with a
multiplexed host bus an d th e H I func ti on is selected, this signal is line 9
of the Host Address bus.
Port B 10—When the HI08 is configured as GPIO through the HPCR,
this signal is individually programmed through the HDDR.
This input is 5 V tolerant.
HRW
HRD
/HRD
PB11
Input
Input
Input or
Output
Disconnected
internally
Host Read/Write—When the HI08 is programmed to interface with a
single-data-strobe h ost bus an d the HI f unction is selecte d, this sign al is
the Host Read/Write input.
Host Read Data—When the HI08 is programmed to interface with a
double-data-strobe host bus and the HI function is selected, this signal
is the Host Read Data strobe (HRD) Schmitt-trigger input. The polarity
of the data strobe is programmable, but is configured as active-low
(HRD
) after reset.
Port B 11—When the HI08 is configured as GPIO through the HPCR,
this signal is individually programmed through the HDDR.
This input is 5 V tolerant.
Table 2-11. Host Interface (Continued)
Signal Name Type
State During
Reset or Stop
1
Signal Description
Page 43
Host Interface (HI08)
Signals/Connections 2-13
HDS/HDS
HWR
/HWR
PB12
Input
Input
Input or
Output
Disconnected
internally
Host Data Strobe—When the HI08 is programmed to interface with a
single-data-strobe h ost bus an d the HI f unction is selecte d, this sign al is
the Host Data Strobe (HDS) Schmitt-trigger input. The polarity of the
data strobe is programmable, but is configured as active-low (HDS
)
following reset.
Host Write Data—When the HI08 is programmed to interface with a
double-data-strobe host bus and the HI function is selected, this signal
is the Host Write Data Strobe (HWR) Schmitt-trigger input. The polarity
of the data strobe is programmable, but is configured as active-low
(HWR
) following reset.
Port B 12—When the HI08 is configured as GPIO through the HPCR,
this signal is individually programmed through the HDDR.
This input is 5 V tolerant.
HCS
HA10
PB13
Input
Input
Input or
Output
Disconnected
internally
Host Chip Select—When the HI08 is programmed to interface with a
non-multiplexed host bus and the HI function is selected, this signal is
the Host Chip Select (HCS) input. The polarity of the chip select is
programmable, but is configured active-low (HCS
) after reset.
Host Address 10—When the HI08 is programmed to interface with a
multiplexed host bus and the HI function is selected, this signal is line
10 of the Host Address bus.
Port B 13—When the HI08 is configured as GPIO through the HPCR,
this signal is individually programmed through the HDDR.
This input is 5 V tolerant.
HREQ
/HREQ
HTRQ
/HTRQ
PB14
Output
Output
Input or
Output
Disconnected
internally
Host Request—When the HI08 is programmed to interface with a
single host request host bus and the HI function is selected, this signal
is the Host Request (HREQ) output. The polarity of the host request is
programmable, but is configured as active-low (HREQ
) following reset.
The host request can be programmed as a driven or open-drain output.
Transmit Host Request—When the HI08 is programmed to interface
with a double hos t re que st ho st bus and the HI function is selec ted , this
signal is the Transmit Host Request (HTRQ) output. The polarity of the
host request is programmable, but is configured as active-low (HTRQ
)
following reset. The host request may be programmed as a driven or
open-drain output.
Port B 14—When the HI08 is programmed to interface with a
multiplexed host bus and the signal is configured as GPIO through the
HPCR, this signal is individually programmed through the HDDR.
This input is 5 V tolerant.
Table 2-11. Host Interface (Continued)
Signal Name Type
State During
Reset or Stop
1
Signal Description
Page 44
Host Interface (HI08)
2-14 DSP56303 User’s Manual
HACK/HACK
HRRQ
/HRRQ
PB15
Input
Output
Input or
Output
Disconnected
internally
Host Acknowledge—When the HI08 is programmed to interface with a
single host request host bus and the HI function is selected, this signal
is the Host Acknowledge (HACK) Schmitt-trigger input. The polarity of
the host acknowledge is prog ram ma ble , but is c onfi gured as active-low
(HACK) after reset.
Receive Host Request—When the HI08 is programmed to interface
with a double hos t re que st ho st bus and the HI function is selec ted , this
signal is the Receive Host Request (HRRQ) output. The polarity of the
host request is programmable, but is configured as active-low (HRRQ
)
after reset. The host request may be programmed as a driven or
open-drain output.
Port B 15
When the HI08 is configured as GPIO through the HPCR, this signal is
individually programmed through the HDDR.
This input is 5 V tolerant.
Note: 1. The Wait processing state does not affect the signal state.
Table 2-11. Host Interface (Continued)
Signal Name Type
State During
Reset or Stop
1
Signal Description
Page 45
Enhanced Synchronous Serial Interface 0 (ESSI0)
Signals/Connections 2-15
2.8 Enhanced Synchronous Serial Interface 0 (ESSI0)
Two synchronous serial interfaces (ESSI0 and ESSI1) provide a full-duplex serial port for
serial communication with a variety of serial devices, including one or more
industry-standard CODECs, other DSPs, microprocessors, and peripherals that implement the
Motorola Serial Peripheral Interface (SPI).
Table 2-12. Enhanced Synchronous Serial Interface 0 (ESSI0)
Signal
Name
Type
State During
1
Signal Description
Reset Stop
SC00
PC0
Input or
Output
Input Disconnected
internally
Serial Control 0—Functions in either Synchronous or
Asynchronous mode. For Asynchronous mode, this signal is
the receive clock I/O (Schmitt-trigger input). For Synchronous
mode, this signal i s either fo r Trans mitter 1 outp ut or Seri al I/O
Flag 0.
Port C 0—The default configuration following reset is GPIO.
For PC0, signal direction is controlled through the Port C
Direction Register (PRRC).
This signal is configured as SC00 or PC0 through the Port C
Control Register (PCRC).
This input is 5 V tolerant.
SC01
PC1
Input/Output
Input or
Output
Input Disconnected
internally
Serial Control 1—Functions in either Synchronous or
Asynchronous mode. For Asynchronous mode, this signal is
the receiver frame sync I/O. For Synchronous mode, this
signal is either Transmitter 2 output or Serial I/O Flag 1.
Port C 1—The default configuration following reset is GPIO.
For PC1, signal direction is controlled through PRRC.
This signal is configured as SC01 or PC1 through PCRC.
This input is 5 V tolerant.
SC02
PC2
Input/Output
Input or
Output
Input Disconnected
internally
Serial Control Signal 2—The frame sync for both the
transmitter and receiver in Synchronous mode, and for the
transmitter only in Asynchronous mode. When configured as
an output, this signal is the internally generated frame sync
signal. When configured as an input, this signal receives an
external frame sync signa l for the tra nsmi tter (and the re ceiver
in synchronous operation).
Port C 2—The default configuration following reset is GPIO.
For PC2, signal direction is controlled through PRRC.
This signal is configured as SC02 or PC2 through PCRC.
This input is 5 V tolerant.
Page 46
Enhanced Synchronous Serial Interface 0 (ESSI0)
2-16 DSP56303 User’s Manual
SCK0
PC3
Input/Output
Input or
Output
Input Disconnected
internally
Serial Clock—Provides the serial bit rate clock for the ESSI
interface for both the transmitte r and receiver in Synchronous
modes, or the transmitter only in Asynchronous modes.
Although an external serial clock can be independent of and
asynchronous to the DSP system clock, it must exceed the
minimum clock cycle time of 6 T (that is, the system clock
frequency must be at least three times the ext ernal ESSI clock
frequency). The ESSI needs a t le as t thre e DSP p has es ins ide
each half of the serial clock.
Port C 3—The default configuration following reset is GPIO.
For PC3, signal direction is controlled through PRRC.
This signal is configured as SCK0 or PC3 through PCRC.
This input is 5 V tolerant.
SRD0
PC4
Input
Input or
Output
Input Disconnected
internally
Serial Receive Data—Receives serial data and transfers the
data to the ESSI receive shift register. SRD0 is an input when
data is being received.
Port C 4—The default configuration following reset is GPIO.
For PC4, signal direction is controlled through PRRC.
This signal is configured as SRD0 or PC4 through PCRC.
This input is 5 V tolerant.
STD0
PC5
Output
Input or
Output
Input Disconnected
internally
Serial Transmit Data—Transmits data from the serial
transmit shift register. STD0 is an output when data is being
transmitted.
Port C 5—The default configuration following reset is GPIO.
For PC5, signal direction is controlled through PRRC.
This signal is configured as STD0 or PC5 through PCRC.
This input is 5 V tolerant.
Note: 1. The Wait processing state does not affect the signal state.
Table 2-12. Enhanced Synchronous Serial Interface 0 (ESSI0) (Continued)
Signal
Name
Type
State During
1
Signal Description
Reset Stop
Page 47
Enhanced Synchronous Serial Interface 1 (ESSI1)
Signals/Connections 2-17
2.9 Enhanced Synchronous Serial Interface 1 (ESSI1)
Table 2-13. Enhanced Synchronous Serial Interface 1 (ESSI1)
Signal
Name
Type
State During
1
Signal Description
Reset Stop
SC10
PD0
Input or
Output
Input Disconnected
internally
Serial Control 0—Functions in either Synchronous or
Asynchronous mode. For Asynchronous mode, this signal is
the receive clock I/O (Schmitt-trigger input). For Synchronous
mode, this signal is either for Transmitter 1 output or Serial I/O
Flag 0.
Port D 0—The default configuration following reset is GPIO.
For PD0, signal direction is controlled through the Port D
Direction Register (PRRD).
This signal is configured as SC10 or PD0 through the Port D
Control Register (PCRD).
This input is 5 V tolerant.
SC11
PD1
Input/Output
Input or
Output
Input Disconnected
internally
Serial Control 1—Functions in either Synchronous or
Asynchronous mode. For Asynchronous mode, this signal is
the receiver fram e sync I/O. Fo r Synchronou s mode, this signal
is either Transmitter 2 output or Serial I/O Flag 1.
Port D 1—The default configuration following reset is GPIO.
For PD1, signal direction is controlled through PRRD.
This signal is configured as SC11 or PD1 through PCRD.
This input is 5 V tolerant.
SC12
PD2
Input/Output
Input or
Output
Input Disconnected
internally
Serial Control Signal 2—The frame sync for both the
transmitter and receiver in Synchronous mode, and for the
transmitter only in Asynchronous mode. When configured as
an output, this signal is the internally generated frame sync
signal. When configured as an input, this signal receives an
external frame sync signal for the transmitter (and the receiver
in synchronous operation).
Port D 2—The default configuration following reset is GPIO.
For PD2, signal direction is controlled through PRRD.
This signal is configured as SC12 or PD2 through PCRD.
This input is 5 V tolerant.
Page 48
Enhanced Synchronous Serial Interface 1 (ESSI1)
2-18 DSP56303 User’s Manual
SCK1
PD3
Input/Output
Input or
Output
Input Disconnected
internally
Serial Clock—Provides the serial bit rate clock for the ESSI
interface for both the transmitter and receiver in Synchronous
modes, or the transmitter only in Asynchronous modes.
Although an external serial clock can be independent of and
asynchronous to the DSP system clock, it must exceed the
minimum clock cycle time of 6 T (that is, the system clock
frequency must be at least three tim es the ex tern al ESSI c lock
frequency). The ESSI needs at least three DSP phases inside
each half of the serial clock.
Port D 3—The default configuration following reset is GPIO.
For PD3, signal direction is controlled through PRRD.
This signal is configured as SCK1 or PD3 through PCRD.
This input is 5 V tolerant.
SRD1
PD4
Input
Input or
Output
Input Disconnected
internally
Serial Receive Data—Receives serial data and transfers the
data to the ESSI receive shift register. SRD0 is an input when
data is being received.
Port D 4—The default configuration following reset is GPIO.
For PD4, signal direction is controlled through PRRD.
This signal is configured as SRD1 or PD4 through PCRD.
This input is 5 V tolerant.
STD1
PD5
Output
Input or
Output
Input Disconnected
internally
Serial Transmit Data—Transm its d ata fro m the serial trans mit
shift register. STD1 is an output when data is being
transmitted.
Port C 5—The default configuration following reset is GPIO.
For PD5, signal direction is controlled through PRRD.
This signal is configured as STD1 or PD5 through PCRD.
This input is 5 V tolerant.
Note: 1. The Wait processing state does not affect the signal state.
Table 2-13. Enhanced Synchronous Serial Interface 1 (ESSI1) (Continued)
Signal
Name
Type
State During
1
Signal Description
Reset Stop
Page 49
Serial Communication Interface (SCI)
Signals/Connections 2-19
2.10 Serial Communication Interface (SCI)
The Serial Communication interface (SCI) provides a full duplex port for serial
communication with other DSPs, microprocessors, or peripherals such as modems.
Table 2-14. Serial Communication Interface (SCI)
Signal
Name
Type
State During
1
Signal Description
Reset Stop
RXD
PE0
Input
Input or
Output
Input Disconnected
internally
Serial Receive Data—Receives byte-oriented serial data and
transfers it to the SCI receive shift register.
Port E 0—The default configuratio n following re set is GPIO.
When configured as PE0, sig nal dire ction i s controll ed throu gh
the Port E Directions Register (PRRE).
This signal is configured as RXD or PE0 through the Port E
Control Register (PCRE).
This input is 5 V tolerant.
TXD
PE1
Output
Input or
Output
Input Disconnected
internally
Serial Transmit Data—Transmits data from SC I transmi t data
register.
Port E 1—The default configuratio n following re set is GPIO.
When configured as PE1, sig nal dire ction i s controll ed throu gh
the SCI PRRE.
This signal is configured as TXD or PE1 through PCRE.
This input is 5 V tolerant.
SCLK
PE2
Input/Output
Input or
Output
Input Disconnected
internally
Serial Clock—Provides the input or output clock used by the
transmitter and/or the receiver.
Port E 2—The default configuratio n following re set is GPIO.
For PE2, signal direction is controlled through the SCI PRRE.
This signal is configured as SCLK or PE2 through PCRE.
This input is 5 V tolerant.
Note: 1. The Wait processing state does not affect the signal state.
Page 50
Timers
2-20 DSP56303 User’s Manual
2.11 Timers
The DSP56303 has three identical and independent timers. Each can use internal or external
clocking, interrupt the DSP56303 after a specified number of events (clocks), or signal an
external device after counting a specific number of internal events.
Table 2-15. Triple Timer Signals
Signal
Name
Type
State During
1
Reset Stop Signal Description
TIO0 Input or
Output
Input Disconnected
internally
Timer 0 Schmitt-Trigger Input/Output—As an external
event counter or in Measurement mode, TIO0 is input. In
Watchdog, Timer, or Pulse Modulation mode, TIO0 is output.
The default mode after reset is GPIO input. This can be
changed to output or configured as a Timer Input/Output
through the Timer 0 Control/Status Register (TCSR0).
This input is 5 V tolerant.
TIO1 Input or
Output
Input Disconnected
internally
Timer 1 Schmitt-Trigger Input/Output—As an external
event counter or in Measurement mode, TIO1 is input. In
Watchdog, Timer, or Pulse Modulation mode, TIO1 is output.
The default mode after reset is GPIO input. This can be
changed to output or configured as a Timer Input/Output
through the Timer 1 Control/Status Register (TCSR1).
This input is 5 V tolerant.
TIO2 Input or
Output
Input Disconnected
internally
Timer 2 Schmitt-Trigger Input/Output—As an external
event counter or in Measurement mode, TIO2 is input. In
Watchdog, Timer, or Pulse Modulation mode, TIO2 is output.
The default mode after reset is GPIO input. This can be
changed to output or configured as a Timer Input/Output
through the Timer 2 Control/Status Register (TCSR2).
This input is 5 V tolerant.
Note: 1. The Wait processing state does not affect the signal state.
Page 51
JTAG/OnCE Interface
Signals/Connections 2-21
2.12 JTAG/OnCE Interface
Table 2-16. JTAG/OnCE Interface
Signal Name Type
State During
Reset
Signal Description
TCK Input Input Test Clock—A test clock signal for synchronizing JTAG test
logic.
This input is 5 V tolerant.
TDI Input Input Test Data Input—A test data serial signal for test instructions
and data. TDI is sam pled on th e ris ing e dge o f TC K and has an
internal pull-up resistor.
This input is 5 V tolerant.
TDO Output Tri-stated Test Data Output—A test data serial signal for test
instructions and data. TDO can be tri-stated. The signal is
actively driven in th e s hi ft-IR an d s hif t-D R co ntroller states and
changes on the falling edge of TCK.
This pin is 5 V tolerant.
TMS Input Input Test Mode Select—Sequences the test co ntroller’s state
machine, is sampled on the rising edge of TCK, and has an
internal pull-up resistor.
This input is 5 V tolerant.
TRST
Input Input Test Reset—As yn ch rono us ly initializes the test c ontroller, has
an internal pull-up resistor, and must be asserted after power
up.
This input is 5 V tolerant.
DE
Input/Output Input Debug Event—Provides a way to enter Debug mode from an
external command controller (as input) or to acknowledge that
the chip has entered Debug mode (as output). When asserted
as an input, DE
causes the DSP56300 core to finis h the current
instruction, save the instruction pipeline information, enter
Debug mode, and wait for commands from the debug serial
input line. When a debug request or a breakpoint condition
cause the chip to enter Debug mode DE is asserted as an
output for three clock cycles. DE
has an inter nal pull-up
resistor.
DE
is not a standard part of the JTAG Test Access Port (TAP)
Controller. It connects to the OnCE module to initiate Debug
mode directly or to provide a direct external indication that the
chip has entered the Debug mode. All other interface with the
OnCE module must occur through the JTAG port.
This input is 5 V tolerant.
Page 52
JTAG/OnCE Interface
2-22 DSP56303 User’s Manual
Page 53
Memory Configurat ion 3-1
Chapter 3
Memory Configuration
Like all members of the DSP56300 core family, the DSP56303 addresses three sets of
16 M × 24-bit memory internally: program, X data, and Y data. Each of these memory spaces
includes both on-chip and external memory (accessed through the external memory
interface). The DSP56303 is extremely flexible because it has several modes to allocate
on-chip memory between the program memory and the two data memory spaces. You can
also configure it to operate in a special sixteen-bit compatibility mode that allows the chip to
use DSP56000 object code without any change; this can result in higher performance of
existing code for applications that do not require a larger address space. This section provides
detailed information on each of these memory spaces.
3.1 Program Memory Space
Program memory space consists of the following:
■ Internal program RAM (4 K by default)
■ Instruction cache (optional, 1 K) formed from program RAM. When enabled, the
memory addresses used by the internal cache memory are switched to external
memory. The internal memory in this address range switches to cache-only mode and
is not available via direct addressing when cache is enabled. In systems using
Instruction Cache, always enable the cache (CE = 1) before loading code into internal
program memory; this prevents the condition in which code loaded into program
memory before cache is enabled “disappears” after cache is enabled.
■ Off-chip memory expansion (optional, as much as 64 K in 16-bit mode or 256 K in
24-bit mode using the 18 external address lines or 4 M using the external address lines
and the four address attribute lines). Refer to the DSP56300 Family Manual, especially
Chapter 9, External Memory Interface (Port A), for details on using the external
memory interface to access external program memory.
■ Bootstrap program ROM (192 × 24-bit)
Note: Program memory space at locations $FF00C0–$FFFFFF is reserved and should not
be accessed.
Page 54
Program Memory Space
3-2 DSP56303 User’s Manual
3.1.1 Internal Program Memory
The default on-chip program memory consists of a 24-bit-wide, high-speed, SRAM
occupying the lowest 4 K (default), 3 K, 2 K, or 1 K locations in program memory space,
depending on the settings of the OMR[MS] and (SR[CE]) bits. Section 4.3.2, Operating
Mode Register (OMR), on page 4-15 provides details on the MS bit. Section 4.3.1, Status
Register (SR), on page 4-9 provides details on the CE bit. The default on-chip program RAM
is organized in 16 banks with 256 locations each (4 K). Setting the MS bit switches four banks
of program memory to the X data memory and an additional four banks of program memory
to the Y data memory. Setting the CE bit switches four banks of internal program memory to
the Instruction Cache and reassigns its address to external program memory. The memory
addresses for the Instruction Cache vary depending on the setting of the MS and CE bits.
Section 3.6 provides a summary of the internal RAM configurations. Refer to the memory
maps for detailed information.
3.1.2 Memory Switch Modes—Prog ram Memory
Memory switch mode allows reallocation of portions of program RAM to X and Y data
RAM. OMR[7] is the memory switch (MS) bit that controls this function, as follows:
■ When the MS bit is cleared, program memory consists of the default 4 K × 24-bit
memory space described in the previous section. In this default mode, the lowest
external program memory location is $1000. If the CE bit is set, the program memory
consists of the lowest 3 K × 24-bits of memory space and the lowest external program
memory location is $0C00.
■ When the MS bit is set, the highest 2 K × 24-bit portion of the internal program
memory is switched to internal X and Y data memory. In this mode, the lowest
external program memory location is $800. If the CE bit is set and the MS bit is set, the
program memory consists of the lowest 1 K × 24-bits of memory space and the lowest
external program memory location is $400.
3.1.3 Instruction Cache
In program memory space, the location of the internal Instruction Cache (when enabled by the
CE bit) varies depending on the setting of the MS bit, as noted above. Refer to the memory
maps for detailed address information. When the instruction cache is enabled (that is, the
SR[CE] bit is set), 1 K program words switch to instruction cache and are not accessible via
addressing; the address range switches to external program memory.
Page 55
X Data Memory Space
Memory Configurat ion 3-3
3.1.4 Program Bootstrap ROM
The program memory space occupying locations $FF0000–$FF00BF includes the internal
bootstrap ROM. This ROM contains the 192-word DSP56303 bootstrap program.
3.2 X Data Memory Space
The X data memory space consists of the following:
■ Internal X data memory (2 K by default up to 3 K)
■ Internal I/O space (upper 128 locations)
■ Optional off-chip memory expansion (up to 64 K in 16-bit mode, or 256 K in 24-bit
mode using the 18 external address lines, or 4 M using the external address lines and
the four address attribute lines). Refer to the DSP56300 Family Manual, especially
Chapter 9, External Memory Interface (Port A), for details on using the external
memory interface to access external X data memory.
Note: The X memory space at $FF0000–$FFEFFF is reserved and should not be
accessed.
3.2.1 Internal X Data Memory
The default on-chip X data RAM is a 24-bit-wide, internal, static memory occupying the
lowest 2 K locations ($000–$7FF) in X memory space. The on-chip X data RAM is organized
into 8 banks with 256 locations each. Available X data memory space is increased by 1 K
through reallocation of program memory using the memory switch mode described in the next
section.
3.2.2 Memory Switch Modes—X Data Memory
Memory switch mode reallocates portions of program RAM to X and Y data memory. Bit 7 in
the OMR is the MS bit that controls this function, as follows:
■ When the MS bit is cleared, the X data memory consists of the default 2 K × 24-bit
memory space described in the previous section. In this default mode, the lowest
external X data memory location is $800.
■ When the MS bit is set, a portion of the higher locations of the internal program
memory is switched to X and Y data memory. The X data memory in this mode
consists of a 3 K × 24-bit memory space. In this mode, the lowest external X data
memory location is $C00.
Page 56
Y Data Memory Space
3-4 DSP56303 User’s Manual
3.2.3 Internal I/O Space—X Data Memory
One part of the on-chip peripheral registers and some of the DSP56303 core registers occupy
the top 128 locations of the X data memory ($FFFF80–$FFFFFF). This area is referred to as
the internal X I/O space and it can be accessed by MOVE, MOVEP instructions and by
bit-oriented instructions (BCHG, BCLR, BSET, BTST, BRCLR, BRSET, BSCLR, BSSET,
JCLR, JSET, JSCLR and JSSET). The contents of the internal X I/O memory space are listed
in Appendix A.
3.3 Y Data Memory Space
The Y data memory space consists of the following:
■ Internal Y data memory (2 K by default up to 3 K)
■ External I/O space (upper 128 locations)
■ Optional off-chip memory expansion (up to 64 K in 16-bit mode, or 256 K in 24-bit
mode using the 18 external address lines, or 4 M using the external address lines and
the four address attribute lines). Refer to the DSP56300 Family Manual, especially
Chapter 9, External Memory Interface (Port A), for details on using the external
memory interface to access external Y data memory.
Note: The Y memory space at $FF0000–$FFEFFF is reserved and should not be
accessed.
3.3.1 Internal Y Data Memory
The default on-chip Y data RAM is a 24-bit-wide, internal, static memory occupying the
lowest 2 K ($000–$7FF) of Y memory space. The on-chip Y data RAM is organized into 8
banks with 256 locations each. Available Y data memory space is increased by 1 K through
reallocation of program memory using the memory switch mode described in the next section.
3.3.2 Memory Switch Modes—Y Data Memory
Memory switch mode reallocates of portions of program RAM to X and Y data memory. Bit 7
in the OMR is the MS bit that controls this function, as follows:
■ When the MS bit is cleared, the Y data memory consists of the default 2 K × 24-bit
memory space described in the previous section. In this default mode, the lowest
external Y data memory location is $800.
■ When the MS bit is set, a portion of the higher locations of the internal program
memory is switched to X and Y data memory. The Y data memory in this mode
consists of a 3 K × 24-bit memory space. In this mode, the lowest external Y data
memory location is $C00.
Page 57
Dynamic Memory Configuration Switching
Memory Configurat ion 3-5
3.3.3 External I/O Space—Y Data Memory
The off-chip peripheral registers should be mapped into the top 128 locations of Y data
memory ($FFFF80–$FFFFFF in the 24-bit Address mode or $FF80–$FFFF in the 16-bit
Address mode) to take advantage of the Move Peripheral Data (MOVEP) instruction and the
bit-oriented instructions (BCHG, BCLR, BSET, BTST, BRCLR, BRSET, BSCLR, BSSET,
JCLR, JSET, JSCLR, and JSSET).
3.4 Dynamic Memory Configuration Switching
Do not change the OMR[MS] bit when the SR[CE] bit is set. The Instruction Cache occupies
the top 1 K of what is otherwise Program RAM, and to switch memory into or out of Program
RAM when the cache is enabled can cause conflicts. To change the MS bit when CE is set:
1. Clear CE.
2. Change MS.
3. Set CE.
Because an interrupt could cause the DSP to fetch instructions out of sequence and might
violate the switch condition, special care should be taken in relation to the interrupt vector
routines.
CAUTION
To ensure that dynamic switching is trouble-free, do not allow any
accesses (including instruction fetches) to or from the affected address
ranges in program and data memories during the switch cycle.
CAUTION
Pay special attention when executing a memory switch routine using the
OnCE port. Running the switch routine in trace mode, for example, can
cause the switch to complete after the MS/MSW bits change while the DSP
is in Debug mode. As a result, subsequent instructions may be fetched
according to the new memory configuration (after the switch) and thus
may execute improperly.
Page 58
Sixteen-Bit Compatibility Mode Configuration
3-6 DSP56303 User’s Manual
3.5 Sixteen-Bit Compatibility Mode Configuration
The sixteen-bit compatibility (SC) mode allows the DSP56303 to use DSP56000 object code
without change. The SC bit (Bit 13 in the SR) is used to switch from the default 24-bit mode
to this special 16-bit mode. SC is cleared by reset. You must set this bit to select the SC mode.
The address ranges described in the previous sections apply in the SC mode with regard to the
reallocation of X and Y data memory to program memory in MS mode, but the maximum
addressing ranges are limited to $FFFF, and all data and program code are 16 bits wide.
3.6 RAM Configuration Summary
The RAM configurations for the DSP56303 are listed in Table 3-1.
The actual memory locations for Program RAM and the Instruction Cache in the Program
memory space are determined by the MS and CE bits, and their addresses are given in Table
3-2.
Table 3-1. DSP56303 RAM Configurations
Bit Settings Memory Sizes (in K)
MS CE Program RAM X data RAM Y data RAM Cache
004220
013221
102330
111331
Table 3-2. DSP56303 RAM Address Ranges by Configuration
MS CE Program RAM Location Cache Location
00 $000–$FFF N/A
0 1 $000–$BFF $C00–$FFF (interna l location not ac cessible; ad dress range
assigned to external Program Memory)
1 0 $000–$7FF N/A
1 1 $000–$3FF $400–$7FF (internal location not accessible; addressed
assigned to external Program Memory)
Page 59
Memory Maps
Memory Configurat ion 3-7
3.7 Memory Maps
The following figures describe each of the memory space and RAM configurations defined by
the settings of the SC, MS, and CE bits. The figures show the configuration and the table
describes the bit settings, memory sizes, and memory locations.
Figure 3-1. Default Settings (0, 0, 0)
Internal
Reserved
Bootstrap ROM
External
Internal
Program RAM
4 K
$FFFFFF
$FFF0C0
$FF0000
$001000
$000000
Internal
Reserved
Internal I/O
External
Internal
X data RAM
2 K
External
$000800
Internal
Reserved
External I/O
External
Internal
Y data RAM
2 K
External
$FF0000
$000000
$FFF000
$FFFF80
Program X Data Y Data
Default
Bit Settings Memory Configuration
SC MS CE Program RAM X Data RAM Y Data RAM Cache
Addressable
Memory Size
000 4 K
$000–$FFF
2 K
$000–$7FF
2 K
$000–$7FF
None 16 M
$FFFFFF
$000800
$FF0000
$000000
$FFF000
$FFFF80
$FFFFFF
Page 60
Memory Maps
3-8 DSP56303 User’s Manual
Figure 3-2. Instruction Cache Enabled (0, 0, 1)
Internal
Reserved
Bootstrap ROM
External
Internal
Program RAM
3 K
$FFFFFF
$FFF0C0
$FF0000
$000000
Internal
Reserved
Internal I/O
External
Internal
X data RAM
2 K
External
$000800
Internal
Reserved
External I/O
External
Internal
Y data RAM
2 K
External
$FFF000
$FFFF80
Program X Data Y Data
$000C00
Bit Settings Memory Configuration
SC MS CE Program RAM X Data RAM Y Data RAM Cache
Addressable
Memory Size
001 3 K
$000–$BFF
2 K
$000–$7FF
2 K
$000–$7FF
1 K
internal not
accessible
16 M
$FFFFFF
$FF0000
$000000
$000800
$FFF000
$FFFF80
$FFFFFF
$FF0000
$000000
Page 61
Memory Maps
Memory Configurat ion 3-9
Figure 3-3. Switched Program RAM (0, 1, 0)
Internal
Reserved
Bootstrap ROM
Internal
Program RAM
2 K
$FFFFFF
$FFF0C0
$FF0000
$000000
Internal
Reserved
Internal I/O
External
Internal
X data RAM
3 K
External
$000C00
Internal
Reserved
External I/O
External
Internal
Y data RAM
3 K
External
$FFF000
$FFFF80
Program X Data Y Data
Bit Settings Memory Configuration
SC MS CE Program RAM X Data RAM Y Data RAM Cache
Addressable
Memory Size
010 2 K
$000–$7FF
3 K
$000–$BFF
3 K
$000–$BFF
None 16 M
External
$FFFFFF
$FF0000
$000000
$000C00
$FFF000
$FFFF80
$FFFFFF
$FF0000
$000000
$000800
Page 62
Memory Maps
3-10 DSP56303 User’s Manual
Figure 3-4. Switched Program RAM and Instruction Cache Enabled (0, 1, 1)
Internal
Reserved
Bootstrap ROM
External
Internal
RAM 1 K
$FFFFFF
$FFF0C0
$FF0000
$000000
Internal
Reserved
Internal I/O
External
Internal
X data RAM
3 K
External
$000C00
Internal
Reserved
External I/O
External
Internal
Y data RAM
3 K
External
$FFF000
$FFFF80
Program X Data Y Data
$000400
Bit Settings Memory Configuration
SC MS CE Program RAM X Data RAM Y Data RAM Cache
Addressable
Memory Size
011 1 K
$000–$3FF
3 K
$000–$BFF
3 K
$000–$BFF
1 K
internal not
accessible
16 M
Program
$FFFFFF
$FF0000
$000000
$000C00
$FFF000
$FFFF80
$FFFFFF
$FF0000
$000000
Page 63
Memory Maps
Memory Configurat ion 3-11
Figure 3-5. 16-bit Space with Default RAM (1, 0, 0)
External
Internal
Program RAM
4 K
$FFFF
$1000
$0000
Internal I/O
Internal
X data RAM
2 K
External
External I/O
Internal
Y data RAM
2 K
External
Program X Data Y Data
Bit Settings Memory Configuration
SC MS CE Program RAM X Data RAM Y Data RAM Cache
Addressable
Memory Size
100 4 K
$000–$FFF
2 K
$000–$7FF
2 K
$000–$7FF
None 64 K
$FFFF
$0000
$FF80
$0800
$FFFF
$0000
$FF80
$0800
Page 64
Memory Maps
3-12 DSP56303 User’s Manual
Figure 3-6. 16-bit Space with Instruction Cache Enabled (1, 0, 1)
External
Internal
Program RAM
3 K
$FFFF
$0000
Internal I/O
External
Internal
X data RAM
2 K
External I/O
External
Internal
Y data RAM
2 K
Program X Data Y Data
$0C00
$0800
Bit Settings Memory Configuration
SC MS CE Program RAM X Data RAM Y Data RAM Cache
Addressable
Memory Size
101 3 K
$000–$BFF
2 K
$000–$7FF
2 K
$000–$7FF
1 K
internal not
accessible
64 K
$FFFF
$0000
$FF80
$0800
$FFFF
$0000
$FF80
Page 65
Memory Maps
Memory Configurat ion 3-13
Figure 3-7. 16-bit Space with Switched Program RAM (1, 1, 0)
Internal
Program RAM
2 K
$FFFF
$0000
Internal I/O
Internal
X data RAM
3 K
External
External I/O
Internal
Y data RAM
3 K
External
$FFFF
$0000
Program X Data Y Data
$FF80
$0C00
$0800
Bit Settings Memory Configuration
SC MS CE Program RAM X Data RAM Y Data RAM Cache
Addressable
Memory Size
110 2 K
$000–$7FF
3 K
$000–$BFF
3 K
$000–$BFF
None 64 K
External
$FFFF
$0000
$FF80
$0C00
Page 66
Memory Maps
3-14 DSP56303 User’s Manual
Figure 3-8. 16-bit Space, Switched Program RAM, Instruction Cache Enabled
(1, 1, 1)
External
$FFFF
$0000
Internal I/O
Internal
X data RAM
3 K
External
$0C00
External I/O
Internal
Y data RAM
3 K
External
Program X Data Y Data
$0400
Bit Settings Memory Configuration
SC MS CE Program RAM X Data RAM Y Data RAM Cache
Addressable
Memory Size
111 1 K
$000–$3FF
3 K
$000–$BFF
3 K
$000–$BFF
1 K
internal not
accessible
64 K
Internal
RAM 1 K
Program
$FFFF
$0000
$FF80
$0C00
$FFFF
$0000
$FF80
Page 67
Core Configuration 4-1
Chapter 4
Core Configuration
This chapter presents DSP56300 core configuration details specific to the DSP56303,
including:
n Operating modes
n Bootstrap program
n Central Processor registers
— Status register (SR)
— Operating mode register (OMR)
n Interrupt Priority Registers (IPRC and IPRP)
n PLL control (PCTL) register
n Bus Interface Unit registers
— Bus Control Register (BCR)
— DRAM Control Register (DCR)
— Address Attribute Registers (AAR[3–0])
n DMA Control Registers 5–0 (DCR[5–0])
n Device identification register (IDR)
n JTAG identification register
n JTAG boundary scan register (BSR)
For information on specific registers or modules in the DSP56300 core, refer to the
DSP56300 Family Manual.
Page 68
Operating Modes
4-2 DSP56303 User’s Manual
4.1 Operating Modes
The DSP56303 begins operation by leaving the Reset state and going into one of eight
operating modes. As the DSP56303 exits the Reset state, it loads the values of
MODA, MODB,
MODC, and MODD into bits MA, MB, MC, and MD of the OMR. These bit settings determine
the chip’s operating mode, which in turn determines the bootstrap program option the chip
uses to start up. Software can also set the OMR[MA–MD] bits directly. A jump directly to the
bootstrap program entry point ($FF0000) after the OMR bits are set causes the DSP56303 to
execute the specified bootstrap program option (except modes 0 and 8). Table 4-1 shows the
DSP56303 bootstrap operation modes, the corresponding settings of the external operational
mode signal lines (the OMR[MA–MD] bits), and the reset vector address to which the
DSP56303 jumps once it leaves the Reset state.
Table 4-1. DSP56303 Operating Modes
Mode MODD MODC MODB MODA
Reset
Vector
Description
0 0 0 0 0 $C00000 Expanded mode
Bypasses the bootstrap ROM, and the DSP56303
starts fetching instructions beginning at address
$C00000. Memory accesses are performed using
SRAM memory access type with 31 wait states and
no address attributes selected (default). Address
$C00000 is reflected as address $00000 on Port A
signals A[0–17].
1 0 0 0 1 $FF0000 Bootstrap from byte-wide memory
The bootstrap program it loads a program RAM
segment from consecutive byte-wide P memory
locations, starting at P:$D00000 (bits 7-0). The
memory is selected by the Address Attribute AA1
and is accessed with 31 wait states. The EPROM
bootstrap code expects to read 3 bytes specifying
the number of program words, 3 b ytes s peci fying t he
address to start loadin g th e p rogra m w o rds an d th en
3 bytes for each program word to be loaded. The
number of words, the starting address and the
program words are read least significant byte first
followed by the mid and then by the most significant
byte. The program words are condensed into 24-bit
words and stored in contiguous PRAM memory
locations starting at the specified starting address.
After reading the pro gram wo rds , pro gra m execution
starts from the same address where loading started.
Page 69
Operating Modes
Core Configuration 4-3
2 0 0 1 0 $FF0000 Bootstrap through SCI
The DSP is configured to load the program RAM
from the SCI interface. The number of program
words to be loaded and the startin g ad dress mus t be
specified. The SCI b ootstrap c ode exp ects to r eceive
3 bytes specifying the number of program words, 3
bytes specifying the address to start loading the
program words and then 3 bytes for each program
word to be loaded. The n umber of wo rds, the st arting
address and the program words are received least
significant byte first followed by the mid and then by
the most significant byte. Afte r receivin g the program
words, program exec ution starts in the sam e address
where loading started. The SCI is programmed to
work in asynchronous mode with 8 data bits, 1 stop
bit and no parity. The clock source is external and
the clock frequency m us t be 16x th e ba ud ra te. After
each byte is received, it is echoed back through the
SCI transmitter.
3 0 0 1 1 $FF0000 Reserved
4 0 1 0 0 $FF0000 HI08 bootstrap in ISA/DSP563xx mode
The HI08 is configured to load the program RAM
from the Host Interface programmed to operate in
the ISA mode. The HOST ISA bootstrap code
expects to read a 24-bit word specifying the number
of program words, a 24-bit word specifying the
address to start loadin g th e p rogra m w o rds an d th en
a 24-bit word for each program word to be loaded.
The program words are stored in contiguous P RAM
memory locations starting at the specified starting
address. After reading the program words, program
execution starts from the same address where
loading started. The Host Interface bootstrap load
program may be stopped by setting the Host Flag 0
(HF0). This starts execution of the loaded program
from the specified starting address.
Table 4-1. DSP56303 Operating Modes (Continued)
Mode MODD MODC MODB MODA
Reset
Vector
Description
Page 70
Operating Modes
4-4 DSP56303 User’s Manual
5 0 1 0 1 $FF0000 HI08 bootstrap in HC11 nonmultiplexed mode
The bootstrap program sets the host interface to
interface with the Motorola HC11 microcontroller
through the HI08. The HOST HC11 bootstrap code
expects to read a 24-bit word specifying the number
of program words, a 24-bit word specifying the
address to start loadin g th e p rogra m w o rds an d th en
a 24-bit word for each program word to be loaded.
The program words are stored in contiguous P RAM
memory locations starting at the specified starting
address. After reading the program words, program
execution starts from the same address where
loading started. The Host Interface bootstrap load
program may be stopped by setting the Host Flag 0
(HF0). This starts execution of th e loaded program
from the specified starting address.
6 0 1 1 0 $FF0000 HI08 bootstrap in 8051 multiplexed bus mode
The bootstrap program sets the host interface to
interface with the Intel 8051 bus through the HI08.
The HI08 pin configuration is optimized for
connection to the Intel 8051 multiplexed bus, in
double-strobe pin configuration. The HOST 8051
bootstrap code expects acc esses tha t are byte wi de.
The HOST 8051 bootstrap code expects to read 3
bytes forming a 24 -bi t w o rd sp eci fy ing th e num be r o f
program words, 3 bytes forming a 24-bit word
specifying the address to start loading the program
words and then 3 bytes form ing 24-bit words fo r each
program word to be loaded. The program words are
stored in contiguous PRAM memory locations
starting at the specified starting address. A fter
reading the program words, pr ogram execution sta rts
from the same address where loading started. The
Host Interface bootstrap load program may be
stopped by setting the Ho st F lag 0 (H F0 ). Th is sta rts
execution of the loaded program from the specified
starting address. The base address of the HI08 in
multiplexed mode is $80 and is not modified by the
bootstrap code. All the address lines are enabled
and should be connected accordingly.
Table 4-1. DSP56303 Operating Modes (Continued)
Mode MODD MODC MODB MODA
Reset
Vector
Description
Page 71
Operating Modes
Core Configuration 4-5
7 0 1 1 1 $FF0000 HI08 bootstrap in MC68302 bus mode
The bootstrap program l oads the prog ram RAM from
the Host Interface programmed to o perate in the
MC68302 bus mode, in single-strobe pin
configuration. The HOST MC68302 bootstrap code
expects accesses that are byte wide. The HOST
MC68302 bootstrap code expects to read 3 bytes
forming a 24-bit word specifying the number of
program words, 3 bytes forming a 24-bit word
specifying the address to start loading the program
words and then 3 bytes form ing 24-bit words fo r each
program word to be loaded. The program words are
stored in contiguous PRAM memory locations
starting at the specified starting address. A fter
reading the program words, pr ogram execution starts
from the same address where loading started. The
Host Interface bootstrap load program may be
stopped by setting the Ho st F lag 0 (H F0 ). Th is sta rts
execution of the loaded program from the specified
starting address.
8 1 0 0 0 $008000 Expanded mode
Bypasses the bootstrap ROM, and the DSP56303
starts fetching instructions beginning at address
$008000. Memory accesses are performed using
SRAM memory access type with 31 wait states and
no address attributes selected.
9 1 0 0 1 $FF0000 Bootstrap from byte-wide memory
The bootstrap program it loads a program RAM
segment from consecutive byte-wide P memory
locations, starting at P:$D00000 (bits 7-0). The
memory is selected by the Address Attribute AA1
and is accessed with 31 wait states. The EPROM
bootstrap code expects to read 3 bytes specifying
the number of program words, 3 b ytes s peci fying t he
address to start loadin g th e p rogra m w o rds an d th en
3 bytes for each program word to be loaded. The
number of words, the starting address and the
program words are read least significant byte first
followed by the mid and then by the most significant
byte. The program words are condensed into 24-bit
words and stored in contiguous PRAM memory
locations starting at the specified starting address.
After reading the pro gram wo rds , pro gra m execution
starts from the same address where loading started.
Table 4-1. DSP56303 Operating Modes (Continued)
Mode MODD MODC MODB MODA
Reset
Vector
Description
Page 72
Operating Modes
4-6 DSP56303 User’s Manual
A 1 0 1 0 $FF0000 Bootstrap through SCI
The DSP is configured to load the program RAM
from the SCI interface. The number of program
words to be loaded and the startin g ad dress mus t be
specified. The SCI b ootstrap c ode exp ects to r eceive
3 bytes specifying the number of program words, 3
bytes specifying the address to start loading the
program words and then 3 bytes for each program
word to be loaded. The number of wo rds, the st arting
address and the program words are received least
significant byte first followed by the mid and then by
the most significant byte. Afte r receivin g the program
words, program exec ution starts in the sam e address
where loading started. The SCI is programmed to
work in asynchronous mode with 8 data bits, 1 stop
bit and no parity. The clock source is external and
the clock frequency m us t be 16x th e ba ud ra te. After
each byte is received, it is echoed back through the
SCI transmitter.
B 1 0 1 1 $FF0000 Reserved
C 1 1 0 0 $FF0000 HI08 bootstrap in ISA/DSP563xx mode
The HI08 is configured to load the program RAM
from the Host Interface programmed to operate in
the ISA mode. The HOST ISA bootstrap code
expects to read a 24-bit word specifying the number
of program words, a 24-bit word specifying the
address to start loadin g th e p rogra m w o rds an d th en
a 24-bit word for each program word to be loaded.
The program words are stored in contiguous P RAM
memory locations starting at the specified starting
address. After reading the program words, program
execution starts from the same address where
loading started. The Host Interface bootstrap load
program may be stopped by setting the Host Flag 0
(HF0). This starts execution of th e loaded program
from the specified starting address.
Table 4-1. DSP56303 Operating Modes (Continued)
Mode MODD MODC MODB MODA
Reset
Vector
Description
Page 73
Operating Modes
Core Configuration 4-7
D 1 1 0 1 $FF0000 HI08 bootstrap in HC11 nonmultiplexed mode
The bootstrap program sets the host interface to
interface with the Motorola HC11 microcontroller
through the HI08. The HOST HC11 bootstrap code
expects to read a 24-bit word specifying the number
of program words, a 24-bit word specifying the
address to start loadin g th e p rogra m w o rds an d th en
a 24-bit word for each program word to be loaded.
The program words are stored in contig uou s PRAM
memory locations starting at the specified starting
address. After reading the program words, program
execution starts from the same address where
loading started. The Host Interface bootstrap load
program may be stopped by setting the Host Flag 0
(HF0). This starts execution of the loaded program
from the specified starting address.
E 1 1 1 0 $FF0000 HI08 bootstrap in 8051 multiplexed bus mode
The bootstrap program sets the host interface to
interface with the Intel 8051 bus through the HI08.
The HI08 pin configuration is optimized for
connection to the Intel 8051 multiplexed bus, in
double-strobe pin configuration. The HOST 8051
bootstrap code expects acc esses tha t are byte wi de.
The HOST 8051 bootstrap code expects to read 3
bytes forming a 24-bit word specifying the number of
program words, 3 bytes forming a 24-bit word
specifying the address to start loading the program
words and then 3 bytes form ing 24-bit words fo r each
program word to be loaded. The program words are
stored in contiguous PRAM memory locations
starting at the specified starting address. A fter
reading the program words, pr ogram execution starts
from the same address where loading started. The
Host Interface bootstrap load program may be
stopped by setting the Ho st F lag 0 (H F0 ). Th is sta rts
execution of the loaded program from the specified
starting address. The base address of the HI08 in
multiplexed mode is 0x80 and is not modified by the
bootstrap code. All the address lines are enabled
and should be connected accordingly.
Table 4-1. DSP56303 Operating Modes (Continued)
Mode MODD MODC MODB MODA
Reset
Vector
Description
Page 74
Bootstrap Program
4-8 DSP56303 User’s Manual
4.2 Bootstrap Program
The bootstrap program is factory-programmed in an internal 192-word by 24-bit bootstrap
ROM located in program memory space at locations $FF0000–$FF00BF. The bootstrap
program can load any program RAM segment from an external byte-wide EPROM, the SCI,
or the host port. The bootstrap program code is listed in Appendix A.
Upon exit from the Reset state, the DSP56303 samples the
MODA–MODD signal lines and loads
their values into OMR[MA–MD]. The mode input signals (
MODA–MODD) and the resulting
MA, MB, MC, and MD bits determine which bootstrap mode the DSP56303 enters (see
Table 4-1).
Note: To stop the bootstrap in any HI08 bootstrap mode, set the Host Flag 0 (HF0). The
loaded user program begins executing from the specified starting address.
You can invoke the bootstrap program options (except modes 0 and 8) at any time by writing
the appropriate values to the MA, MB, MC, and MD bits in the OMR and jumping to the
bootstrap program entry point, $FF0000. Software can set the mode selection bits directly in
the OMR. Bootstrap modes 0 and 8 are the normal DSP56303 functioning modes. The other
bootstrap modes select different specific bootstrap loading source devices. Refer to Appendix
A for detailed information about the bootstrap program.
F 1 1 1 1 $FF0000 HI08 bootstrap in MC68302 bus mode
The bootstrap program l oads the prog ram RAM from
the Host Interface programmed to operate in the
MC68302 bus mode, in single-strobe pin
configuration. The HOST MC68302 bootstrap code
expects accesses that are byte wide. The HOST
MC68302 bootstrap code expects to read 3 bytes
forming a 24-bit word specifying the number of
program words, 3 bytes forming a 24-bit word
specifying the address to start loading the program
words and then 3 bytes form ing 24-bit words fo r each
program word to be loaded. The program words are
stored in contiguous PRAM memory locations
starting at the specified starting address. A fter
reading the program words, pr ogram execution sta rts
from the same address where loading started. The
Host Interface bootstrap load program may be
stopped by setting the Ho st F lag 0 (H F0 ). Th is sta rts
execution of the loaded program from the specified
starting address.
Table 4-1. DSP56303 Operating Modes (Continued)
Mode MODD MODC MODB MODA
Reset
Vector
Description
Page 75
Central Processor Unit (CPU) Registers
Core Configuration 4-9
In these modes, the bootstrap program expects the following data sequence when
downloading the user program through an external port:
1. Three bytes that specify the number of (24-bit) program words to load
2. Three bytes that specify the (24-bit) start address where the user program loads in the
DSP56303 program memory
3. The user program (three bytes for each 24-bit program word)
Note: The three bytes for each data sequence are loaded least significant byte first.
When the bootstrap program finishes loading the specified number of words, it jumps to the
specified starting address and executes the loaded program.
4.3 Central Processor Unit (CPU) Registers
There are two CPU registers that must be configured to initialize operation. The Status
Register (SR) selects various arithmetic processing protocols and contains several status
reporting flag bits. The Operating Mode Register (OMR) configures several system operating
modes and characteristics.
4.3.1 Status Register (SR)
The Status Register (SR) (Figure ) is a 24-bit register that indicates the current system state of
the processor and the results of previous arithmetic computations. The SR is pushed onto the
system stack when program looping is initialized or a JSR is performed, including long
interrupts. The SR consists of the following three special-purpose 8-bit control registers:
n Extended Mode Register (EMR) (SR[23–16]) and Mode Register (MR) (SR[15–8])
—These special-purpose registers define the current system state of the processor. The
bits in both registers are affected by hardware reset, exception processing, ENDDO
(end current DO loop) instructions, RTI (return from interrupt) instructions, and TRAP
instructions. In addition, the EMR bits are affected by instructions that specify SR as
their destination (for example, DO FOREVER instructions, BRKcc instructions, and
MOVEC). During hardware reset, all EMR bits are cleared. The MR register bits are
affected by DO instructions, and instructions that directly reference the MR (for
example, ANDI, ORI, or instructions, such as MOVEC, that specify SR as the
destination). During processor reset, the interrupt mask bits are set and all other bits are
cleared.
n Condition Code Register (CCR) (SR[7–0])—Defines the results of previous arithmetic
computations. The CCR bits are affected by Data Arithmetic Logic Unit (Data ALU)
operations, parallel move operations, instructions that directly reference the CCR (for
example, ORI and ANDI), and instructions that specify SR as a destination (for
Page 76
Central Processor Unit (CPU) Registers
4-10 DSP56303 User’s Manual
example, MOVEC). Parallel move operations affect only the S and L bits of the CCR.
During processor reset, all CCR bits are cleared.
n The definition of the three 8-bit registers within the SR is primarily for the purpose of
compatibility with other Motorola DSPs. Bit definitions in the following paragraphs
identify the bits within the SR and not within the subregister.
Extended Mode Register (EMR) Mode Register (MR) Condition Code Register (CCR)
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CP[1–0] RM SM CE
SA FV LF DM SC S[1–0] I[1–0] S L E U N Z V C
Reset:
110000000000001100000000
Reserved bit. Read as zero; write to zero for future compatibility
Figure 4-1. Status Register (SR)
Table 4-2. Status Register Bit Definitions
Bit Number Bit Name Re set Value Description
23–22 CP[1–0] 11
Core Priority
Under control of the CDP[1–0] bits in the OMR, the CP bits specify the
priority of core accesses to external memory. These bits are compared
against the priority bits of the active DMA channel. If the core priority is
greater than the DMA priority, the DMA waits for a free time slot on the
external bus. If t he co re prio rity i s le ss th an the DMA priority, the core waits
for a free time slot on the external bus. If the core priority equals the DMA
priority, the core and DMA access the external bus in a round robin pattern
(for example, ... P, X, Y, DMA, P, X, Y, ...).
Priority
Mode
Core
Priority
DMA
Priority
OMR
(CDP[1-0])
SR (CP[1–0])
Dynamic
0
(Lowest)
Determined
by DCRn
(DPR[1–0])
for active
DMA
channel
00 00
10001
20010
3
(Highest)
00 11
Static
core < DMA 01 xx
core = DMA 10 xx
core > DMA 11 xx
21 RM 0 Rounding Mode
Selects the type of rounding performed by the Data ALU during arithmetic
operations. If RM is cleared, convergent rounding is selected. If RM is set,
two’s-complement rounding is selected.
20 SM 0 Arithmetic Saturation Mode
Selects automatic saturation on 48 bits for the results going to the
accumulator. This saturation is performed by a special circuit inside the
MAC unit. The purpose of this bit is to provide an Arithmetic Saturation
mode for algorithms that do not recognize or cannot take advantage of the
extension accumulator.
Page 77
Central Processor Unit (CPU) Registers
Core Configuration 4-11
19 CE 0 Cache Enable
Enables/disables the instruction cache controller. If CE is set, the cache is
enabled, and instructions are cached into and fetched from the internal
Program RAM. If CE is cleared, the cache is disabled and the DSP56300
core fetches instructions from external or internal program memory,
according to the memory sp ace tab le of th e specifi c DSP5630 0 core-b ased
device.
NOTE: To ensure proper operation, do not clear Cache Enable mode while
Burst mode is enabled (OMR[BE] is set).
18
0 Reserved. Write to zero for future compatibility.
17 SA 0 Sixteen-Bit Arithmetic Mode
Affects data width fu nct ion ali ty, en ab lin g t he Six teen -bi t Ari thm eti c mod e of
operation. When SA is set, th e core us es 16-b it opera tions instea d of 24-b it
operations. In this mode, 16-bit data is right-aligned in the 24-bit memory
locations, registers, and 24-b it regist er portion s. Shiftin g, limiting , rounding ,
arithmetic instructions, and moves are performed accordingly. For details
on Sixteen-Bit Arithmetic mode, consult the
DSP56300 Family Manual
.
16 FV 0 DO FOREVER Flag
Set when a DO FOREVER loop executes. The FV flag, like the LF flag, is
restored from the stack when a DO FOREVER loop terminates. Stacking
and restoring the FV flag when initiating and exiting a DO FOREVER loop,
respectively, allow program loops to be nested. When returning from the
long interrupt with an RTI instruction, the system stack is pulled and the
value of the FV bit is restored.
15 LF 0 Do Loop Flag
When a program loop is in progre ss, enables th e detect ion of the end of the
loop. The LF is restored from stack when a program loop terminates.
Stacking and restoring the LF when initiating and exiting a program loop,
respectively, allow program loops to be nested. When returning from the
long interrupt with an RTI instruction, the System Stack is pulled and the LF
bit value is restored.
Table 4-2. Status Register Bit Definitions (Continued)
Bit Number Bit Name Re set Value Description
Page 78
Central Processor Unit (CPU) Registers
4-12 DSP56303 User’s Manual
14 DM 0 Double-Precision Multiply Mode
Enables four multiply/MAC operations to implement a double-precision
algorithm that multiplies two 48-bit operands with a 96-bit result. Clearing
the DM bit disables the mode.
NOTE: The Double-Precisi on Multipl y mode is suppo rted to maintai n object
code compatibility with devices in the DSP56000 family. For a more
efficient way of executing double precision multiply, refer to the chapter on
the Data Arithmetic Logic Unit in the
DSP56300 Family Manual
.
In Double-Precision Multiply mode, the behavior of the four specific
operations listed in the double-precision algorithm is modified. Therefore,
do not use these operations (with those specific register combinations) in
Double-Precision Multiply mode for any purpose other than the double
precision multiply algorithm. All other Data ALU operations (or the four
listed operations, but with other register combinations) can be used.
The double-precision multiply algorithm uses the Y0 Register at all stages.
Therefore, do not change Y0 when running the double-precision multiply
algorithm. If the Data ALU must be used in an interrupt service routine, Y0
should be saved with other Data ALU registers to be used and restored
before the interrupt routine terminates.
13 SC 0 Sixteen-Bit Compatibility Mode
Affects addressing functionality, enabling full compatibility with object code
written for the DSP56000 family. When SC is set, MOVE operatio ns to/from
any of the following PCU registers clear the eight MSBs of the destination:
LA, LC, SP, SSL, SSH, EP, SZ, VBA and SC. If the source is either the SR
or OMR, then the eight MSBs of the destination are also cleared. If the
destination is either the SR or OMR, then the eight MSBs of the destination
are left unchanged. To chang e the value of one of the eight MSBs of th e SR
or OMR, clear SC.
SC also affects the contents of the Loop Counter Register. If SC is cleared
(normal operation), then a lo op cou nt value of z ero ca uses th e loop body to
be skipped, and a loop co unt value of $FFFFFF cause s the lo op to ex ecute
the maximum number of 2
24
– 1 times. If the SC bit is set, a loop count
value of zero causes the loop to execute 2
16
times, and a loop count value
of $FFFFFF causes the loop to execute 2
16
– 1 times.
NOTE: Due to pipelinin g, a ch ange in t he SC bit tak es effect only afte r three
instruction cycles. Insert three NOP instructions after the instruction that
changes the value of this bit to ensure proper o peration.
12
0 Reserved. Write to 0 for future compatibility.
Table 4-2. Status Register Bit Definitions (Continued)
Bit Number Bit Name Re set Value Description
Page 79
Central Processor Unit (CPU) Registers
Core Configuration 4-13
11–10 S[1–0] 0 Scaling Mode
Specify the scaling to be performed in the Data ALU shifter/limiter and the
rounding position in the Data ALU MAC unit. The Shifter/limiter Scaling
mode affects data read from the A or B accumulator registers out to the
X-data bus (XDB) and Y-data bus (YDB). Different scaling modes can be
used with the same program code to allow dynamic scaling. One
application of dynamic scaling is to facilitate block floating-point arithmetic.
The scaling mode also affects the MAC rounding position to maintain
proper rounding when different portions of the accumulator registers are
read out to the XDB and YDB. Scaling mode bits are cleared at the start of
a long Interrupt Service Routine and during a hardware reset.
S1 S0
Scaling
Mode
Rounding Bit SEquation
0 0 No scaling 23 S = (A46 XOR A45)
OR (B46 XOR B45)
OR S (previous)
0 1 Scale down 24 S = (A47 XOR A46)
OR (B47 XOR B46)
OR S (previous)
1 0 Scale up 22 S = (A45 XOR A44)
OR (B45 XOR B44)
OR S (previous)
1 1 Reserved — S undefined
9–8 I[1–0] 11 Interrupt Mask
Reflect the current Interrupt Priority Level (IPL) of the processor and
indicate the IPL needed for an interrupt source to interrupt the processor.
The current IPL of the processor can be changed under software control.
The interrupt mask bits are set during hardware reset, but no t during
software reset.
Priority I1 I0
Exceptions
Permitted
Exceptions Masked
Lowest
00
IPL 0, 1, 2, 3 None
01
IPL 1, 2, 3 IPL 0
10
IPL 2, 3 IPL 0, 1
Highest
11
IPL 3 IPL 0, 1, 2
7S0Scaling
Set when a result moves from a ccumulator A or B to the XDB or YDB buses
(during an accumulator to memory or accumulator to register move) and
remains set until explicitly cleared; that is, the S bit is a
sticky bit
. The
logical equations of this bi t are depende nt on the Scaling mo de. The scaling
bit is set if the absolute value in the accu mulator, befor e scaling, is > 0. 25 or
< 0.75.
Table 4-2. Status Register Bit Definitions (Continued)
Bit Number Bit Name Re set Value Description
Page 80
Central Processor Unit (CPU) Registers
4-14 DSP56303 User’s Manual
6L0Limit
Set if the overflow bit is set or if the data shifter/limiter circuits perform a
limiting operation. In Arithmetic Saturation mode, the L bit is also set when
an arithmetic saturation occurs in the Data ALU result; otherwise, it is not
affected. The L bit is cleared only by a processor reset or by an instruction
that specifically clears it (that is, a
sticky bit
); this allows the L bit to be us ed
as a latching overflow bit. The L bit is affected by data movement
operations that read the A or B accumulator registers.
5E1Extension
Cleared if all the b its of the integ er porti on of the 56 -bit resul t ar e all one s or
all zeros; otherwise, this bit is set. The Scaling mode defines the integer
portion. If the E bit is cleared , then the l ow-order f raction po rtion conta ins all
the significant bits; the high-order integer portion is sign extension. In this
case, the accumulator extension register can be ignored. If the E bit is set, it
indicates that the accumulator extension register is in use.
S1 S0 Scaling Mode Integer Portion
0 0 No scaling Bits 55–47
0 1 Scale down Bits 55–48
1 0 Scale up Bits 5–46
1 1 Reserved Undefined
4U0Unnormalized
Set if the two MSBs of the Most Significant Portion (MSP) of the result are
identical; otherwise, this bit is cleared. The MSP portion of the A or B
accumulators is defined by the Scaling mode.
S1 S0 Scaling Mode Integer Portion
0 0 No scaling
U = (Bit 47 XOR Bit 46)
0 1 Scale down
U = (Bit 48 XOR Bit 47)
1 0 Scale up
U = (Bit 46 XOR Bit 45)
11 Reserved
U undefined
3N0Negative
Set if the MSB of the result is set; otherwise, this bit is cleared.
2Z0Zero
Set if the result equals zero; otherwise, this bit is cleared.
1V0Overflow
Set if an arithmetic overflow occurs in the 56-bit result; otherwise, this bit is
cleared. V indicates that the result cannot be represented in the
accumulator register (that is, the register overflowed). In Arithmetic
Saturation mode, an arithmetic overflow occurs if the Data ALU result is not
representable in the accumulator without the extension part (that is, 48-bit
accumulator or the 32-bit accumulator in Arithmetic Sixteen-bit mode).
0C0Carry
Set if a carry is generated b y th e M SB resul t ing from an addition operation.
This bit is also set if a borrow is generated in a subtraction operation;
otherwise, this bit is cleared . The ca rry or borro w is gen erated from Bi t 55 of
the result. The C bit is also affected by bit manipulation, rotate, and shift
instructions.
Table 4-2. Status Register Bit Definitions (Continued)
Bit Number Bit Name Re set Value Description
Page 81
Central Processor Unit (CPU) Registers
Core Configuration 4-15
4.3.2 Operating Mode Register (OMR)
The OMR is a read/write register divided into three byte-sized units. The lowest two bytes
(EOM and COM) control the chip’s operating mode. The high byte (SCS) controls and
monitors the stack extension. The OMR control bits are shown in Figure 4-2.
The Enhanced Operating Mode (EOM) and Chip Operating Mode (COM) bytes are affected
only by processor reset and by instructions directly referencing the OMR (that is, ANDI, ORI,
and other instructions, such as MOVEC, that specify OMR as a destination). The Stack
Control/Status (SCS) byte is referenced implicitly by some instructions, such as DO, JSR, and
RTI, or directly by the MOVEC instruction. During processor reset, the chip operating mode
bits (MD, MC, MB, and MA) are loaded from the external mode select pins MODD, MODC,
MODB, and MODA respectively. Table 4-3 defines the DSP56303 OMR bits.
Stack Control/Status (SCS) Extended Operating Mode (EOM) Chip Operating Mode (COM)
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PEN MSW[1–0] SEN WRP EOV EUN XYS ATE APD ABE BRT TAS BE CDP[1–0] M S SD EBD MD MC MB MA
Reset:
00000000000000110000****
*
After reset, these bits reflect the corresponding value of the mode input (that is, MODD, MODC, MODB, or MODA,
respectively).
Reserved bit. Read as zero; write to zero for future compatibility
Figure 4-2. Operating Mode Register (OMR)
Table 4-3. Operating Mode Register (OMR) Bit Definitions
Bit Number Bit Name Reset Value Description
23–21
0 Reserved. Write to 0 for future compatibility.
20 SEN 0 Stack Extension Enable
Enables/disable s the stack extens ion in data memory. If the SEN bit is set,
the extension i s enab led. Hardware reset clears thi s bit, so the default out
of reset is a disabled stack extension.
19 WRP 0 Stack Extension Wrap Flag
Set when copying from the on-chip hardware stack (System Stack
Register file) t o th e s tac k e xt ens ion memory begins. You c an us e t his fl ag
during the debugging phase of the software development to evaluate and
increase the speed of software-implemented algorithms. The WRP flag is
a
sticky bit
(that is, cleared only by hardware r eset or by an explicit
MOVEC operation to the OMR).
Page 82
Central Processor Unit (CPU) Registers
4-16 DSP56303 User’s Manual
18 EOV 0 Stack Extension Overflow Flag
Set when a stack overflow occurs in Stack Extended mode. Extended
stack overflow is rec ognized wh en a push opera tion is req uested whi le SP
= SZ (Stack Size register), and the Extend ed mode is enabled by the SEN
bit. The EOV flag is a
sticky bit
(that is, cleared only by hardware reset or
by an explicit MOVEC operation to the OMR). The transition of the EOV
flag from zero to one c auses a Priority Lev el 3 (Non-mask able) s tack err or
exception.
17 EUN 0 Stack Extension Underflow Flag
Set when a stack underflow occurs in Extended Stack mode. Extended
stack underflow is rec og nized w hen a pu ll ope rati on i s re que st ed, SP = 0,
and the SEN bit enables Extend ed mode. The EUN flag is a
sticky bit
(that
is, cleared only by hardware reset o r by an explic it MOVEC operation to
the OMR). Transition of the EUN flag from zero to one causes a Priority
Level 3 (Non-maskable) stack error exception.
NOTE: While the chip is in Extended Stack mode, the UF bit in the SP
acts like a normal counte r bit.
16 XYS 0 Stack Extension XY Select
Determines whether the stack extension is mapped onto X or Y memory
space. If the bit is clear, then the stack extension is mapped onto the X
memory space. If the XYS bit is set, the stack extension is mapped to the
Y memory space.
15 ATE 0 Address Trace Enable
When set, the Address Trace Enable (ATE) bit enables Address Trace
mode. The Address Trace mode is a debugging tool that reflects internal
memory accesses at the external bus address.
14 APD 0 Address Attribute Priority Disable
Disables the priority assigned to the Address Attribute signals (AA[0–3]).
When APD = 0 (default setting), the four Address Attribute signals each
have a certain priority: AA3 has the highest priority, AA0 has the lowest
priority. Therefore, only one AA signal can be active at one time. This
allows continuous partitioning of external memory; however, certain
functions, such as using the AA signals as additional address lines,
require the use of additional interface hardware. When APD is set, the
priority mechanism is disabled, allowing more than one AA signal to be
active simultaneously. Therefore, the AA signals can be used as
additional address lines without the need for additional interface
hardware. For details on the Address Attribute Registers, see Section
4.6.3,
Address Attribute Registers (AAR[0–3])
, on page 4-30.
13 ABE 0 Asynchronous Bus Arbitration Enable
Eliminates the setup and hold time requirements for BB and BG, and
substitutes a req uired non-over lap interval b etween the deas sertion of one
BG input to a DSP56300 family device and the assertion of a second BG
input to a second DSP56300 family device on the same bus. When the
ABE bit is set, the BG and BB inputs are synchronized. This
synchronization causes a delay between a change in BG
or BB until this
change is actually accepted by the receiving device.
Table 4-3. Operating Mode Register (OMR) Bit Definitions (Continued)
Bit Number Bit Name Reset Value Description
Page 83
Central Processor Unit (CPU) Registers
Core Configuration 4-17
12 BRT 0 Bus Release Timing
Selects between fast or slow bus release. If BRT is cleared, a Fast Bus
Release mode is selected (that is, no additional cycles are added to the
access and BB
is not guaranteed to be the last Port A pin that is tri-stated
at the end of the access). If BRT is set, a Slow Bus Release mode is
selected (that is, an additional cycle is add ed t o the access, and BB
is the
last Port A pin that is tri-stated at the end of the access).
11 TAS 0 TA
Synchronize Select
Selects the synchronization method for the input Port A pin—TA
(Transfer
Acknowledge). If TAS is cle are d, you a r e res ponsi bl e for a ss erti ng t he TA
pin in synchrony with the chip clock, as described in the technical data
sheet. If TAS is set, the TA input pin is synchronized inside the chip, thus
eliminating the need for an off-chip synchronizer. Note that the TAS bit
has no effect when the TA pin is deasserted: you are responsible for
deasserting the TA
pin in synchrony with the chip clock, regardless of the
value of TAS.
10 BE 0 Cache Burst Mode Enable
Enables/disables Burst mode in the memory expansion port during an
instruction cache miss. If the bit is cleared, Burst mode is disabled and
only one program word is fetched from the external memory when an
instruction cache miss condition is detected. If the bit is set, Burst mode is
enabled, and up to four program words are fetched from the external
memory when an instruction cache miss is detected.
9–8 CDP[1–0] 11 Core-DMA Priority
Specify the priority of core and DMA accesses to the external bus.
00 Determined by comparing status register CP[1–0] to the
active DMA channel priority
01 DMA accesses have higher priority than core accesses
10 DMA accesses have the same priority as the core accesses
11 DMA accesses have lower priority than the core accesses
7MS0Memory Switch Mode
Allows some internal data memory (X, Y, or both) to become part of the
chip internal Program RA M.
Notes:
1. Program data placed in the Program RAM/Instruction Cache area
changes its placement after the OMR[MS] bit is set (that is, the
Instruction Cache always uses the lowest internal Program RAM
addresses).
2. To ensure proper operation, place six NOP instructions after the
instruction that chang es the MS bit.
3. To ensure proper operation, do not set the MS bit while the
Instruction Cache is enabled (SR[CE] bit is set).
Table 4-3. Operating Mode Register (OMR) Bit Definitions (Continued)
Bit Number Bit Name Reset Value Description
Page 84
Configuring Interrupts
4-18 DSP56303 User’s Manual
4.4 Configuring Interrupts
DSP56303 interrupt handling, like that for all DSP56300 family members, is optimized for
DSP applications. Refer to the sections describing interrupts in Chapter 2, Core Architecture
Overview, in the DSP56300 Family Manual. Two registers are used to configure the interrupt
characteristics:
n Interrupt Priority Register-Core (IPRC)—Programmed to configure the priority levels
for the core DMA interrupts and the external interrupt lines as well as the interrupt line
trigger modes
n Interrupt Priority Register-Peripherals (IPRP)—Programmed to configure the priority
levels for the interrupts used with the on-chip peripheral devices
The interrupt table resides in the 256 locations of program memory to which the PCU vector
base address (VBA) register points. These locations store the starting instructions of the
interrupt handler for each specified interrupt. The memory is programmed by the bootstrap
program at startup.
6SD0Stop Delay Mode
Determines the length of the delay invoked when the core exits the Stop
state. The STOP instruction suspends core processing indefinitely until a
defined event occurs to restart it. If SD is cleared, a 128K clock cycle
delay is invoked before a STOP instruction cycle continues. However, if
SD is set, the delay before the instruction cycle continues is 16 clock
cycles. The long delay allows a clock stabilization period for the internal
clock to begin oscillating and to stabilize. When a stable external clock is
used, the shorter delay allows faster start-up of the DSP56300 core.
5
0 Reserved. Write to zero for future compatibility.
4 EBD 0 External Bus Disable
Disables the external bus controller to reduce power consumption when
external memories are not used. When EBD is set, the external bus
controller is disabled and external memory cannot be accessed. When
EBD is cleared, the ex ternal bus control ler is enab led an d exte rnal a cces s
can be performed. Hardware reset clears the EBD bit.
3–0 MD–MA * Chip Operating Mode
Indicate the operating mode of the DSP56300 core. On hardware reset,
these bits are loaded from the external mode select pins, MODD, MODC,
MODB, and MODA, respectively. After the DSP56300 core leaves the
Reset state, MD–MA can be changed under program control.
* The MD–MA bits reflect the corresponding value of the mode input (that is, MODD–MODA), respectively.
Table 4-3. Operating Mode Register (OMR) Bit Definitions (Continued)
Bit Number Bit Name Reset Value Description
Page 85
Configuring Interrupts
Core Configuration 4-19
4.4.1 Interrupt Priority Registers (IPRC and IPRP)
There are two interrupt priority registers in the DSP56303. The IPRC (Figure 4-3) is
dedicated to DSP56300 core interrupt sources, and IPRP (Figure 4-4) is dedicated to
DSP56303 peripheral interrupt sources.
Figure 4-4. Interrupt Priority Register-Peripherals (IPRP) (X:$FFFFFE)
Figure 4-3. Interrupt Priority Register-Core (IPRC) (X:$FFFFFF)
IAL0IAL1IAL2IBL0IBL1IBL2ICL0ICL1ICL2
01234567
8
91011
IRQA IPL
IRQA
mode
IRQB
IPL
IRQB
mode
IRQC
IPL
IRQC
mode
IRQD IPL
D0L0D0L1D1L0D1L1
23
22
21 20 19 18 17 16 15 14 13 12
DMA0 IPL
DMA1 IPL
D2L0D2L1D3L0D3L1D4L0D4L1D5L0D5L1
DMA2 IPL
DMA3 IPL
DMA4 IPL
DMA5 IPL
IDL2 IDL1 IDL0
IRQD
mode
HPL0HPL1S0L0S0L1S1L0S1L1
23
22
21 20 19 18 17 16 15 14 13 12
01234567
8
91011
HI08 IPL
ESSI0 IPL
ESSI1 IPL
SCI IPL
TRIPLE TIMER IPL
T0L0
T0L1
SCL0SCL1
reserved
reserved
Reserved bit; read as zero; should be written with zero for future compatibility
Page 86
Configuring Interrupts
4-20 DSP56303 User’s Manual
The DSP56303 has a four-level interrupt priority structure. Each interrupt has two interrupt
priority level bits (IPL[1–0]) that determine its interrupt priority level. Level 0 is the lowest
priority; Level 3 is the highest-level priority and is non-maskable. Table 4-4 defines the IPL
bits.
The IPRC also selects the trigger mode of the external interrupts (
IRQA–IRQD). If the value of
the IxL2 bit is 0, the interrupt mode is level-triggered. If the value is 1, the interrupt mode is
negative-edge-triggered.
4.4.2 Interrupt Table Memory Map
Each interrupt is allocated two instructions in the interrupt table, resulting in 128 table entries
for interrupt handling. Table 4-5 shows the table entry address for each interrupt source. The
DSP56303 initialization program loads the table entry for each interrupt serviced with two
interrupt servicing instructions. In the DSP56303, only some of the 128 vector addresses are
used for specific interrupt sources. The remaining interrupt vectors are reserved and can be
used for host
NMI (IPL = 3) or for host command interrupt (IPL = 2). Unused interrupt vector
locations can be used for program or data storage.
Table 4-4. In terrupt Priori ty Level Bits
IPL bits
Interrupts Enabled Interrupts Masked Interrupt Priority Level
xxL1 xxL0
00 No —0
0 1 Yes 0 1
10 Yes 0, 1 2
1 1 Yes 0, 1, 2 3
Table 4-5. Interrupt Sources
Interrupt
Starting Address
Interrupt
Priority Level
Range
Interrupt Source
VBA:$00 3 Hardware RESET
VBA:$02 3 Stack error
VBA:$04 3 Illegal instruction
VBA:$06 3 Debug request interrupt
VBA:$08 3 Trap
VBA:$0A 3 Nonmaskable interrupt (NMI)
VBA:$0C 3 Reserved
Page 87
Configuring Interrupts
Core Configuration 4-21
VBA:$0E 3 Reserved
VBA:$10 0–2 IRQA
VBA:$12 0–2 IRQB
VBA:$14 0–2 IRQC
VBA:$16 0–2 IRQD
VBA:$18 0–2 DMA channel 0
VBA:$1A 0–2 DMA channel 1
VBA:$1C 0–2 DMA channel 2
VBA:$1E 0–2 DMA channel 3
VBA:$20 0–2 DMA channel 4
VBA:$22 0–2 DMA channel 5
VBA:$24 0–2 TIMER 0 compare
VBA:$26 0–2 TIMER 0 overflow
VBA:$28 0–2 TIMER 1 compare
VBA:$2A 0–2 TIMER 1 overflow
VBA:$2C 0–2 TIMER 2 compare
VBA:$2E 0–2 TIMER 2 overflow
VBA:$30 0–2 ESSI0 receive data
VBA:$32 0–2 ESSI0 receive data with exception status
VBA:$34 0–2 ESSI0 receive last slot
VBA:$36 0–2 ESSI0 transmit data
VBA:$38 0–2 ESSI0 transmit data with exception status
VBA:$3A 0–2 ESSI0 transmit last slot
VBA:$3C 0–2 Reserved
VBA:$3E 0–2 Reserved
VBA:$40 0–2 ESSI1 receive data
VBA:$42 0–2 ESSI1 receive data with exception status
VBA:$44 0–2 ESSI1 receive last slot
VBA:$46 0–2 ESSI1 transmit data
VBA:$48 0–2 ESSI1 transmit data with exception status
VBA:$4A 0–2 ESSI1 transmit last slot
VBA:$4C 0–2 Reserved
VBA:$4E 0–2 Reserved
Table 4-5. Interrupt Sources (Continued)
Interrupt
Starting Address
Interrupt
Priority Level
Range
Interrupt Source
Page 88
Configuring Interrupts
4-22 DSP56303 User’s Manual
4.4.3 Processing Interrupt Source Priorities Within an IPL
If more than one interrupt request is pending when an instruction executes, the interrupt
source with the highest IPL is serviced first. When several interrupt requests with the same
IPL are pending, another fixed-priority structure within that IPL determines which interrupt
source is serviced first. Table 4-6 shows this fixed-priority list of interrupt sources within an
IPL, from highest to lowest at each level
The interrupt mask bits in the Status Register
(I[1–0]) can be programmed to ignore low priority-level interrupt requests.
VBA:$50 0–2 SCI receive data
VBA:$52 0–2 SCI receive data with exception status
VBA:$54 0–2 SCI transmit data
VBA:$56 0–2 SCI idle line
VBA:$58 0–2 SCI timer
VBA:$5A 0–2 Reserved
VBA:$5C 0–2 Reserved
VBA:$5E 0–2 Reserved
VBA:$60 0–2 Host receive data full
VBA:$62 0–2 Host transmit data empty
VBA:$64 0–2 Host command (default)
VBA:$66 0–2 Reserved
:::
VBA:$FE 0–2 Reserved
Table 4-6. Interrupt Source Priorities Within an IPL
Priority Interrupt Source
Level 3 (nonmaskable)
Highest Hardware RESET
Stack error
Illegal instruction
Debug request interrupt
Trap
Lowest Nonmaskable interrupt
Table 4-5. Interrupt Sources (Continued)
Interrupt
Starting Address
Interrupt
Priority Level
Range
Interrupt Source
Page 89
Configuring Interrupts
Core Configuration 4-23
Levels 0, 1, 2 (maskable)
Highest IRQA (external interrupt)
IRQB
(external interrupt)
IRQC
(external interrupt)
IRQD (external interrupt)
DMA channel 0 interrupt
DMA channel 1 interrupt
DMA channel 2 interrupt
DMA channel 3 interrupt
DMA channel 4 interrupt
DMA channel 5 interrupt
Host command interrupt
Host transmit data empty
Host receive data full
ESSI0 RX data with exception interrupt
ESSI0 RX data interrupt
ESSI0 receive last slot interrupt
ESSI0 TX data with exception interrupt
ESSI0 transmit last slot interrupt
ESSI0 TX data interrupt
ESSI1 RX data with exception interrupt
ESSI1 RX data interrupt
ESSI1 receive last slot interrupt
ESSI1 TX data with exception interrupt
ESSI1 transmit last slot interrupt
ESSI1 TX data interrupt
SCI receive data with exception interrupt
SCI receive data
SCI transmit data
SCI idle line
SCI timer
TIMER0 overflow interrupt
TIMER0 compare interrupt
TIMER1 overflow interrupt
TIMER1 compare interrupt
Table 4-6. Interrupt Source Priorities Within an IPL (Continued)
Priority Interrupt Source
Page 90
PLL Control Register (PCTL)
4-24 DSP56303 User’s Manual
4.5 PLL Control Register (PCTL)
The bootstrap program must initialize the system Phase-Lock Loop (PLL) circuit by
configuring the PLL Control Register (PCTL). The PCTL is an X-I/O mapped, read/write
register that directs the on-chip PLL operation. (See Figure 4-5.)
Table 4-7 defines the DSP56303 PCTL bits. Changing the following bits may cause the PLL
to lose lock and re-lock according to the new value: PD[3–0], PEN, XTLR, and MF.
TIMER2 overflow interrupt
Lowest TIMER2 compare interrupt
23 22 21 20 19 18 17 16 15 14 13 12
PD3 PD2 PD1 PD0 COD PEN PSTP XTLD XTLR DF2 DF1 DF0
11109876543210
MF11 MF10 MF9 MF8 MF7 MF6 MF5 MF4 MF3 MF2 MF1 MF0
Figure 4-5. PLL Control Register (PCTL)
Table 4-7. PLL Control Register (PCTL) Bit Definitions
Bit Number Bit Name Reset Value Description
23–20 PD[3–0] 0 Predivider Factor
Define the predivision factor (PDF) to be applied to the PLL input frequency.
The PD[3–0] bits are cleared during DSP56303 hardware reset, which
corresponds to a PDF of one.
19 COD 0 Clock Output Disable
Controls the output buffer of the cl oc k a t th e C L KOUT pin. When COD is s et,
the CLKOUT output is pulled high. When COD is cleared, the CLKOUT pin
provides a 50 percent duty cycle clock.
18 PEN Set to PINIT
input value
PLL Enable
Enables PLL operation.
17 PSTP 0 PLL Stop State
Controls PLL and on-chip crystal oscillator behavior during the stop
processing state.
16 XTLD 0 XTAL Disable
Controls the on-chip crystal oscillator XTAL output. The XTLD bit is cleared
during DSP56303 hardware reset, so the XTAL output signal is active,
permitting normal operation of the crystal oscillator.
15 XTLR 0 Crystal Range
Controls the on-chip crystal oscillator transconductance. The XTLR bit is
cleared (0) during hardware reset in the DSP56303.
Table 4-6. Interrupt Source Priorities Within an IPL (Continued)
Priority Interrupt Source
Page 91
Bus Interface Unit (BIU) Registers
Core Configuration 4-25
4.6 Bus Interface Unit (BIU) Registers
The three Bus Interface Unit (BIU) registers configure the external memory expansion port
(Port A). They include the following:
n Bus Control Register (BCR)
n DRAM Control Register (DCR)
n Address Attribute Registers (AAR[3–0])
To use Port A correctly, configure these registers as part of the bootstrap process. The
following subsections describe these registers.
4.6.1 Bus Control Register
The Bus Control Register (BCR), depicted in Figure 4-6, is a read/write register that controls
the external bus activity and Bus Interface Unit (BIU) operation. All BCR bits except bit 21,
BBS, are read/write bits. The BCR bits are defined in Table 4-8.
Figure 4-6. Bus Control Register (BCR)
14–12 DF[2–0] 0 Division Factor
Define the DF of the low-p ower divi der. Thes e bits spe cify the D F as a pow er
of two in the range from 2
0
to 27.
11–0 MF[11–0] 0 PLL Multiplication Factor
Define the multip li cation facto r that is a pplied to th e PLL input frequen cy. T he
MF bits are cleared during DSP56 303 hardwa re reset a nd thus corre spond to
an MF of one.
Table 4-7. PLL Control Re gister (PCTL) Bit Definitions (Continued )
Bit Number Bit Name Reset Value Description
23 22 21 20 19 18 17 16 15 14 13 12
BRH BLH BBS BDFW4 BDFW3 BDFW2 BDFW1 BDFW0 BA3W2 BA3W1 BA3W0 BA2W2
11109876543210
BA2W1 BA2W0 BA1W4 BA1W3 BA1W2 BA1W1 BA1W0 BA0W4 BA0W3 BA0W2 BA0W1 BA0W0
Page 92
Bus Interface Unit (BIU) Registers
4-26 DSP56303 User’s Manual
Table 4-8. Bus Control Register (BCR) Bit Definitions
Bit
Number
Bit Name Reset Value Description
23 BRH 0 Bus Request Hold
Asserts the BR signal, even if no ex tern al access is need ed. When BRH is set, t he
BR
signal is always asserted. If BRH is cleared, the BR is asserted only if an
external access is attempted or pending.
22 BLH 0 Bus Lock Hold
Asserts the BL
signal, even if no read-m odify-w rite acces s is occ urring. W hen BLH
is set, the BL
signal is always asserted. If BLH is cleared, the BL signal is asserted
only if a read-modify-write external access is attempted.
21 BBS 0 Bus State
This read-only bit is set when the DSP is the bus master and is cleared otherwise.
20–16 BDFW[4–0] 11111
(31 wait
states)
Bus Default Area Wait State Control
Defines th e number of wait states (one through 31) inserted into each external
access to an area that is n ot d efi ned by any of t he AAR re gis te rs. T he access type
for this area is SRAM only. These bits should not be programmed as zero since
SRAM memory access requires at least one wait state.
When four through seven wait states are selected, one additional wait state is
inserted at the end of the access. When selecting eight or more wait states, two
additional wait states are inserted at the end of the access. These trailing wait
states increase the data hold time and the memory release time and do not
increase the memory access time.
15–13 BA3W[2–0] 1
(7 wait states)
Bus Area 3 Wait State Control
Defines the number of wait states (one through seven) inserted in each external
SRAM access to Area 3 (D RAM acc esses a re not af fected by the se bits). Are a 3 is
the area defined by AAR3.
NOTE: Do not program the value of these bits as zero since SRAM memory
access requires at least one wait state.
When four through seven wait states are selected, one additional wait state is
inserted at the end of the access. This trailing wait state increases the data hold
time and the memory re lease time and does not increase the mem ory ac ce ss time.
12–10 BA2W[2–0] 111
(7 wait states)
Bus Area 2 Wait State Control
Defines the numbe r of wa it s t a tes (on e th rough seven) inse rted int o ea ch external
SRAM access to Area 2 (D RAM acc esses a re not af fected by the se bits). Are a 2 is
the area defined by AAR2.
NOTE: Do not program the value of these bits as zero, since SRAM memory
access requires at least one wait state.
When four through seven wait states are selected, one additional wait state is
inserted at the end of the access. This trailing wait state increases the data hold
time and the memory re lease time and does not increase the mem ory ac ce ss time.
Page 93
Bus Interface Unit (BIU) Registers
Core Configuration 4-27
4.6.2 DRAM Control Register (DCR)
The DRAM controller is an efficient interface to dynamic RAM devices in both random
read/write cycles and Fast Access mode (Page mode). An on-chip DRAM controller controls
the page hit circuit, the address multiplexing (row address and column address), the control
signal generation (
CAS and RAS) and the refresh access generation (CAS before RAS) for a
variety of DRAM module sizes and access times. The on-chip DRAM controller
configuration is determined by the DRAM Control Register (DCR). The DRAM Control
Register (DCR) is a 24-bit read/write register that controls and configures the external DRAM
accesses. The DCR bits are shown in Figure 4-7.
Note: To prevent improper device operation, you must guarantee that all the DCR bits
except BSTR are not changed during a DRAM access.
9–5 BA1W[4–0] 11111
(31 wait
states)
Bus Area 1 Wait State Control
Defines the number of wait states (one through 31) inserted into each external
SRAM access to Area 1 (D RAM acc esses a re not af fected by the se bits). Are a 1 is
the area defined by AAR1.
NOTE: Do not program the value of these bits as zero, since SRAM memory
access requires at least one wait state.
When four through seven wait states are selected, one additional wait state is
inserted at the end of the access. When selecting eight or more wait states, two
additional wait states are inserted at the end of the access. These trailing wait
states increase the data hold time and the memory release time and do not
increase the memory access time.
4–0 BA0W[4–0] 11111
(31 wait
states)
Bus Area 0 Wait State Control
Defines the number of wait states (one through 31) inserted in each external
SRAM access to Area 0 (D RAM acc esses a re not af fected by the se bits). Are a 0 is
the area defined by AAR0.
NOTE: Do not program the value of these bits as zero, since SRAM memory
access requires at least one wait state.
When selecting four throu gh seven wait states, one add itional w ait state is inserte d
at the end of the access. When selecting eight or more wait states, two additional
wait states are inserted at the en d of the a ccess. The se traili ng wait states i ncrease
the data hold time and the memory release time and do not increase the memory
access time.
Table 4-8. Bus Control Register (BCR) Bit Definitions (Continued)
Bit
Number
Bit Name Reset Value Description
Page 94
Bus Interface Unit (BIU) Registers
4-28 DSP56303 User’s Manual
Figure 4-7. DRAM Control Register (DCR)
Table 4-9. DRAM Control Register (DCR) Bit Definitions
Bit
Number
Bit Name
Reset
Value
Description
23 BRP 0 Bus Refresh Prescaler
Controls a prescaler in series with the refresh clock divider. If BPR is set, a
divide-by-64 prescaler is connected in series with the refresh clock divider. If BPR is
cleared, the prescaler is bypassed. The refresh request rate (in clock cycles) is the
value written to BRF[7–0] bits + 1, multiplied by 64 (if BRP is set) or by one (if BRP is
cleared). When programming the periodic refresh rate, you must consider the RAS
time-out period. Hardware support for the RAS
time-out restriction does not exist.
NOTE: Refresh requests are not accumulated and, therefore, in a fast refresh request
rate not all the refresh requests are served (for example, the combination BRF[7–0] =
$00 and BRP = 0 generates a refresh request every clock cycle, but a refresh access
takes at least five clock cycles).
22–15 BRF[7–0] 0 Bus Refresh Rate
Controls the refresh request rate. The BRF[7–0] bits specify a divide rate of 1–256
(BRF[7–0] = $00–$FF). A refresh request is generated each time the refresh counter
reaches zero if the refresh counter is enabled (BRE = 1).
14 BSTR 0 Bus Software Triggered Reset
Generates a software-triggered refresh request. When BSTR is set, a refresh request
is generated and a refresh access is executed to all DRAM banks (the exact timing of
the refresh access depends on the pending external accesses and the status of the
BME bit). After the ref resh a cces s (CAS
before RAS) is executed, the DRA M controlle r
hardware clears the BSTR bit. The refresh cycle length depends on the BRW[1–0] bits
(a refresh access is as long as the out-of-page access).
13 BREN 0 Bus Refresh Enable
Enables/disables th e internal ref resh cou nter. When BREN is set, the refres h counter i s
enabled and a refresh request (CAS
before RAS) is generated each time the r efresh
counter reaches zero. A refresh cycle occurs for all DRAM banks together (that is, all
pins that are defined as RAS
are asserted together). When this bit is cleared, the
refresh counter is disabled and a refresh request may be software triggered by using
the BSTR bit. In a system in which DSPs share the same DRAM, the DRAM controller
of more than one DSP may be active, but it is recommended that only one DSP have
its BREN bit set and that bus mastership is requested for a refresh access. If BREN is
set and a WAIT i ns truc t io n is ex ec uted, periodic refres h is still generate d each time the
refresh counter reaches zero. If BREN is set and a STOP instruction is executed,
periodic refresh is not generated and the refresh counter is disabled. The contents of
the DRAM are lost.
23 22 21 20 19 18 17 16 15 14 13 12
BRP BRF7 BRF6 BRF5 BRF4 BRF3 BRF2 BRF1 BRF0 BSTR BREN BME
11109876543210
BPLE
BPS1 BPS0 BRW1 BRW0 BCW1 BCW0
Reserved bit. Read as zero; write to zero for future compatibility
Page 95
Bus Interface Unit (BIU) Registers
Core Configuration 4-29
12 BME 0 Bus Mastership Enable
Enables/disables interface to a local DRAM for the DSP. When BME is cleared, the
RAS and CAS pins are tri-stated when mastershi p is lost. The refo re, you mu st conn ect
an external pull-up resistor to these pins. In this case (BME = 0), the DSP DRAM
controller assumes a page fault each time the mastership is lost. A DRAM refresh
requires a bus mastership. If the BME bit is set, the RAS
and CAS pins are always
driven from the DSP. Therefore, DRAM refresh can be performed, even if the DSP is
not the bus master.
11 BPLE 0 Bus Page Logic Enable
Enables/disables the in-page identifying logic. When BPLE is set, it enables the page
logic (the page size is defined b y BPS[1–0] bi ts). Each in-pa ge identi fication cau ses the
DRAM controller to drive only the column address (and the associated CAS
signal).
When BPLE is cleared, the page logic is disabled, and the DRAM controller always
accesses the external DRAM in out-of-page accesses (for example, row address with
RAS
assertion and then column address with CAS assertion). This mode is useful for
low power dissipation. Only one in-page identifying logic exists. Therefore, during
switches from one DRAM external bank to another DRAM bank (the DRAM external
banks are defined by the access type bits in the AARs, different external banks are
accessed through different AA/RAS
pins), a page fault occurs.
10
0 Reserved. Write to zero for future compatibility.
9–8 BPS[1–0] 0 Bus DRAM Page Size
Defines the size of the external DRAM page and thus the number of the column
address bits. The internal page mechanism works according to these bits only if the
page logic is enab led (by th e BPL E bi t). The four combinati ons of BPS[1 –0] ena bl e th e
use of many DRAM sizes (1 M bit, 4 M bit, 16 M bit, and 64 M bit). The encoding of
BPS[1–0] is:
00 = 9-bit column width, 512 words
01 = 10-bit column width, 1 K words
10 = 11-bit column width, 2 K words
11 = 12-bit column width, 4 K words
When the row address is driven, all 24 bits of the external address bus are driven [for
example, if BPS[1–0] = 01, when driving the row address, the 14 MSBs of the internal
address (XAB, YAB, PAB, or DAB) are driven on address lines A[0–13], and the
address lines A[14–23] are driven with the 10 MSBs of the internal address. This
method enables the use of different DRAMs with the same page size.
7–4
0 Reserved. Write to zero for future compatibility.
3–2 BRW[1–0] 0 Bus Row Out-of-page Wait States
Defines the number of w ait sta t es tha t s hou ld b e inserted into each D RA M o ut-o f-page
access. The encoding of BRW[1–0] is:
00 = 4 wait states for each out-of-page access
01 = 8 wait states for each out-of-page access
10 = 11 wait states for each out-of-page access
11 = 15 wait states for each out-of-page access
1–0 BCW[1–0] 0 Bus Column In-Page Wait State
Defines the number of wait states to insert for each DRAM in-page access. The
encoding of BCW[1–0] is:
00 = 1 wait st ate for each in- page access
01 = 2 wait states for each in-page access
10 = 3 wait states for each in-page access
11 = 4 wait states for each in-page access
Table 4-9. DRAM Control Register (DCR) Bit Definitions (Continued )
Bit
Number
Bit Name
Reset
Value
Description
Page 96
Bus Interface Unit (BIU) Registers
4-30 DSP56303 User’s Manual
4.6.3 Address Attribute Registers (AAR[0–3])
The Address Attribute Registers (AAR[0–3]) are read/write registers that control the activity
of the
AA0/RAS0–AA3/RAS3 pins. The associated AAn/RASn pin is asserted if the address
defined by the BAC bits in the associated AAR matches the exact number of external address
bits defined by the BNC bits, and the external address space (X data, Y data, or program) is
enabled by the AAR. Figure 4-8 shows an AAR register; Table 4-10 lists the bit definitions.
Note: The DSP56303 does not support address multiplexing.
Figure 4-8. Address Attribute Registers (AAR[0–3]) (X:$FFFFF9–$FFFFF6)
Table 4-10. Address Attribute Registers (AAR[0–3]) Bit Definitions
Bit
Number
Bit Name
Reset
Value
Description
23–12 BAC[11–0] 0 Bus Address to Compare
Read/write control bits that define the upper 12 bits of the 24-bit address with which to
compare the external address to determine whether to assert the corresponding AA/RAS
signal. This is also true of 16-bit c ompati bilit y mode . The BNC[ 3–0] bits defi ne the nu mber
of address bits to compare.
11–8 BNC[3–0] 0 Bus Number of Address Bits to Compare
Specify the number of bits (from the BAC bits) that are compared to the external address.
The BAC bits are always compared with the Most Significant Portion of the external
address (for example , i f BN C[3– 0] = 0011, then the BAC [11 –9] bi ts are compared to the 3
MSBs of the external address). If no bits are specified (that is, BNC[3–0] = 0000), the AA
signal is activated for the entire 16 M-word space identified by the space enable bits
(BPEN, BXEN, BYEN), but only when the add ress is ex ternal to th e inter nal me mory map.
The combinations BNC[3–0] = 1111, 1110, 1101 are reserved.
BAC0
BPEN
0
1
BYEN
2
BAT1
3
BAAP
4
567891011
BXEN
121314
BAC8
15
1617181920212223
BAT0
BAC3 BAC2BAC11 BAC5BAC7 BAC6BAC9BAC10 BAC1
BNC3
BNC1BNC2
BNC0
BAC4
BPAC
Reserved Bit. Write to zero for future compatibility.
External Access Type
AA pin polarity
Program space Enable
X data space Enable
Y data space Enable
Reserved
Packing Enable
Number of Address bit to
compare
Address to Compare
Page 97
Bus Interface Unit (BIU) Registers
Core Configuration 4-31
7 BPAC 0 Bus Packing Enable
Enables/disables the internal packing/unpacking logic. When BPAC is set, packing is
enabled. In this mode each DMA external access initiates three external accesses to an
8-bit wide external m emory (the addresses for these accesses are DAB, th en DAB + 1 and
then DAB + 2). Packing to a 24-bit word (or unpacking from a 24-bit word to three 8-bit
words) is done automat ically by the expansion port control hardware. The external
memory should reside in the eight Least Significant Bits (LSBs) of the external data bus,
and the packing (or unpacking for external write accesses) occurs in “Little Endian” order
(that is, the low byte is stored in the lowest of the three memory locations and is
transferred first; the middle byte is stored/transferred next; and the high byte is
stored/transferred las t). When thi s bit is cleared , the expa nsion port c ont rol logi c assu mes
a 24-bit wide external memory.
NOTES:
1. BPAC is used only for DMA accesses and not core accesses.
2. To ensure sequential external accesses, the DMA address should advance three
steps at a time in two -di mensi onal mode with a row length of on e and an o ffset size of
three. For details, refer to Motorola application note, APR23/D,
Using the DSP56300
Direct Memory Access Controller
.
3. To prevent improper operation, DMA address + 1 and DMA
address + 2 should not cross the AAR bank borders.
4. Arbitration is not allowed during the packing access (that is, the three accesses are
treated as one access with respect to arbitration, and the bus mastership is not
released during these accesses).
6
0 Reserved. Write to 0 for future compatibility.
5 BYEN 0 Bus Y Data Memory Enable
A read/write control bit that enables/disables the AA pin and logic during external Y data
space accesses. When set, BYEN enables the comparison of the external address to the
BAC bits during external Y data space accesses. If BYEN is cleared, no address
comparison is performed.
4 BXEN 0 Bus X Data Memory Enable
A read/write control bit that enables/disables the AA pin and logic during external X data
space accesses. When set, BXEN enables the comparison of the external address to the
BAC bits during external X data space accesses. If BXEN is cleared, no address
comparison is performed.
3 BPEN 0 Bus Program Memory Enable
A read/write control bit that enables/disables the AA/RAS
pin and logic during external
program space accesses. When set, BPEN enables the comparison of the external
address to the BAC bits during external program space accesses. If BPEN is cleared, no
address comparison is performed.
2 BAAP 0
Bus Address Attribute Polarity
A read/write Bus Address Attribute Polarity (BAAP) control bit that defines whether the
AA/RAS
signal is active low or active high. When BAAP is cleared, the AA/RAS signal is
active low (useful for enabling memory modules or for DRAM Row Address Strobe). If
BAAP is set, the appropriate AA/RAS
signal is active high (usefu l as an additi onal addres s
bit).
Table 4-10. Address Attribute Registers (AAR[0–3]) Bit Definitions
Bit
Number
Bit Name
Reset
Value
Description
Page 98
DMA Control Registers 5–0 (DCR[5–0])
4-32 DSP56303 User’s Manual
4.7 DMA Control Registers 5–0 (DCR[5–0])
The DMA Control Registers (DCR[5–0]) are read/write registers that control the DMA
operation for each of their respective channels. All DCR bits are cleared during processor
reset.
Figure 4-9. DMA Control Register (DCR)
1–0 BAT[1–0] 0 Bus Access Type
Read/write bits that define the type of external memory (DRAM or SRAM) to access for
the area defined by the BAC[11–0],BYEN, BXEN, and BPEN bits. The encoding of
BAT[1–0] is:
00 = Reserved
01 = SRAM access
10 = DRAM access
11 = Reserved
When the external access type is defined as a DRAM access (BAT[1–0] = 10), AA/RAS
acts as a Row Address Strobe (RAS) signal. Otherwise, it acts as an Address Attribute
signal. External accesses to the default area always execute as if BAT[1–0] = 01 (that is,
SRAM access). If Port A is used for external accesses, the BAT bits in the AAR3–0
registers must be initialized to the SRAM access type (that is, BAT = 01) or to the DRAM
access type (that is BAT = 10). To ensure proper operation of Port A, this initialization
must occur even for an AAR register that is not used during any Port A access. Note that
at reset, the BAT bits are initialized to 00.
Table 4-11. DMA Control Register (DCR) Bit Definitions
Bit
Number
Bit Name
Reset
Value
Description
23 DE 0 DMA Channel Enable
Enables the channel operation. Setting DE either triggers a single block DMA transfer in the
DMA transfer mode that uses DE as a trigger or enables a single-block, single-line, or
single-word DMA transfe r in the tra nsfer mo des th at use a requ esting d evice as a trigger . DE
is cleared by the end of DMA tra nsfer in some of the transfer mo des define d by the DTM bits.
If software explicitly clears DE during a DMA operation, the channel operation stops only
after the current DMA transfer completes (that is, the current word is stored into the
destination).
Table 4-10. Address Attribute Registers (AAR[0–3]) Bit Definitions
Bit
Number
Bit Name
Reset
Value
Description
23 22 21 20 19 18 17 16 15 14 13 12
DE DIE DTM2 DTM1 DTM0 DPR1 DPR0 DCON DRS4 DRS3 DRS2 DRS1
11109876543210
DRS0 D3D DAM5 DAM4 DAM3 DAM2 DAM1 DAM0 DDS1 DDS0 DSS1 DSS0
Page 99
DMA Control Registers 5–0 (DCR[5–0])
Core Configuration 4-33
22 DIE 0 DMA Interrupt Enable
Generates a DMA interrupt at the end of a DMA block transfer after the counter is loaded
with its preloaded value. A DMA interrupt is also generated when software explicitly clears
DE
during a DMA operation. Once asserted, a DMA interrupt requ est can be cle ared only by
the service of a DMA interrupt routine. To ensure that a new interrupt request is not
generated, clear DIE while the DMA interrupt is serviced and before a new DMA request is
generated at the end of a DMA block transfer—that is, at the beginning of the DMA channel
interrupt service rout ine. When DIE is cleared, the DMA interrupt is disa bled.
21–19 DTM[2–0] 0 DMA Transfer Mode
Specify the operating modes of the DMA channel, as follows:
DTM[2–0] Trigger
DE
Cleared
After
Transfer Mode
000 request Yes
Block Transfer—DE enabled and DMA request initiated.
The transfer is complete when th e counter decrements to
zero and the DMA controller reloads the counter with the
original value.
001 request Yes
Word Transfer—A word-by-word block transfer (length
set by the counter) that is DE enabled. The transfer is
complete when the counter decrements to zero and the
DMA controller reloads the counter with the original
value.
010 request Yes Line Transfer—A line by line block transfer (length set by
the counter) that is DE enabled. The transfer is complete
when the counter decrements to zero and the DMA
controller reloads the counter with the original value.
011 DE Yes
Block Transfer—The DE-initiated transfer is complete
when the counter decrements to zero and the DMA
controller reloads the counter with the original value.
100 request No
Block Transfer—The transfer is enabled by DE and
initiated by the first DMA request. The transfer is
completed when the counter decrements to zero and
reloads itself with the original value. The DE bit is not
cleared at the end of the bloc k, so the DMA ch annel wai ts
for a new request.
NOTE: The DMA End-of-Block-Transfer Interrupt cannot
be used in this mode.
101 request No Word Transfer—The transfer is enabled by DE and
initiated by every DMA request. When the counter
decrements to zero, it is reloaded with its original value.
The DE bit is not automatically cleared, so the DMA
channel waits for a new request.
NOTE: The DMA End-of-Block-Transfer Interrupt cannot
be used in this mode.
110 Reserved
111 Reserved
NOTE: When DTM[2–0] = 001 or 101, some peripherals can generate a second DMA request while the DMA controller is
still processing the first request (see the description of the DRS bits).
Table 4-11. DMA Control Register (DCR) Bit Definitions (Continue d)
Bit
Number
Bit Name
Reset
Value
Description
Page 100
DMA Control Registers 5–0 (DCR[5–0])
4-34 DSP56303 User’s Manual
18–17 DPR[1–0] 0 DMA Channel Priority
Define the DMA chan nel pri orit y re lat iv e to the oth er DM A c han nel s and to the core priority i f
an external bus access is required. For pending DMA transfers, the DMA controller
compares channel priority levels to determine which channel can activate the next word
transfer. This dec is ion is req uired because all cha nne ls us e c omm on resources, such a s th e
DMA address generation logic, buses, and so forth.
DPR[1–0] Channel Priority
00 Priority level 0 (lowest)
01 Priority level 1
10 Priority level 2
11 Priority level 3 (highest)
n If all or some channels have the same priority, then channels are activated in a
round-robin fashion—that is, channel 0 is activated to transfer one word, followed by
channel 1, then channel 2, and so on.
n If channels have different priorities, the highest priority channel executes DMA
transfers and continues for its pending DMA transfers.
n If a lower-priority channel is executing DMA transfers when a higher priority channel
receives a transfer request, the lower-priority channel finishes the current word
transfer and arbitration starts again.
n If some channels with the same priority are active in a round-robin fashion and a new
higher-priority channel receives a transfer request, the higher-priority channel is
granted transfer access after the current word transfer is complete. After the
higher-priority channel tra nsfers are c omplete, the roun d-robin trans fers conti nue. The
order of transfers in the round-ro bi n mo de m ay cha nge , bu t the a lgo rith m rem ai ns the
same.
n The DPR bits also determine the DMA priority relative to the core priority for external
bus access. Arbitration uses the current active DMA priority, the core priority defined
by the SR bits CP[1–0], and the core-DM A priority define d by the OMR bits C DP[1–0].
Priority of core accesses to external memory is as follows:
Table 4-11. DMA Control Registe r (DCR) Bit Definitions (Continue d)
Bit
Number
Bit Name
Reset
Value
Description
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