Motorola DSP56301 User Manual
DSP56301 User’s Manual
24-Bit Digital Signal Processor
DSP56301UM/AD
Revision 3, March 2001
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MOTOROLA INC., 1996, 2001
Overview
1
Signals/Connections
Memory Configuration
Core Configura tio n
Programming the Peripherals
Host Interface (HI32)
Enhanced Synchronous Serial Interface (ESSI)
2
3
4
5
6
7
Serial Communications Interface (SCI)
Triple Timer Module
Bootstrap Program
Programming Reference
8
9
A
B
1
Overview
2
3
4
5
6
7
Signals/Connections
Memory Configuration
Core Configuration
Programming the Peripherals
Host Interface (HI32)
Enhanced Synch ron ous Serial Interface (ESSI)
A
B
8
9
Serial Communications Interface (SCI)
Triple Timer Module
Bootstrap Program
Programming Reference
Contents
Chapter 1
Overview
1.1 Manual Organization .............................................................................................................1-1
1.2 Manual Conventions.............................................................................................................. 1-2
1.3 DSP56300 Core Features.......................................................................................................1-4
1.4 DSP56300 Core Functional Blocks.......................................................................................1-6
1.4.1 Data ALU............................................................................................................................... 1-6
1.4.1.1 Data ALU Registers......................................................................................................... 1-7
1.4.1.2 Multiplier-Accumulator (MAC) ...................................................................................... 1-7
1.4.2 Address Generation Unit (AGU)........................................................................................... 1-7
1.4.3 Program Control Unit (PCU).................................................................................................1-8
1.4.4 PLL and Clock Oscillator ...................................................................................................... 1-9
1.4.5 JTAG TAP and OnCE Module.............................................................................................. 1-9
1.4.6 On-Chip Memory................................................................................................................. 1-10
1.5 Internal Buses ...................................................................................................................... 1-10
1.6 DMA....................................................................................................................................1-11
1.7 Peripherals ........................................................................................................................... 1-12
1.7.1 General-Purpose Input/Output (GPIO) signals.................................................................... 1-12
1.7.2 Host Interface (HI32)........................................................................................................... 1-12
1.7.3 Enhance Synchronous Serial Interface (ESSI) .................................................................... 1-12
1.7.4 Serial Communications Interface (SCI)............................................................................... 1-13
1.7.5 Triple Timer Module ........................................................................................................... 1-13
1.8 Related Documents and Web Sites...................................................................................... 1-14
Chapter 2
Signals/Connections
2.1 Power ..................................................................................................................................... 2-4
2.2 Ground ................................................................................................................................... 2-4
2.3 Clock...................................................................................................................................... 2-5
2.4 PLL ........................................................................................................................................ 2-5
2.5 External Memory Expansion Port (Port A) ........................................................................... 2-6
2.5.1 External Address Bus............................................................................................................. 2-6
2.5.2 External Data Bus..................................................................................................................2-6
2.5.3 External Bus Control ............................................................................................................. 2-6
2.6 Interrupt and Mode Control...................................................................................................2-9
2.7 Host Interface (HI32)........................................................................................................... 2-10
Contents v
2.8 Enhanced Synchronous Serial Interface 0 ........................................................................... 2-22
2.9 Enhanced Synchronous Serial Interface 1 ........................................................................... 2-25
2.10 Serial Communications Interface (SCI)............................................................................... 2-27
2.11 Timers..................................................................................................................................2-27
2.12 JTAG and OnCE Interface................................................................................................... 2-29
Chapter 3
Memory Configuration
3.1 Program Memory Space ........................................................................................................ 3-1
3.1.1 Internal Program Memory .................................................................................................... 3-2
3.1.2 Memory Switch Modes—Program Memory.........................................................................3-2
3.1.3 Instruction Cache...................................................................................................................3-2
3.1.4 Program Bootstrap ROM.......................................................................................................3-3
3.2 X Data Memory Space........................................................................................................... 3-3
3.2.1 Internal X Data Memory........................................................................................................ 3-3
3.2.2 Memory Switch Modes—X Data Memory ........................................................................... 3-3
3.2.3 Internal I/O Space—X Data Memory.................................................................................... 3-4
3.3 Y Data Memory Space........................................................................................................... 3-4
3.3.1 Internal Y Data Memory........................................................................................................ 3-4
3.3.2 Memory Switch Modes—Y Data Memory ........................................................................... 3-4
3.3.3 External I/O Space—Y Data Memory................................................................................... 3-5
3.4 Dynamic Memory Configuration Switching ......................................................................... 3-5
3.5 Sixteen-Bit Compatibility Mode Configuration....................................................................3-6
3.6 Internal Memory Configuration Summary ............................................................................ 3-6
3.7 Memory Maps........................................................................................................................ 3-7
Chapter 4
Core Configuration
4.1 Operating Modes.................................................................................................................... 4-2
4.2 Bootstrap Program.................................................................................................................4-5
4.3 Central Processor Unit (CPU) Registers................................................................................4-6
4.3.1 Status Register (SR)............................................................................................................... 4-6
4.3.2 Operating Mode Register (OMR)........................................................................................4-12
4.4 Configuring Interrupts ......................................................................................................... 4-15
4.4.1 Interrupt Priority Registers (IPRC and IPRP)...................................................................... 4-16
4.4.2 Interrupt Table Memory Map .............................................................................................. 4-17
4.4.3 Processing Interrupt Source Priorities Within an IPL ......................................................... 4-19
4.5 PLL Control Register (PCTL) ............................................................................................. 4-21
4.6 Bus Interface Unit (BIU) Registers ..................................................................................... 4-22
4.6.1 Bus Control Register............................................................................................................ 4-22
4.6.2 DRAM Control Register (DCR)..........................................................................................4-24
4.6.3 Address Attribute Registers (AAR[0–3]) ............................................................................ 4-27
4.7 DMA Control Registers 5–0 (DCR[5–0]) ........................................................................... 4-29
4.8 Device Identification Register (IDR)................................................................................... 4-34
vi DSP56303 DSP56301 User’s Manual
4.9 JTAG Identification (ID) Register....................................................................................... 4-35
4.10 JTAG Boundary Scan Register (BSR)................................................................................. 4-35
Chapter 5
Programming the Peripherals
5.1 Peripheral Initialization Steps................................................................................................ 5-1
5.2 Mapping the Control Registers.............................................................................................. 5-2
5.3 Data Transfer Methods ..........................................................................................................5-2
5.3.1 Polling.................................................................................................................................... 5-2
5.3.2 Interrupts................................................................................................................................ 5-3
5.3.3 DMA......................................................................................................................................5-4
5.3.4 Advantages and Disadvantages ............................................................................................. 5-4
5.4 General-Purpose Input/Output (GPIO).................................................................................. 5-4
5.4.1 Port B Signals and Registers.................................................................................................. 5-5
5.4.2 Port C Signals and Registers.................................................................................................. 5-6
5.4.3 Port D Signals and Registers ................................................................................................. 5-6
5.4.4 Port E Signals and Registers.................................................................................................. 5-6
5.4.5 Triple Timer Signals and Registers ....................................................................................... 5-7
Chapter 6
Host Interface (HI32)
6.1 Features.................................................................................................................................. 6-1
6.2 Overview................................................................................................................................ 6-4
6.3 Data Transfer Paths................................................................................................................6-6
6.3.1 Host-to-DSP Data Path..........................................................................................................6-6
6.3.2 DSP-To-Host Data Path......................................................................................................... 6-7
6.4 Reset States.......................................................................................................................... 6-12
6.5 DSP-Side Operating Modes................................................................................................. 6-12
6.5.1 Terminate and Reset (DCTR[HM] = $0)...........................................................................6-13
6.5.2 PCI Mode (DCTR[HM] = $1) ........................................................................................... 6-13
6.5.3 Universal (DCTR[HM] = $2) and Enhanced Universal (DCTR[HM] = $3) Bus Modes 6-15
6.5.4 GPIO Mode (DCTR[HM] = $4)........................................................................................6-16
6.5.5 Self-Configuration Mode (DCTR[HM] = $5) ................................................................... 6-16
6.6 Host Port Pins ...................................................................................................................... 6-18
6.7 HI32 DSP-Side Programming Model..................................................................................6-22
6.7.1 DSP Control Register (DCTR)............................................................................................ 6-23
6.7.2 DSP PCI Control Register (DPCR)..................................................................................... 6-26
6.7.3 DSP PCI Master Control Register (DPMC)........................................................................ 6-30
6.7.4 DSP PCI Address Register (DPAR)....................................................................................6-33
6.7.5 DSP Status Register (DSR)..................................................................................................6-35
6.7.6 DSP PCI Status Register (DPSR)........................................................................................6-38
6.7.7 DSP Receive Data FIFO (DRXR) ....................................................................................... 6-41
6.7.8 DSP Master Transmit Data Register (DTXM) .................................................................... 6-42
6.7.9 DSP Slave Transmit Data Register (DTXS)........................................................................ 6-42
Contents vii
6.7.10 DSP Host Port GPIO Direction Register (DIRH)................................................................6-43
6.7.11 DSP Host Port GPIO Data Register (DATH)......................................................................6-43
6.8 Host-Side Programming Model...........................................................................................6-44
6.8.1 HI32 Control Register (HCTR) ........................................................................................... 6-48
6.8.2 Host Interface Status Register (HSTR)................................................................................ 6-56
6.8.3 Host Command Vector Register (HCVR) ........................................................................... 6-59
6.8.4 Host Master Receive Data Register (HRXM) ..................................................................... 6-61
6.8.5 Host Slave Receive Data Register (HRXS).........................................................................6-61
6.8.6 Host Transmit Data Register (HTXR).................................................................................6-62
6.8.6.1 PCI Mode (DCTR[HM] = $1) ....................................................................................... 6-63
6.8.6.2 Universal Bus mode (DCTR[HM] = $2 or $3).............................................................. 6-63
6.8.7 Device ID/Vendor ID Configuration Register (CDID/CVID)............................................. 6-64
6.8.8 Status/Command Configuration Register (CSTR/CCMR).................................................. 6-64
6.8.9 Class Code/Revision ID Configuration Register (CCCR/CRID)........................................ 6-67
6.8.10 Header Type/Latency Timer Configuration Register (CHTY/CLAT/CCLS)..................... 6-68
6.8.11 Memory Space Base Address Configuration Register (CBMA)......................................... 6-70
6.8.12 Subsystem ID and Subsystem Vendor ID Configuration Register (CSID)......................... 6-71
6.8.13 Interrupt Line-Interrupt Pin Configuration Register(CILP) ................................................ 6-73
6.9 HI32 Programming Model/Quick Reference....................................................................... 6-74
Chapter 7
Enhanced Synchronous Serial Interface (ESSI)
7.1 ESSI Enhancements............................................................................................................... 7-2
7.2 ESSI Data and Control Signals.............................................................................................. 7-3
7.2.1 Serial Transmit Data Signal (STD)........................................................................................7-3
7.2.2 Serial Receive Data Signal (SRD)......................................................................................... 7-3
7.2.3 Serial Clock (SCK)................................................................................................................ 7-3
7.2.4 Serial Control Signal (SC0)................................................................................................... 7-4
7.2.5 Serial Control Signal (SC1)................................................................................................... 7-4
7.2.6 Serial Control Signal (SC2)................................................................................................... 7-6
7.3 Operation ............................................................................................................................... 7-6
7.3.1 ESSI After Reset.................................................................................................................... 7-6
7.3.2 Initialization........................................................................................................................... 7-6
7.3.3 Exceptions.............................................................................................................................. 7-7
7.4 Operating Modes: Normal, Network, and On-Demand....................................................... 7-10
7.4.1 Normal/Network/On-Demand Mode Selection................................................................... 7-10
7.4.2 Synchronous/Asynchronous Operating Modes ................................................................... 7-11
7.4.3 Frame Sync Selection .......................................................................................................... 7-11
7.4.4 Frame Sync Signal Format .................................................................................................. 7-11
7.4.5 Frame Sync Length for Multiple Devices............................................................................ 7-12
7.4.6 Word Length Frame Sync and Data Word Timing.............................................................. 7-12
7.4.7 Frame Sync Polarity............................................................................................................. 7-12
7.4.8 Byte Format (LSB/MSB) for the Transmitter......................................................................7-13
7.4.9 Flags..................................................................................................................................... 7-13
7.5 ESSI Programming Model................................................................................................... 7-14
viii DSP56303 DSP56301 User’s Manual
7.5.1 ESSI Control Register A (CRA).......................................................................................... 7-14
7.5.2 ESSI Control Register B (CRB) .......................................................................................... 7-18
7.5.3 ESSI Status Register (SSISR).............................................................................................. 7-28
7.5.4 ESSI Receive Shift Register ................................................................................................7-29
7.5.5 ESSI Receive Data Register (RX) ....................................................................................... 7-30
7.5.6 ESSI Transmit Shift Registers............................................................................................. 7-30
7.5.7 ESSI Transmit Data Registers (TX[2–0])............................................................................7-33
7.5.8 ESSI Time Slot Register (TSR)........................................................................................... 7-33
7.5.9 Transmit Slot Mask Registers (TSMA, TSMB).................................................................. 7-33
7.5.10 Receive Slot Mask Registers (RSMA, RSMB)................................................................... 7-35
7.6 GPIO Signals and Registers................................................................................................. 7-36
7.6.1 Port Control Registers (PCRC and PCRD)..........................................................................7-36
7.6.2 Port Direction Registers (PRRC and PRRD)....................................................................... 7-37
7.6.3 Port Data Registers (PDRC and PDRD).............................................................................. 7-38
Chapter 8
Serial Communication Interface (SCI)
8.1 Operating Modes.................................................................................................................... 8-1
8.1.1 Synchronous Mode ................................................................................................................ 8-2
8.1.2 Asynchronous Mode.............................................................................................................. 8-2
8.1.3 Multidrop Mode..................................................................................................................... 8-2
8.1.3.1 Transmitting Data and Address Characters..................................................................... 8-3
8.1.3.2 Wired-OR Mode .............................................................................................................. 8-3
8.1.3.3 Idle Line Wakeup............................................................................................................. 8-3
8.1.3.4 Address Mode Wakeup.................................................................................................... 8-3
8.2 I/O Signals ............................................................................................................................. 8-3
8.2.1 Receive Data (RXD)..............................................................................................................8-4
8.2.2 Transmit Data (TXD)............................................................................................................. 8-4
8.2.3 SCI Serial Clock (SCLK) ...................................................................................................... 8-4
8.3 SCI After Reset......................................................................................................................8-5
8.4 SCI Initialization.................................................................................................................... 8-6
8.4.1 Preamble, Break, and Data Transmission Priority................................................................. 8-7
8.4.2 Bootstrap Loading Through the SCI (Boot Mode 2 or A)..................................................... 8-8
8.5 Exceptions.............................................................................................................................. 8-8
8.6 SCI Programming Model....................................................................................................... 8-9
8.6.1 SCI Control Register (SCR) ................................................................................................ 8-12
8.6.2 SCI Status Register (SSR) ................................................................................................... 8-17
8.6.3 SCI Clock Control Register (SCCR)................................................................................... 8-19
8.6.4 SCI Data Registers............................................................................................................... 8-22
8.6.4.1 SCI Receive Register (SRX).......................................................................................... 8-22
8.6.4.2 SCI Transmit Register (STX) ........................................................................................ 8-23
8.7 GPIO Signals and Registers................................................................................................. 8-24
8.7.1 Port E Control Register (PCRE).......................................................................................... 8-24
8.7.2 Port E Direction Register (PRRE) ....................................................................................... 8-25
8.7.3 Port E Data Register (PDRE)............................................................................................... 8-25
Contents ix
Chapter 9
Triple Timer Module
9.1 Overview................................................................................................................................ 9-1
9.1.1 Triple Timer Module Block Diagram....................................................................................9-2
9.1.2 Individual Timer Block Diagram........................................................................................... 9-2
9.2 Operation ............................................................................................................................... 9-3
9.2.1 Timer After Reset ..................................................................................................................9-3
9.2.2 Timer Initialization ................................................................................................................ 9-4
9.2.3 Timer Exceptions................................................................................................................... 9-4
9.3 Operating Modes.................................................................................................................... 9-5
9.3.1 Triple Timer Modes............................................................................................................... 9-6
9.3.1.1 Timer GPIO (Mode 0) ..................................................................................................... 9-6
9.3.1.2 Timer Pulse (Mode 1)...................................................................................................... 9-8
9.3.1.3 Timer Toggle (Mode 2) ................................................................................................. 9-10
9.3.1.4 Timer Event Counter (Mode 3) ..................................................................................... 9-12
9.3.2 Signal Measurement Modes................................................................................................. 9-14
9.3.2.1 Measurement Input Width (Mode 4) ............................................................................. 9-14
9.3.2.2 Measurement Input Period (Mode 5)............................................................................. 9-16
9.3.2.3 Measurement Capture (Mode 6).................................................................................... 9-18
9.3.3 Pulse Width Modulation (PWM, Mode 7)........................................................................... 9-19
9.3.4 Watchdog Modes................................................................................................................. 9-22
9.3.4.1 Watchdog Pulse (Mode 9) ............................................................................................. 9-22
9.3.4.2 Watchdog Toggle (Mode 10)......................................................................................... 9-24
9.3.4.3 Reserved Modes............................................................................................................. 9-25
9.3.5 Special Cases ....................................................................................................................... 9-25
9.3.6 DMA Trigger....................................................................................................................... 9-25
9.4 Triple Timer Module Programming Model......................................................................... 9-25
9.4.1 Prescaler Counter................................................................................................................. 9-25
9.4.2 Timer Prescaler Load Register (TPLR)............................................................................... 9-27
9.4.3 Timer Prescaler Count Register (TPCR) ............................................................................. 9-28
9.4.4 Timer Control/Status Register (TCSR)................................................................................ 9-28
9.4.5 Timer Load Register (TLR).................................................................................................9-33
9.4.6 Timer Compare Register (TCPR)........................................................................................ 9-34
9.4.7 Timer Count Register (TCR)............................................................................................... 9-34
Chapter A
Bootstrap Program
Chapter
B
Programming Reference
B.1 Internal I/O Memory Map......................................................................................................B-3
B.2 Interrupt Sources and Priorities .............................................................................................B-9
B.3 Programming Sheets............................................................................................................B-13
Index
x DSP56303 DSP56301 User’s Manual
Figures
1-1 DSP56301 Block Diagram................................................................................... 1-11
2-1 Signals Identified by Functional Group ................................................................. 2-2
2-2 Host Interface/Port B Detail Signal Diagram......................................................... 2-3
3-1 Default Settings (0, 0, 0).........................................................................................3-7
3-2 16-Bit Space With Default RAM (0, 0, 1).............................................................. 3-8
3-3 Switched Program RAM (0, 1, 0)........................................................................... 3-9
3-4 16-Bit Space With Switched Program RAM (0, 1, 1).......................................... 3-10
3-5 Instruction Cache Enabled (1, 0, 0)...................................................................... 3-11
3-6 16-Bit Space With Instruction Cache Enabled (1, 0, 1)....................................... 3-12
3-7 Switched Program RAM and Instruction Cache Enabled (1, 1, 0) ...................... 3-13
3-8 16-Bit Space, Switched Program RAM, Instruction Cache Enabled (1, 1, 1) ..... 3-14
4-1 Status Register (SR) ............................................................................................... 4-7
4-2 Operating Mode Register (OMR)......................................................................... 4-12
4-4 Interrupt Priority Register-Peripherals (IPRP) (X:$FFFFFE).............................. 4-16
4-3 Interrupt Priority Register-Core (IPRC) (X:$FFFFFF)........................................ 4-16
4-5 PLL Control Register (PCTL)..............................................................................4-21
4-6 Bus Control Register (BCR)................................................................................. 4-22
4-7 DRAM Control Register (DCR)........................................................................... 4-24
4-8 Address Attribute Registers (AAR[0–3]) (X:$FFFFF9–$FFFFF6)..................... 4-27
4-9 DMA Control Register (DCR) ............................................................................. 4-29
4-10 Identification Register Configuration (Revision E) ............................................. 4-34
4-11 JTAG Identification (ID) Register Configuration................................................ 4-35
5-1 Memory Mapping of Peripherals Control Registers .............................................. 5-2
5-2 Host Interface/Port B Detail Signal Diagram......................................................... 5-5
5-3 Port C Signals......................................................................................................... 5-6
5-4 Port D Signals......................................................................................................... 5-6
5-5 Port E Signals.........................................................................................................5-6
5-6 Triple Timer Signals............................................................................................... 5-7
6-1 HI32 Block Diagram .............................................................................................. 6-5
6-2 Connection to a PCI Bus ...................................................................................... 6-19
6-3 Connection to 16-Bit ISA/EISA Data Bus........................................................... 6-20
6-4 Connection to the DSP56300 Core Port A Bus.................................................... 6-21
6-5 DSP Control Register (DCTR)............................................................................. 6-23
6-6 DSP PCI Control Register (DPCR)...................................................................... 6-26
6-7 DSP PCI Master Control Register (DPMC)......................................................... 6-30
DSP56301 User’s Manual xi
6-8 DSP PCI Address Register (DPAR).....................................................................6-33
6-9 DSP Status Register (DSR).................................................................................. 6-35
6-10 DSP PCI Status Register (DPSR)......................................................................... 6-38
6-11 DSP Host Port Direction Register (DIRH)........................................................... 6-43
6-12 DSP Host Port GPIO Data Register (DATH)....................................................... 6-43
6-13 Host Interface Control Register (HCTR) ............................................................. 6-48
6-14 Host Interface Status Register (HSTR) ................................................................ 6-56
6-15 Host Command Vector Register (HCVR)............................................................ 6-59
6-16 Device/Vendor ID Configuration Register (CDID/CVID) .................................. 6-64
6-17 Status/Command Configuration Register (CSTR/CCMR) .................................. 6-64
6-18 Class Code/Revision ID Configuration Register CCCR/CRID).......................... 6-67
6-19 Header Type/Latency Timer Configuration Register (CHTY/CLAT/CCLS)...... 6-68
6-20 Memory Space Base Address Configuration Register (CBMA).......................... 6-70
6-21 Subsystem ID and Subsystem Vendor ID Configuration Register (CSID).......... 6-71
6-22 Interrupt Line-Interrupt Pin Configuration Register(CILP)................................. 6-73
7-1 ESSI Block Diagram .............................................................................................. 7-1
7-2 ESSI Control Register A(CRA)............................................................................7-14
7-3 ESSI Clock Generator Functional Block Diagram............................................... 7-17
7-4 ESSI Frame Sync Generator Functional Block Diagram..................................... 7-17
7-5 ESSI Control Register B (CRB)........................................................................... 7-18
7-6 CRB FSL0 and FSL1 Bit Operation (FSR = 0).................................................... 7-24
7-7 CRB SYN Bit Operation...................................................................................... 7-25
7-8 CRB MOD Bit Operation..................................................................................... 7-26
7-9 Normal Mode, External Frame Sync (8 Bit, 1 Word in Frame)........................... 7-27
7-10 Network Mode, External Frame Sync (8 Bit, 2 Words in Frame) ....................... 7-27
7-11 ESSI Status Register (SSISR) .............................................................................. 7-28
7-12 ESSI Data Path Programming Model (SHFD = 0)............................................... 7-31
7-13 ESSI Data Path Programming Model (SHFD = 1)............................................... 7-32
7-14 ESSI Transmit Slot Mask Register A (TSMA).................................................... 7-33
7-15 ESSI Transmit Slot Mask Register B (TSMB).....................................................7-34
7-16 ESSI Receive Slot Mask Register A (RSMA) ..................................................... 7-35
7-17 ESSI Receive Slot Mask Register B (RSMB)...................................................... 7-35
7-18 Port Control Registers (PCRC X:$FFFFBF) (PCRD X:$FFFAF)....................... 7-36
7-19 Port Direction Registers (PRRC X:$FFFFBE) (PRRD X: $FFFFAE)................ 7-37
7-20 Port Data Registers (PDRC X:$FFFFBD) (PDRD X: $FFFFAD) ...................... 7-38
8-1 SCI Data Word Formats (SSFTD = 1), 1............................................................. 8-10
8-2 SCI Data Word Formats (SSFTD = 0), 2............................................................. 8-11
8-3 SCI Control Register (SCR)................................................................................. 8-12
xii DSP56301 User’s Manual
8-4 SCI Clock Control Register (SCCR).................................................................... 8-19
8-5 SCI Baud Rate Generator..................................................................................... 8-20
8-6 16 x Serial Clock..................................................................................................8-21
8-7 SCI Programming Model—Data Registers.......................................................... 8-22
8-8 Port E Control Register (PCRE X:$FFFF9F)....................................................... 8-24
8-9 Port E Direction Register (PRRE X:$FFFF9E).................................................... 8-25
8-10 Port Data Registers (PDRE X:$FFFF9D) ............................................................ 8-25
9-1 Triple Timer Module Block Diagram..................................................................... 9-2
9-2 Timer Module Block Diagram ............................................................................... 9-3
9-3 Timer Mode (TRM = 1) ......................................................................................... 9-7
9-4 Timer Mode (TRM = 0) ......................................................................................... 9-7
9-5 Pulse Mode (TRM = 1) .......................................................................................... 9-8
9-6 Pulse Mode (TRM = 0) .......................................................................................... 9-9
9-7 Toggle Mode, TRM = 1 ....................................................................................... 9-10
9-8 Toggle Mode, TRM = 0 ....................................................................................... 9-11
9-9 Event Counter Mode, TRM = 1............................................................................ 9-12
9-10 Event Counter Mode, TRM = 0............................................................................ 9-13
9-11 Pulse Width Measurement Mode, TRM = 1 ........................................................ 9-15
9-12 Pulse Width Measurement Mode, TRM = 0 ........................................................ 9-15
9-13 Period Measurement Mode, TRM = 1.................................................................. 9-16
9-14 Period Measurement Mode, TRM = 0.................................................................. 9-17
9-15 Capture Measurement Mode, TRM = 0 ............................................................... 9-18
9-16 Pulse Width Modulation Toggle Mode, TRM = 1............................................... 9-20
9-17 Pulse Width Modulation Toggle Mode, TRM = 0............................................... 9-21
9-18 Watchdog Pulse Mode.......................................................................................... 9-23
9-19 Watchdog Toggle Mode....................................................................................... 9-24
9-20 Timer Module Programmer’s Model.................................................................... 9-26
9-21 Timer Prescaler Load Register (TPLR)................................................................ 9-27
9-22 Timer Prescaler Count Register (TPCR).............................................................. 9-28
9-23 Timer Control/Status Register (TCSR)................................................................ 9-28
B-1 Status Register (SR) .............................................................................................B-13
B-2 Operating Mode Register (OMR).........................................................................B-14
B-3 Interrupt Priority Register Core (IPRC)...............................................................B-15
B-4 Interrupt Priority Register Peripherals (IPRP) .....................................................B-16
B-5 Phase-Locked Loop Control Register (PCTL).....................................................B-17
B-6 Bus Control Register (BCR).................................................................................B-18
B-7 DRAM Control Register (DCR)...........................................................................B-19
B-8 Address Attribute Registers (AAR[3–0]).............................................................B-20
DSP56301 User’s Manual xiii
B-9 DMA Control Registers 5–0 (DCR[5–0])............................................................B-21
B-10 DSP Control Register (DCTR).............................................................................B-22
B-11 DSP PCI Control Register (DPCR)......................................................................B-23
B-12 DSP PCI Master Control Register (DPMC).........................................................B-24
B-13 DSP PCI Address Register (DPAR).....................................................................B-25
B-14 HI32 Control Register (HCTR)............................................................................B-26
B-15 Host Command Vector Register (HCVR)............................................................B-27
B-16 Status/Command Configuration Register (CSTR/CCMR) ..................................B-28
B-17 Header Type/Latency Timer Configuration Register (CHTY/CLAT/CCLS)......B-29
B-18 Memory Space Base Address Configuration Register (CBMA)..........................B-30
B-19 Subsystem ID and Subsystem Vendor ID Configuration Register (CSID)..........B-31
B-20 ESSI Control Register A (CRA)...........................................................................B-32
B-21 ESSI Control Register B (CRB)...........................................................................B-33
B-22 ESSI Transmit and Receive Slot Mask Registers (TSM, RSM)..........................B-34
B-23 SCI Control Register (SCR).................................................................................B-35
B-24 SCI Clock Control Registers (SCCR)..................................................................B-36
B-25 Timer Prescaler Load Register (TPLR)................................................................B-37
B-26 Timer Control/Status Register (TCSR)................................................................B-38
B-27 Timer Load Registers (TLR)................................................................................B-39
B-28 Host Data Direction and Host Data Registers (HDDR, HDR).............................B-40
B-29 Port C Registers (PCRC, PRRC, PDRC).............................................................B-41
B-30 Port D Registers (PCRD, PRRD, PDRD) ............................................................B-42
B-31 Port E Registers (PCRE, PRRE, PDRE)..............................................................B-43
xiv DSP56301 User’s Manual
Tables
1-1 High True/Low True Signal Conventions ................................................................. 1-2
1-2 DSP56301 Switch Memory Configuration.............................................................. 1-10
1-3 DSP56301 Documentation ...................................................................................... 1-14
2-1 DSP56301 Functional Signal Groupings................................................................... 2-1
2-2 Power Inputs .............................................................................................................. 2-4
2-3 Ground Signals .......................................................................................................... 2-4
2-4 Clock Signals............................................................................................................. 2-5
2-5 Phase-Lock Loop Signals .......................................................................................... 2-5
2-6 External Address Bus Signals.................................................................................... 2-6
2-7 External Data Bus Signals ......................................................................................... 2-6
2-8 External Bus Control Signals..................................................................................... 2-6
2-9 Interrupt and Mode Control....................................................................................... 2-9
2-10 Host Interface........................................................................................................... 2-10
2-11 Summary of HI32 Signals and Modes..................................................................... 2-14
2-12 Host Port Pins (HI32) .............................................................................................. 2-16
2-13 Enhanced Synchronous Serial Interface 0 ............................................................... 2-23
2-14 Enhanced Serial Synchronous Interface 1 ............................................................... 2-25
2-15 Serial Communication Interface.............................................................................. 2-27
2-16 Triple Timer Signals................................................................................................ 2-28
2-17 JTAG/OnCE Interface ............................................................................................. 2-29
3-1 DSP56301 RAM Configurations............................................................................... 3-6
3-2 DSP56301 RAM Address Ranges by Configuration................................................. 3-6
4-1 DSP56301 Operating Modes ..................................................................................... 4-2
4-2 Operating Mode Definitions...................................................................................... 4-3
4-3 Status Register Bit Definitions .................................................................................4-7
4-4 Operating Mode Register (OMR) Bit Definitions................................................... 4-12
4-5 Interrupt Priority Level Bits..................................................................................... 4-17
4-6 Interrupt Sources...................................................................................................... 4-17
4-7 Interrupt Source Priorities Within an IPL................................................................ 4-19
4-8 PLL Control Register (PCTL) Bit Definitions ........................................................ 4-21
4-9 Bus Control Register (BCR) Bit Definitions........................................................... 4-22
4-10 DRAM Control Register (DCR) Bit Definitions..................................................... 4-25
4-11 Address Attribute Registers (AAR[0–3]) Bit Definitions ....................................... 4-27
4-12 DMA Control Register (DCR) Bit Definitions........................................................ 4-29
6-1 HI32 Features, Core-Side and Host-Side................................................................... 6-2
6-2 HI32 Features in PCI Mode and Universal Bus Mode.............................................. 6-3
6-3 HI32 (PCI Master Data Transfer Formats ................................................................. 6-8
6-4 Transmit Data Transfer Format ................................................................................. 6-9
6-5 Receive Transfer Data Formats ............................................................................... 6-10
6-6 HI32 Reset ............................................................................................................... 6-12
6-7 HI32 Modes ............................................................................................................. 6-13
6-8 Host Port Pin Functionality...................................................................................... 6-18
6-9 HI32 Programming Model, DSP Side ..................................................................... 6-22
Tables xv
6-10 DSP Control Register (DCTR) Bit Definitions ....................................................... 6-23
6-11 DSP PCI Control Register (DPCR) Bit Definitions ................................................ 6-27
6-12 DSP PCI Master Control Register (DMPC) Bit Definitions ................................... 6-31
6-13 DSP PCI Address Register (DPAR) Bit Definitions............................................... 6-33
6-14 DSP Status Register (DSR) Bit Definitions............................................................. 6-35
6-15 DSP PCI Status Register (DPSR) Bit Definitions................................................... 6-38
6-16 DATH and DIRH Functionality .............................................................................. 6-43
6-17 HI32 Programming Model, Host-Side Registers..................................................... 6-44
6-18 PCI Bus Commands................................................................................................. 6-46
6-19 Host-Side Registers (PCI Memory Address Space1)............................................... 6-47
6-20 Host-Side Registers (PCI Configuration Address Space1)...................................... 6-47
6-21 Host-Side Registers (Universal Bus Mode Address Space1)................................... 6-47
6-22 Host Interface Control Register (HCTR) Bit Definitions........................................ 6-49
6-23 Host Interface Status Register (HSTR) Bit Definitions........................................... 6-57
6-24 Host Command Vector Register (HCVR) Bit Definitions ...................................... 6-60
6-25 Device ID/Vendor ID Configuration Register (CDID/CVID) Bit Definitions........ 6-64
6-26 Status/Command Configuration Register (CSTR/CCMR) Bit Definitions............. 6-65
6-27 Class Code/Revision ID Configuration Register (CCCR/CRID) Bit Definitions... 6-67
6-28 Header Type/Latency Timer Configuration Register (CHTY/CLAT/CCLS)
Bit Definitions.......................................................................................................... 6-68
6-29 Memory Space Base Address Configuration Register (CBMA) Bit Definitions.... 6-70
6-30 Interrupt Line-Interrupt Pin Configuration Register(CILP) Bit Definitions .......... 6-73
7-1 ESSI Clock Sources................................................................................................... 7-3
7-2 Mode and Signal Definitions..................................................................................... 7-5
7-3 ESSI Control Register A (CRA) Bit Definitions..................................................... 7-15
7-4 ESSI Control Register B (CRB) Bit Definitions ..................................................... 7-19
7-5 ESSI Status Register (SSISR) Bit Definitions......................................................... 7-28
7-6 ESSI Port Signal Configurations ............................................................................. 7-37
8-1 SCI Registers After Reset.......................................................................................... 8-5
8-2 SCI Control Register (SCR) Bit Definitions............................................................ 8-12
8-3 SCI Status Register.................................................................................................. 8-17
8-4 SCI Status Register (SSR) Bit Definitions .............................................................. 8-17
8-5 SCI Clock Control Register (SCCR) Bit Definitions .............................................. 8-19
9-1 Timer Prescaler Load Register (TPLR) Bit Definitions.......................................... 9-27
9-2 Timer Prescaler Count Register (TPCR) Bit Definitions ........................................ 9-28
9-3 Timer Control/Status Register (TCSR) Bit Definitions........................................... 9-28
9-4 Inverter (INV) Bit Operation................................................................................... 9-32
B-1 Guide to Programming Sheets...................................................................................B-2
B-2 Internal I/O Memory Map (X Data Memory)............................................................B-3
B-3 Interrupt Sources........................................................................................................B-9
B-4 Interrupt Source Priorities Within an IPL................................................................B-11
xvi DSP56301 User’s Manual
Chapter 1
Overview
This manual describes the DSP56301 24-bit digital signal processor (DSP), its memory,
operating modes, and peripheral modules. The DSP56301 is an implementation of the
DSP56300 core with a unique configuration of on-chip memory, cache, and peripherals.
Use this manual in conjunction with the DSP56300 Family Manual (DSP56300FM/AD),
which describes the CPU, core programming models, and instruction set details. DSP56301
Technical Data (DSP56301/D)—referred to as the data sheet—provides electrical
specifications, timing, pinout, and packaging descriptions of the DSP56301. You can obtain
these documents, as well as Motorola’s DSP development tools, through a local Motorola
Semiconductor Sales Office or authorized distributor. To receive the latest information on this
DSP, access the Motorola DSP home page at the address given on the back cover of this
document.
1.1 Manual Organization
This manual contains the following chapters and appendices:
n Chapter 1, Overview Features list and block diagram, related documentation,
organization of this manual, and the notational conventions used.
n Chapter 2, Signals/Connections DSP56301 signals and their functional groupings.
n Chapter 3, Memory Maps DSP56301 memory spaces, RAM configuration, memory
configuration bit settings, memory sizes, and memory locations.
n Chapter 4, Core Configuration Registers for configuring the DSP56300 core when
programming the DSP56301—in particular, the interrupt vector locations and the
operation of the interrupt priority registers; operating modes and how they affect the
processor’s program and data memories.
n Chapter 5, Programming the Peripherals Guidelines on initializing the DSP56301
peripherals, including mapping control registers, specifying a method of transferring
data, and configuring for General-Purpose Input/Output (GPIO).
Overview 1-1
Manual Conventions
n Chapter 6, Host Interface (HI32) HI32 features, signals, architecture, programming
model, reset, interrupts, external host programming model, initialization, and a quick
reference to the HI32 programming model.
n Chapter 7, Enhanced Synchronous Serial Interface (ESSI) Enhancements, data and
control signals, programming model, operating modes, initialization, exceptions, and
GPIO.
n Chapter 8, Serial Communication Interface (SCI) Signals, programming model,
operating modes, reset, initialization, and GPIO.
n Chapter 9, Triple Timer Module Architecture, programming model, and operating
modes of three identical timer devices available for use as internals or event counters.
n Appendix A, Bootstrap Program Bootstrap code for the DSP56301.
n Appendix B, Programming Reference Peripheral addresses, interrupt addresses, and
interrupt priorities for the DSP56301; programming sheets list the contents of the
major DSP56301 registers for programmer’s reference.
1.2 Manual Conventions
This manual uses the following conventions:
n Bits within registers are always listed from most significant bit (MSB) to least
significant bit (LSB).
n Bits within a register are indicated AA[n–m], n > m, when more than one bit is
involved in a description. For purposes of description, the bits are presented as if they
are contiguous within a register. However, this is not always the case. Refer to the
programming model diagrams or to the programming sheets to see the exact location
of bits within a register.
n When a bit is described as “set,” its value is 1. When a bit is described as “cleared,” its
value is 0.
n The word “assert” means that a high true (active high) signal is pulled high to V
that a low true (active low) signal is pulled low to ground. The word “deassert” means
that a high true signal is pulled low to ground or that a low true signal is pulled high to
V
. See Table 1-1.
CC
Table 1-1. High True/Low True Signal Conventions
CC
or
Signal/Symbol Logic State Signal State Voltage
1
PIN
PIN False Deasserted
1-2 DSP56301 User’s Manual
True Asserted
Ground
V
CC
2
3
Manual Conventions
Table 1-1. High True/Low True Signal Conventions
Signal/Symbol Logic State Signal State Voltage
PIN True Asserted
PIN False Deasserted
1. PIN is a generic term for any pin on the chip.
2. Ground is an acceptable low voltage level. See the appropriate data sheet for the range of acceptable low
voltage levels (typically a TTL logic low).
3. V
n Pins or signals that are asserted low (made active when pulled to ground) are indicated
is an acceptable high voltage level. See the appropriate data sheet for the range of acceptable high
CC
voltage levels (typically a TTL logic high).
V
CC
Ground
3
2
like this:
— In text, they have an overbar: for example,
RESET is asserted low.
— In code examples, they have a tilde in front of their names. In Example 1-1, line 3
refers to the
n Sets of signals are indicated by the first and last signals in the set, for instance HA[0–2].
n “Input/Output” indicates a bidirectional signal. “Input or Output” indicates a signal
SS0 signal (shown as ~SS0).
that is exclusively one or the other.
n Code examples are displayed in a monospaced font, as shown in Example 1-1.
Example 1-1. Sample Code Listing
BFSET #$0007,X:PC C ; Con figure : line 1
; MISO0, MOSI0, SCK0 for SPI master line 2
; ~SS0 as PC3 for GPIO line 3
n Hexadecimal values are indicated with a dollar sign ($) preceding the value. For
example, $FFFFFF is the X memory address for the core interrupt priority register.
n The word “reset” appears in four different contexts in this manual:
— the reset signal, written as
RESET
— the reset instruction, written as RESET
— the reset operating state, written as Reset
— the reset function, written as reset
Overview 1-3
DSP56300 Core Features
1.3 DSP56300 Core Features
All DSP56300 core family members contain the DSP56300 core and additional modules. The
modules are chosen from a library of standard predesigned elements, such as memories and
peripherals. New modules can be added to the library to meet customer specifications. A
standard interface between the DSP56300 core and the on-chip memory and peripherals
supports a wide variety of memory and peripheral configurations. In particular, the DSP56301
includes Motorola’s JTAG port and OnCE module. Core features are fully described in the
DSP56300 Family Manual. This manual, in contrast, documents pinout, memory, and
peripheral features. Core features are as follows:
n 80/100 Million Instructions per Second (MIPS) using an internal 80/100 MHz clock at
3.0–3.6 V, depending on the revision of the DSP56301
n Object code compatible with the DSP56000 core
n Highly parallel instruction set
n Data Arithmetic Logic Unit (Data ALU)
— Fully pipelined 24 x 24-bit parallel multiplier-accumulator (MAC)
— 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and
parsing)
— Conditional ALU instructions
— 24-bit or 16-bit arithmetic support under software control
n Program Control Unit (PCU)
— Position Independent Code (PIC) support
— Addressing modes optimized for DSP applications (including immediate offsets)
— On-chip instruction cache controller
— On-chip memory-expandable hardware stack
— Nested hardware DO loops
— Fast auto-return interrupts
n Direct Memory Access (DMA) Controller
— Six DMA channels supporting internal and external accesses
— One-, two-, and three- dimensional transfers (including circular buffering)
— End-of-block-transfer interrupts
— Triggering from interrupt lines and all peripherals
1-4 DSP56301 User’s Manual
DSP56300 Core Features
n Phase Lock Loop (PLL)—Allows change of low power Divide Factor (DF) without
loss of lock
n Output clock with skew elimination
n Hardware debugging support
— On-Chip Emulation (OnCE) module
— Joint Action Test Group (JTAG) Test Access Port (TAP) port
— Address Trace mode reflects internal Program RAM accesses at the external port
n On-chip memories:
— Program RAM, instruction cache, X data RAM, and Y data RAM sizes are
programmable:
Program RAM
Size
4096 × 24-bit 0 2048 × 24-bit 2048 × 24-bit disabled
3072 × 24-bit 1024 × 24-bit 2048 × 24-bit 2048 × 24-bit enabled
2048 × 24-bit 0 3072 × 24-bit 3072 × 24-bit disabled
1024 × 24-bit 1024 × 24-bit 3072 × 24-bit 3072 × 24-bit enabled
1. Controlled by the Cache Enable (CE) bit in the Status Register (SR)
2. Controlled by the Memory Select (MS) bit in the Operating Mode Register (OMR)
Instruction
Cache Size
X Data RAM
Size
Y Data RAM
Size
Instruction
Cache
(CE = 0)
(CE = 1)
(CE = 0)
(CE = 1)
1
Switch
2
Mode
disabled
(MS = 0)
disabled
(MS = 0)
enabled
(MS = 1)
enabled
(MS = 1)
— 192 or 3 K × 24-bit bootstrap ROM, depending on the DSP56301 revision
n Off-chip memory expansion:
— Data memory expansion to two 16 M × 24-bit word memory spaces in 24-Bit mode
or two 64 K × 16-bit memory spaces in Sixteen-Bit Compatibility mode
— Program memory expansion to one 16 M × 24-bit words memory space in
24-Bit mode or 64 K × 16-bit in Sixteen-Bit Compatibility mode
— External memory expansion port
— Chip Select Logic for glueless interface to SRAMs
— On-chip DRAM Controller for glueless interface to DRAMs
n On-chip peripheral support:
— 32-bit parallel PCI/Universal Host Interface (HI32), PCI Rev. 2.1 compliant with
glueless interface to other DSP563xx buses
— ISA interface requires only 74LS45-style buffer
— Two Enhanced Synchronous Serial Interfaces (ESSI0 and ESSI1)
Overview 1-5
DSP56300 Core Functional Blocks
— Serial Communications Interface (SCI) with baud rate generator
— Triple timer module
— Up to forty-two programmable General Purpose Input/Output (GPIO) pins,
depending on which peripherals are enabled
n Reduced power dissipation
— Very low power CMOS design
— Wait and Stop low-power standby modes
— Fully-static logic
— Optimized power management circuitry (instruction-dependent,
peripheral-dependent, and mode-dependent)
1.4 DSP56300 Core Functional Blocks
The functional blocks of the DSP56300 core are as follows:
n Data arithmetic logic unit (ALU)
n Address generation unit
n Program control unit
n PLL and clock oscillator
n JTAG TAP and OnCE module
In addition, the DSP56301 provides a set of on-chip peripherals, discussed in Section 1.7,
Peripherals, on page 1-12.
1.4.1 Data ALU
The data ALU performs all the arithmetic and logical operations on data operands in the
DSP56300 core. These are the components of the data ALU:
n Fully pipelined 24 × 24-bit parallel multiplier-accumulator
n Bit field unit, comprising a 56-bit parallel barrel shifter (fast shift and normalization;
bit stream generation and parsing)
n Conditional ALU instructions
n Software-controllable 24-bit or 16-bit arithmetic support
n Four 24-bit input general-purpose registers: X1, X0, Y1, and Y0
n Six data ALU registers (A2, A1, A0, B2, B1, and B0) that are concatenated into two
general-purpose, 56-bit accumulators, A and B, accumulator shifters
n Two data bus shifter/limiter circuits
1-6 DSP56301 User’s Manual
DSP56300 Core Functional Blocks
1.4.1.1 Data ALU Registers
The data ALU registers are read or written over the X data bus and the Y data bus as 16- or
24-bit operands. The source operands for the data ALU can be 24, 48, or 56 bits in 24-bit
mode or 16, 32, or 40 bits in 16-bit mode. They always originate from data ALU registers.
The results of all data ALU operations are stored in an accumulator. Data ALU operations are
performed in two clock cycles in a pipeline so that a new instruction can be initiated in every
clock cycle, yielding an effective execution rate of one instruction per clock cycle.
1.4.1.2 Multiplier-Accumulator (MAC)
The MAC unit comprises the main arithmetic processing unit of the DSP56300 core and
performs all of the calculations on data operands. For arithmetic instructions, the unit accepts
as many as three input operands and outputs one 56-bit result of the following form:
extension:most significant product:least significant product (EXT:MSP:LSP).
The multiplier executes 24-bit × 24-bit parallel, fractional multiplies between
twos-complement signed, unsigned, or mixed operands. The 48-bit product is right-justified
and added to the 56-bit contents of either the A or B accumulator. A 56-bit result can be
stored as a 24-bit operand. The LSP is either truncated or rounded into the MSP. Rounding is
performed if specified.
1.4.2 Address Generation Unit (AGU)
The AGU performs the effective address calculations using integer arithmetic necessary to
address data operands in memory and contains the registers that generate the addresses. It
implements four types of arithmetic: linear, modulo, multiple wrap-around modulo, and
reverse-carry. The AGU operates in parallel with other chip resources to minimize
address-generation overhead.
The AGU is divided into halves, each with its own identical address ALU. Each address ALU
has four sets of register triplets, and each register triplet includes an address register, offset
register, and modifier register. Each contains a 24-bit full adder (called an offset adder). A
second full adder (called a modulo adder) adds the summed result of the first full adder to a
modulo value that is stored in its respective modifier register. A third full adder (called a
reverse-carry adder) is also provided. The offset adder and the reverse-carry adder work in
parallel and share common inputs. The only difference between them is that the carry
operation propagates in opposite directions. Test logic determines which of the three summed
results of the full adders is output.
Each address ALU can update one address register from its own address register file during
one instruction cycle. The contents of the associated modifier register specify the type of
Overview 1-7
DSP56300 Core Functional Blocks
arithmetic used in the address register update calculation. The modifier value is decoded in
the address ALU.
1.4.3 Program Control Unit (PCU)
The PCU prefetches and decodes instructions, controls hardware DO loops, and processes
exceptions. Its seven-stage pipeline controls the different processing states of the DSP56300
core. The PCU consists of three hardware blocks:
n Program decode controller — decodes the 24-bit instruction loaded into the instruction
latch and generates all signals necessary for pipeline control.
n Program address generator — contains all the hardware needed for program address
generation, system stack, and loop control.
n Program interrupt controller — arbitrates among all interrupt requests (internal
interrupts, as well as the five external requests
generates the appropriate interrupt vector address.
IRQA, IRQB, IRQC, IRQD, and NMI), and
PCU features include the following:
n Position-independent code support
n Addressing modes optimized for DSP applications (including immediate offsets)
n On-chip instruction cache controller
n On-chip memory-expandable hardware stack
n Nested hardware DO loops
n Fast auto-return interrupts
n Hardware system stack
The PCU uses the following registers:
n Program counter register
n Status register
n Loop address register
n Loop counter register
n Vector base address register
n Size register
n Stack pointer
n Operating mode register
n Stack counter register
1-8 DSP56301 User’s Manual
DSP56300 Core Functional Blocks
1.4.4 PLL and Clock Oscillator
The clock generator in the DSP56300 core comprises two main blocks: the PLL, which
performs clock input division, frequency multiplication, and skew elimination; and the clock
generator, which performs low-power division and clock pulse generation. These features
allow you to:
n Change the low-power divide factor without losing the lock
n Output a clock with skew elimination
The PLL allows the processor to operate at a high internal clock frequency using a
low-frequency clock input, a feature that offers two immediate benefits:
n A lower-frequency clock input reduces the overall electromagnetic interference
generated by a system.
n The ability to oscillate at different frequencies reduces costs by eliminating the need to
add additional oscillators to a system.
1.4.5 JTAG TAP and OnCE Module
In the DSP56300 core is a dedicated user-accessible TAP that is fully compatible with the
.
IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture
testing high-density circuit boards led to the development of this standard under the
sponsorship of the Test Technology Committee of IEEE and the JTAG. The DSP56300 core
implementation supports circuit-board test strategies based on this standard. The test logic
includes a TAP with four dedicated signals, a 16-state controller, and three test data registers.
A boundary scan register links all device signals into a single shift register. The test logic,
implemented utilizing static logic design, is independent of the device system logic. For
details on the JTAG port, consult the DSP56300 Family Manual.
The OnCE module interacts with the DSP56300 core and its peripherals nonintrusively so that
you can examine registers, memory, or on-chip peripherals. This facilitates hardware and
software development on the DSP56300 core processor. OnCE module functions are
provided through the JTAG TAP signals. For details on the OnCE module, consult the
DSP56300 Family Manual.
Problems with
Overview 1-9
Internal Buses
1.4.6 On-Chip Memory
The memory space of the DSP56300 core is partitioned into program, X data, and Y data
memory space. The data memory space is divided into X and Y data memory in order to work
with the two address ALUs and to feed two operands simultaneously to the data ALU.
Memory space includes internal RAM and ROM and can be expanded off-chip under
software control. There is an on-chip 192/3K x 24-bit bootstrap ROM. For details on internal
memory, see Chapter 3, Memory Configuration. Program RAM, instruction cache, X data
RAM, and Y data RAM size are programmable, as Table 1-2 shows.
Table 1-2. DSP56301 Switch Memory Co nfiguration
Program
RAM Size
4096 × 24-bit 0 2048 × 24-bit 2048 × 24-bit disabled ( CE = 0) disabled (MS = 0)
3072 × 24-bit 1024 × 24-bit 2048 × 24-bit 2048 × 24-bit enabled (CE = 1) disabled (MS = 0)
2048 × 24-bit 0 3072 × 24-bit 3072 × 24-bit disabled (CE = 0) enabled (MS = 1)
1024 × 24-bit 1024 × 24-bit 3072 × 24-bit 3072 × 24-bit enabled (CE = 1) enabled (MS = 1)
1. Controlled by the Cache Enable (CE) bit in the Status Register (SR)
2. Controlled by the Memory Select (MS) bit in the Operating Mode Register (OMR)
Instruction
Cache Size
X Data RAM
Size
Y Data RAM
Size
Instruction Cache
1
Switch Mode
1.5 Internal Buses
All internal buses on the DSP56300 devices are 24-bit buses. To provide data exchange
between the blocks, the DSP56301 implements the following buses:
n Peripheral I/O expansion bus to peripherals
n X memory expansion bus to X memory
n Y memory expansion bus to Y memory
n Program data bus for carrying program data throughout the core
2
n X memory data bus for carrying X data throughout the core
n Y memory data bus for carrying Y data throughout the core
n Program address bus for carrying program memory addresses throughout the core
n X memory address bus for carrying X memory addresses throughout the core
n Y memory address bus for carrying Y memory addresses throughout the core.
1-10 DSP56301 User’s Manual
The block diagram in Figure 1-1 illustrates these buses among other components.
652
EXTAL
XTAL
Triple
Timer
Address
Generation
Unit
Six Channel
DMA Unit
Boot-
strap
ROM
Internal
Data
Bus
Switch
Clock
Generator
PLL
Host
Interface
(HI32)
Program
Interrupt
Controller
6
ESSI
Peripheral
Expansion Area
PIO_EB
3
SCI
Program
Decode
Controller
Memory Expansion Area
Program RAM
4096
(Default)
DSP56300
DDB
YDB
XDB
PDB
GDB
Program
Address
Generator
X Data
× 24
RAM
2048
× 24
(Default)
PM_EB
YAB
XM_EB
XAB
PAB
DAB
24-Bit
Core
Data ALU
× 24
+
MAC
24
Two 56-bit Accumulators
56-bit Barrel Shifter
Y Data
RAM
× 24
2048
(Default)
YM_EB
56 → 56-bit
External
Address
Bus
Switch
External
Bus
Interface
and
I - Cache
Control
External
Data Bus
Switch
Power
Management
JTAG
OnCE™
DMA
24
ADDRESS
14
CONTROL
24
DA T A
5
DE
2
RESET
PINIT/NMI
MODD/IRQA
MODC/
IRQB
MODB/IRQC
MODA/IRQD
Figure 1-1. DSP56301 Block Diagram
1.6 DMA
The DMA block has the following features:
n Six DMA channels supporting internal and external accesses
n One-, two-, and three-dimensional transfers (including circular buffering)
n End-of-block-transfer interrupts
n Triggering from interrupt lines and all peripherals
Overview 1-11
Peripherals
1.7 Peripherals
In addition to the core features, the DSP56301 provides the following peripherals:
n As many as 42 user-configurable General-Purpose Input/Output (GPIO) signals
n Host Interface (HI32)
n Dual Enhanced Synchronous Serial Interfaces (ESSI0 and ESSI1)
n Serial Communications Interface (SCI)
n Triple timer module
1.7.1 General-Purpose Input/O utput (GPIO ) signals
The GPIO port consists of as many as 42 programmable signals, all of which are also used by
the peripherals (HI32, ESSI, SCI, and timer). There are no dedicated GPIO signals. After a
reset, the signals are automatically configured as GPIO. Three memory-mapped registers per
peripheral control GPIO functionality. Programming techniques for these registers to control
GPIO functionality are detailed in Chapter 5, Programming the Peripherals.
1.7.2 Host Interface (HI32)
The Host Interface (HI32) is a fast parallel host port up to 32 bits wide that can directly
connect to the host bus. The HI32 supports a variety of standard buses and provides glueless
connection with a number of industry-standard microcomputers, microprocessors, DSPs, and
DMA controllers. In one of its modes of operation, PCI mode, the HI32 is a dedicated
bidirectional target (slave) / initiator (master) parallel port with a 32-bit wide data path up to
eight words deep. The HI32 can connect directly to the PCI bus.
1.7.3 Enhance Synchronous Serial Interface (ESSI)
The DSP56301 provides two independent and identical ESSIs. Each ESSI has a full-duplex
serial port for communication with a variety of serial devices, including one or more
industry-standard CODECs, other DSPs, microprocessors, and peripherals that implement the
Motorola Serial Peripheral Interface (SPI). The ESSI consists of independent transmitter and
receiver sections and a common ESSI clock generator. ESSI capabilities include:
n Independent (asynchronous) or shared (synchronous) transmit and receive sections
with separate or shared internal/external clocks and frame syncs
n Normal mode operation using frame sync
n Network mode operation with as many as 32 time slots
n Programmable word length (8, 12, 16, 24, or 32 bits)
n Program options for frame synchronization and clock generation
n One receiver and three transmitters per ESSI
1-12 DSP56301 User’s Manual
Peripherals
1.7.4 Serial Communications Interface (SCI)
The SCI provides a full-duplex port for serial communications with other DSPs,
microprocessors, or peripherals such as modems. The SCI interfaces without additional logic
to peripherals that use TTL-level signals. With a small amount of additional logic, the SCI can
connect to peripheral interfaces that have non-TTL level signals, such as the RS-232C,
RS-422, and so forth. This interface uses three dedicated signals: transmit data, receive data,
and SCI serial clock. It supports industry-standard asynchronous bit rates and protocols, as
well as high-speed synchronous data transmission (up to 12.5 Mbps for a 100 MHz clock).
SCI asynchronous protocols include a multidrop mode for master/slave operation with
wakeup on idle line and wakeup on address bit capability. This mode allows the DSP56301 to
share a single serial line efficiently with other peripherals.
Separate SCI transmit and receive sections can operate asynchronously with respect to each
other. A programmable baud-rate generator provides the transmit and receive clocks. An
enable vector and an interrupt vector allow the baud-rate generator to function as a
general-purpose timer when the SCI is not using it or when the interrupt timing is the same as
that used by the SCI.
1.7.5 Triple Timer Module
The triple timer module is composed of a common 21-bit prescaler and three independent and
identical general-purpose 24-bit timer/event counters, each with its own memory-mapped
register set. Each timer has the following properties:
n A single signal that can function as a GPIO signal or as a timer signal
n Uses internal or external clocking and can interrupt the DSP after a specified number
of events (clocks) or signal an external device after counting internal events
n Connects to the external world through one bidirectional signal. When this signal is
configured as an input, the timer functions as an external event counter or measures the
external pulse width/signal period. When the signal is used as an output, the timer
functions as either a timer, a watchdog, or a pulse width modulator.
Overview 1-13
Related Documents and Web Sites
1.8 Related Documents and Web Sites
The documents listed in Table 1-3 are required for a complete description of the DSP56301
and are necessary to design properly with the part. Documentation is available from the
following sources (see back cover for detailed information):
n A local Motorola distributor
n A Motorola semiconductor sales office
n A Motorola Literature Distribution Center
n The World Wide Web (WWW)
Table 1-3. DSP 56301 Documentation
Name Description Order Number
DSP56300 Family
Manual
DSP56301 User’s
Manual
(this manual)
DSP56301
Technical Data
Detailed description of the DSP56300 family processor core and
instruction set
Detailed functional description of the DSP56301 memory
configuration, operation, and register programming
DSP56301 features list and physical, electrical, timing, and package
specifications
DSP56300FM/AD
DSP56301UM/AD
DSP56301/D
You can download these documents and other related documentation (all in pdf format)
referenced by the product page at:
http://www.mot.com/SPS/DSP/
For printed copies, contact the Literature Distribution Center at the number(s) provided on the
back cover of this manual.
1-14 DSP56301 User’s Manual
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