MOTOROLA DSP56156 Technical data

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TECHNICAL DATA

DSP56156 DSP56156ROM

Advance Information

16-bit Digital Signal Processor

The DSP56156 is a general-purpose MPU-style Digital Signal Processor (DSP). On a single semiconductor chip, the DSP56156 comprises a very efficient 16-bit digital signal processing core, program and data memories, a number of peripherals, and system support ci rc uitry. Unique features

of the DSP56156 include a built-in sigma-delta (²ý) codec and phase-locked loop (PLL). This combination of featur es makes the DSP56156 a cost-ef fective, high-perf ormance solution for many DSP applications, especially speech coding, digital communications, and cellular base stations.

The central processing unit of the DSP56156 is the DSP56100 core processor. Like all DSP56100based DSPs, the DSP56156 consists of three execution units operating in parallel, allowing up to six operations to be performed during each instruct ion cycle. This parallelism gr eatly incr eases the effective processing speed of the DSP56156. The MPU-style programming model and instruction set allow straightforward ge neration of ef fici ent, compa ct code. The ba sic ar c hitectur es a nd devel opment tools of Motorola's 16-bit, 24-bit , and 32-bit DSPs are so similar that understanding how to design and program one greatly reduces the time needed to learn the others.

On-Chip Emulation (OnCE ities normally available only through expensive external hardware. Development costs are reduced and in-field testing is greatly simplified using the OnCE DSP56156 in detail.

Sigma-

Delta

Codec

16-bit

Timer/

Event

Counter

16-bit

56100 DSP

Core

Internal

Data

Bus

Switch

port) circuitry provi des convenient and inexpensive debug fa cil-

port. Figure 1 illustrates the

5 15 2

Sync.

Serial

(SSI)

or I/O

Address

Generation

Unit

Sync.

Serial

(SSI)

or I/O

Host

Interface

(HI)

or I/O

Program

Memory *

2048 × 16 RAM

64 × 16 ROM

(boot)

PAB

XAB1 XAB2

GDB

PDB XDB

Memory

2048 × 16 RAM

16-bit Bus

Data

External Address

Bus

Switch

External

Data

Bus

Switch

Address

Data

OnCE™ Port

Clock

PLL

Gen.

Interrupt

Control

IRQ 2

Program

Decode

Controller

Program Control Unit

Program Address

Generator

Figure 1 DSP56156 Block Diagram

Specifications and information herein are subject to change without notice. OnCE is a trademark of Motorola, Inc.

 MOTOROLA INC., 1994

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16 x 16 + 40 —> 40-bit MAC

Data ALU

Two 40-bit Accumulators

* 12 k x 16 ROM replaces the program RAM on the DSP56156ROM

Bus

Control

Introduction

DSP56156 Features

Digital Signal Processing Core

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• Efficient, object code compatible, 16-bit 56100-Family DSP engine — Up to 30 Million Instructions Per Second (MIPS) – 33 ns instruction cycle at 60 MHz

— Up to 180 Million Operations Per Second ( MOPS) at 60 M Hz — Highly parallel instruction set wit h unique DSP a ddressing modes — Two 40-bit accumulators i ncludi n g exte nsion b yte — Parallel 16 × 16- bi t m u lti ply- ac cumul ate in 1 instruction cycle (2 clock cycle s) — Double precision 32 × 3 2-b it mult iply with 72-bit result in 6 i nstruc tion c yc les — Least Mean Square (LMS) adaptive loop filter in 2 instructions — 40-bit Addition/Subtraction in 1 in struct ion c ycl e — Fractional and integer arithmetic with support fo r multiprecision arithmetic — Hardware support for block-floating poi nt FFT — Hardware-nested DO loops including infinit e l oops — Zero-overhead fast interrupts (2 instruction cycles) — Three 16-bit internal data buses and three 16-bit internal address buses for

maximum information tr ansf er on - chip

• On-chip Harvard architecture permitting simultaneous accesses to program

and memories

• 2048 × 16-bit on-chip program RAM and 64 × 16-bit bootstrap ROM

(or 12 k × 16-bit on-chip program ROM on the DSP56156ROM)

• 2048 × 16-bit on-chip data RAM

• External memory expansion with 16-bit address and data buses

• Bootstrap loading from external data bus, Host Interface, or

Synchronous Serial Interface

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2 DSP56156 Data Sheet MOTOROLA

Peripheral and Support Circuits

• Byte-wide Host Interface (HI) with Direct Memory Access support

• Two Synchronous Serial Interfaces (SSI) to communicate with codecs and

synchronous serial devices

— Built in µ-law and A-law compression/expansion — Up to 32 software-selectable ti me s lots in net wo rk mode

• 16-bit Timer/Event Counter also generates and measures digital waveforms

• On-chip sigma-delta voice band Codec: — Sampling clock rates bet we en 100 kHz and 3 MHz

— Four software-programmable decimation/interpolation ratios

— Internal voltage reference ( — No external components required

/5 of positive power supp ly)

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• On-chip peripheral registers memory mapped in data memory space

• Double buffered peripherals

• Up to 27 general purpose I/O pins

• Two external interrupt request pins

• On-Chip Emulation (OnCE™) port for unobtrusive, processor speed-independent debugging

• Software-programmable, Phase-Locked Loop-based (PLL) f requency synthesizer for the core clock

DSP56156 Features

Miscellaneous Features

• Power-saving Wait and Stop modes

Introduction

Documentation

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• Fully static, HCMOS design for operating frequencies from 40 or 60 MHz down to DC

• 112-pin Ceramic Quad Flat Pack (CQFP) surface-mount package; 20 × 20 × 3 mm

• 112-pin Plastic Thin Quad Flat Pack (TQFP) surface-mount package; 20 × 20 × 1.5 mm

• 5 V power supply

Product Documentation

This data sheet plus the two manuals listed in Table 1 are required for a complete DSP56156 description and are necessary to properly design with the part. Documentation is available from a local Motorola distributor, a semiconductor sales office, or through a Motorola Literature Distribution Center.

Table 1 DSP56156 Documentation

Topic Description Order Number

DSP56100 Family Manual Detailed description of the 56000-

family architecture and the 16-bit core processor and instruction set

DSP56100FAMUM/AD

DSP56156 User’s Manual Detailed description of memory,

peripherals, and interfaces

DSP56156 Data Sheet Pin and package descriptions, and

electrical and timing specifications

MOTOROLA DSP56156 Data Sheet 3

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DSP56156UM/AD

DSP56156/D

Introduction

Documentation Data Sheet Contents

Pin Groupings

The DSP56156 is available in a 112-pin Cerami c Quad Flat P ack ( CQFP ) and a 112- pin Pla stic Thin Quad Flat Pack (TQFP). The input and output signals are organized into the functional groups indicated in Table 3. Figure 2 illustrates the chip’s pin functions.

Table 3 Functional Pin Groupings

Functional Group Number of Pins

Address 16

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Data Bus 16

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Bus Control 9 Host Interface (HI) 15 Synchronous Serial Interfaces (SSI) 10 Timer Interface 2 Interrupt and Mode Control 4 Phase-Locked Loop (PLL) and Clock 3

On-Chip Emulation (OnCE On-Chip Codec 7 Power (V Ground (GND) 16 Total 112

NOTE: OVERBARS are used throughout this document to indicate a signal which is at Ground voltage (typi-

cally a TTL logic low — V V

voltage (typically a TTL logic high — VIH or VOH) when the function is logically false.

)10

or VOL) when the function is logically true. These signals are, likewise, at

Port) 4

MOTOROLA DSP56156 Data Sheet 5

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Introduction

Pin Functions

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A0-A15

D0-D15

PS/DS

R/W

MODA/IRQA MODB/IRQB

MODC

RESET

DSO

DSI/OS0

DSCK/OS1

MIC

AUX

SPKP

SPKM

BIAS

VREF

VDIV

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DSP56156

H0-H7* HA0-HA2* HR/W* HEN* HREQ* HACK*

STD0* SRD0* SCK0* SC00-SC10*

STD1* SRD1* SCK1* SC01-SC11*

TIN* TOUT*

EXTAL CLKO SXFC

V GND

External Bus

Interrupt/ Mode Control

On-Chip Emulator (OnCE) Port

On-Chip Codec

Host

Interface (HI)

Two

Synchronous

Serial

Interfaces

(SSI)

Timer/Event

Counter

Clock

and

Phase-locked

Loop

(PLL)

112 pins

* These pins have an alternate function of general purpose input/output.

Figure 2 DSP56156 Pin Functions

6 DSP56156 Data Sheet MOTOROLA

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Pin Descriptions

Address and Data Bus

Bus Control

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Pin Descriptions

Address and Data Bus

A0-A15 (Address Bus) — three-state, active

high outputs. A0-A15 change in t0 and specify the address for external program and data memory accesses. If there is no external bus activity, A0-A15 remain at their previous values. A0-A15 are three-stated during hardware reset.

D0-D15 (Data Bus) — three-state, active

high, bidirectional input/outputs.

Read data is sampled on the trailing edge of t2, while write data o utput is enabled by the leading edge of t2 and three-stated at the leading edge of t0. If there is no externa l bus activity, D0-D15 are three-stated. D0-D15 are also threestated during hardware reset.

Bus Control

PS/DS (Program/Data Memory Select) —

three-state, active low output. This out-

put is asserted only when external data memory is referenced. PS/DS the same for the A0-A15 address lines.

is high for program memory ac-

PS/DS cess and is low for data memory access. If the external bus is not used during an instruction cycle (t0, t1, t2, t3), PS/DS high in t0. PS/DS ance state during hardware reset.

(Read/Write) — three-state, active

R/W

low output. Timing is the same as the

address lines, providing an “early write” signal. R/W t0) is high for a read access and is low for a write access. If the external bus is not used during an instruction cycle

is in the high imped-

(which changes in

timing is

goes

(t0, t1, t2, t3), R/W is three-stated during hardware reset.

(Write Enable) — three-st ate, active

low output. This output is asserted during external memory write cycles. When

is asserted in t1, the data bus pins

WR D0-D15 become outputs and the DSP puts data on the bus during the leading edge of t2. When WR the external data has been latched inside the external device. When WR ed, it qualifies the A0-A15 and PS/DS pins. WR can be connected directly to the WE stated during hardware reset or when the DSP is not bus master.

(Read Enable) — three-st ate, active

low output. This output is asserted

during external memory read cycles. When RD the data bus pins D0-D15 become inputs and an external device is enabled onto the data bus. When RD serted in t3, the external data is latched inside the DSP. When RD qualifies the A0-A15 and PS/DS RD OE three-stated during hardware reset or when the DSP is not bus master.

(Bus Strobe) — three-state, active

low output. Asserted at the start of a

bus cycle (during t0) and deasserted at the end of the bus cycle (during t2).

This pin provides an “early bus start” signal which can be used as address latch and as an “e arly bus end” signa l which can be used by an external bus controller. BS hardware reset.

pin of a static RAM. WR is three-

is asserted in late t0/early t1,

can be connected directly to the

pin of a stat ic RA M or ROM. RD is

goes high in t0. R/W

is deasserted in t3,

is asserted, it

is three-stated during

is assert-

is deas-

pins.

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Pin Descriptions

Bus Control

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TA (Transfer Acknowledge) — active

low input. If there is no external bus ac-

tivity, the TA DSP. When there is external bus cycle activity, TA states in the external bus cycle. TA sampled on the leading edge of the clock. Any numb er of wait stat es f rom 1 to infinity may be inserted by using TA

is sampled high on the leading

If TA edge of the clock beginning the bus cycle, the bus cycle will end 2T after the

has been sampled low on a leading

TA edge of the clock; if the Bus Control Register (BCR) value does not program more wait states. The number of wait states is determined by the TA by the Bus Control Register (BCR), whichever is longer. TA during the leading edge of the clock when wait states are controlled by the BCR value. In that case, TA be sampled low during the leading edge of the last period of the bus cycle programmed by the BCR (2T before the end of the bus cycle programmed by the BCR) in order not to add any wait states.

should always be deasserted during

CLKO

input is ignored by the

can be used to insert wait

is still sampled

will have to

T1 T2

input or

T3 T0

t3 to be sampled high by the leading edge of T0. If TA ed) at the leading edge of the t0 beginning the bus cycle, and if no wait states are specified in the BCR register, zero wait states will be i nserte d in the external bus cycle, regardless the status of

during the leading edge of T2.

(Bus Request) — active low output

when in master mode, active low input when in slave mode. After power-

on reset, this pin is an input (slave mode). In this mode, the bus request

allows another device such as a pro-

BR cessor or DMA controller to become the master of the DSP external data bus D0-D15 and external address bus A0-A15. The DSP asserts BG states after the BR The DSP bus controller releases control of the external data bus D0-D15, address bus A0-A15 and bus control pins PS/DS est time possible consistent w ith proper synchronization. These pins are then placed in the high impedance state and

T3 T0

, RD, WR, and R/W at the earli-

is sampled low (assert-

input is asserted.

Tw T2

a few T

CLKO

T1 T2

Tw T2

T3 T0

Tw T2

T3 T0

Figure 3 TA Controlled Accesses

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Pin Descriptions

Bus Control

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the BB pin is deasserted. The DSP continues executing instructions only if internal program and data memory resources are accessed. If the DSP requests the external bus while BR pin is asserted, the DSP bus controller inserts wait states until the external bus becomes available (BR serted). Note that interrupts are not serviced when a DSP instruction is waiting for the bus controller. Note also that BR rupting the execution of a read/ modify/write instruction.

If the master bit in the OMR register is set, this pin becomes an output (Master Mode). In this mode, the DSP is not the external bus master and has to assert

to request the bus mastership. The

BR DSP bus controller will insert wait states until BG will then begin normal bus accesses after the rising of the clock which sampled BB remain asserted until the DSP no longer needs the bus. In this mode, the Request Hold bit (RH) of the Bus Control Register (BCR) allows BR under software control.

During external accesses caused by an instruction executed out of external program memory, BR for consecutive external X memory accesses and continues toggling for consecutive external P memory accesses unless the Request Hold bit (RH) is set inside the Bus Control Register (BCR).

In the master mode, BR used for non arbitration purpose: if BG is always asserted, BR is asserted in t0 of every external bus access. It can then be used as a chip select to turn a exter-

is prevented from inter-

input is asserted and

high. The BR output signal will

and BB deas-

to be asserted

remains asserted low

can also be

input

nal memory device off and on between internal and external bus accesses. BR timing is in that case similar to A0-A15,

and PS/DS; it is asserted and

R/W deasserted during t0.

(Bus Grant) — active low input when

in master mode, active low output when in slave mode. Output after

power on reset if the slave is selected, this pin is asserted to acknowledge an external bus request. It indicates that the DSP will release control of the external address bus A0-A15, data bus D0-D15 and bus control pins when BB is deasserted. The BG output is asserted in response to a BR

output is asserted and BB is deas-

BG serted, the external address bus A0-A15, data bus D0-D15 and bus control pins are in the high impedance state. BG sertion may occur in the middle of an instruction which requires more than one external bus cycle for execution. Note that BG during indivisible read-modify-write instructions (BFSET, BFCLR, BFCHG). When BR is deasserted and the DSP regains control of the external address bus, data bus, and bus control pins when the BB pin is sampled high.

This pin becomes an input if the master bit in the OMR register is set (Master Mode). It is asserted by an external processor when the DSP may become the bus master. The DSP can start normal external memor y access af ter the BB has been deasserted by the previous bus master. When BG DSP will release the bus as soon as the current transfer is com plete d. The s tate

may be tested by testing the BS bit

of BG in the Bus Control Register. BG nored during hardware reset.

assertion will not occur

is deasserted, the BG output

input. When the

is deasserted, the

as-

is ig-

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Pin Descriptions

Bus Control

Interrupt and Mode Control

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BB (Bus Busy) — active low input when

not bus master, active low output when bus master. This pin is asserted

by the DSP when it becomes the bus master and it performs an external access. It is deasserted when the DSP releases bus mastership. BB input when the DSP is no longer the bus master.

becomes an

Interrupt and Mode Control

MODA/IRQA (Mode Select A/External In-

terrupt Request A) — input. This in-

put has two functions:

•to select the initial chip operating mode and,

•to allow an external device to request a DSP interrupt after internal synchronization.

MODA is read and internally latched in the DSP when the processor exits the reset state. MODA and MODB select the initial chip operating mode. Several clock cycles after leaving the reset state, the MODA pin changes to the external interrupt request IRQA ating mode can be changed by software after reset.

The IRQA ternal interrupt request which indicates that an external device is requesting service. It may be programmed to be level sensitive or negative edge triggered. If level sensitive triggering is selected, an external pull up resistor is required for wired-OR operation. If the processor is in the stop standby state and IRQA processor will exit the stop state.

input is a synchronized ex-

. The chip oper-

is asserted, the

MODB/IRQB

MODC ( Mode Select C) — input. This input

RESET

(Mode Select B/External In-

terrupt Request B) — input. This in-

put has two functions:

•to select the initi al chip operating mode and,

•to allow an external device to request a DSP interrupt after internal synchronization.

MODB is read and internally latched in the DSP when the processor exits the reset state. MODA and MODB select the initial chip operating mode. Several clock cycles after leaving the reset state, the MODB pin changes to the external interrupt request IRQB chip operating mode can be changed by software.

The IRQB request which indicates that an external device is requesting service. It may be programmed to be level sensitive or negative edge triggered. If level sensitive triggering is selected, an external pull up resistor is required for wiredOR operation.

selects the initial bus operating mode. When tied high, the external bus is programmed in the master mode (BR put and BG the bus is programmed in the slave mode (BR MODC is read and internally latched in the DSP when the processor exits the reset state. After RESET ing mode can be changed by software by writing the MC bit of the OMR register.

(Reset) — input. This input is a direct

hardware reset of the processor. When RESET and placed in the reset state. A Schmitt

input is an external interrupt

input) and when tied low

input and BG output).

is asserted, the DSP is initialized

. After reset, the

, the bus operat-

out-

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Pin Descriptions

Interrupt and Mode Control

Host Interface

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trigger input is u sed for nois e immuni ty . When the reset pin is deasserted, the initial chip operating mode is latched from the MODA and MODB pins, and the initial bus operating mode is latched from the MODC pin. The internal reset signal should be deasserted synchronized with the internal clocks.

Host Interface

H0-H7 (Host Dat a Bu s) — bidirectional. This

bidirectional data bus is used to transfer data between the host processor and the DSP. This bus is an input unless enabled by a host processor read. H0-H7 may be programmed as Port B general purpose parallel I/O pins called PB0 -PB7 when the Host Interface (HI) is not being used.

HA0-HA2 (Host Address 0-2) — input*. These

inputs provide the address selection for each HI register and are stable when HEN be programmed as Port B general purpose parallel I/O pins called PB8-PB10 when the HI is not being used.

(Host Read/Write) — input*. Th is in-

HR/W

put selects the direction of data transfer for each host processor access. If HR/W is high and HEN is asserted, H0-H7 are outputs and DSP data is transferred to the host processor. If HR/W HEN host data is transferred to the DSP. When HEN HR/W eral purpose I/O pin called PB11 when the HI is not being used.

is asserted. HA0-HA2 may

is low and

is asserted, H0-H7 are inputs and

is asserted, HR/W is stable.

may be programmed as a gen-

HEN

(Host Enable) — input*. This input en-

ables a data transfer on the host data bus. When HEN is high, H0-H7 becomes an output a nd DSP data may be latched by the host processor. When HEN HR/W host data is latched inside the DSP when HEN chip select signal derived from host address decoding and an enable clock is connected to the Host Enable. HEN may be programmed as a general purpose I/O pin called PB12 when the HI is not being used.

(Host Request) — output*. This open-

HREQ

drain output signal is used by the HI to request service from the host processor. HREQ terrupt request pin of a host processor, a transfer request of a DMA controller, or a control input of external ci rcuitry. HREQ quest occurs in the HI. HREQ serted when the enabled request is cleared or masked, DMA HACK is asserted, or the DSP is reset. HREQ be programmed as a general purpose I/O pin (not open-drain) called PB13 when the HI is not being used.

(Host Acknowledge) — input*. This

HACK

input has two functions:

If programmed as a host acknowledge signal, HACK strobe for HI DMA data transfers. If programmed as an MC68000 ho st interrupt

is low, H0-H7 is an input and

is asserted when an enabled re-

•to provide a host acknowledge signal for DMA transfers and,

•to control handshaking and to provide a host interrupt acknowledge compatible with MC68000 family processors.

is asserted and HR/W

is asserted and

is deasserted. Normally a

may be connected to an in-

may be used as a data

is deas-

may

* These pins can be bidirectional when programmed as general purpose I/O. MOTOROLA DSP56156 Data Sheet 11

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Pin Descriptions

16-bit Timer SSI

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acknowledge, HACK enables the HI Interrupt Vector Register (IVR) onto the host data bus H0-H7 if the Host Request HREQ case, all other HI control pins are ignored and the HI state is not affected. HACK eral purpose I/O pin called PB14 when the HI is not being used.

output is asserted. In this

may be programmed as a gen-

16-bit Timer

TIN (Timer Input) — input*. This input re-

ceives external pulses to be counted by the on-chip 16-bit timer when external clocking is selected. The pulses are internally synchronized to the DSP core internal clock. TIN may be programmed as a general purpose I/O pin called PC10 when the external event function is not being used.

TOUT (Timer Output) — output*. This out-

put generates pulses or toggles on a timer overflow event or a compare event. TOUT may be programmed as a general purpose I/O pin called PC11 when disabled by the timer out enable bits (TO2-TO0).

Synchronous Serial Interfaces (SSI)

PC0 and PC5, respectively, when the STD function is not being used.

SRD0-1 (SSI0-1 Receive Data) — input*.

These input pins receive serial data and transfer the data to the SSI0-1 Receive Shift Register. SRD0 and SRD1 may be programmed as a general purpose I/O pin called PC1 and PC6, respectively, when the SRD function is not being used.

SCK0-1 (S SI0-1 Serial Clock) — bidirection-

al. These bidirectional pins provide the

serial bit rate clock for the SSI0-1 interface. SCK0 and SCK1 may be programmed as a general purpose I/O pin called PC2 and PC7, respectively, when the SSI0-1 interfaces are not being used.

SC10-11 (SSI0-1 Serial Control 1) — bidirec-

tional. These bidirectional pins are

used by the SSI0-1 serial interface as frame sync I/O or flag I/O. SC10 and SC11 may be programmed as a gene ral purpose I/O pin called PC3 and PC8, respectively, when the SSI0-1 are not using these pins.

SC00-01 (SSI0-1 Serial Control 0) — bidirec-

tional. These bidirectional pins are

used by the SSI0-1 serial interface as frame sync I/O or flag I/O. SC00 and SC01 may be programmed as a gene ral purpose I/O pin called PC4 and PC9, respectively, when the SSI0-1 are not using these pins.

STD0-1 (SSI0-1 Transmit Data) — output*.

These output pins transmit seri al data from the SSI 0-1 Transm it Shift R egister. STD0 and STD1 may be programmed as a general purpose I/O pin called

* These pins can be bidirectional when programmed as general purpose I/O.

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Pin Descriptions

OnCE

On-Chip Codec

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On-Chip Emulation

(OnCE

DSI/OS0 (Debug Serial Input/Chip Status 0) —

DSCK/OS1 (Debug Serial Clock/Chip Status 1)

DSO (Debug Serial) — output. The debug

Port)

bidirectional. The DSI/OS0 pin, when

an input, is the pin through which serial data or commands are provided to the OnCE port controller. The data received on the DSI pin will be recognized only when the DSP has entered the debug mode of operation. Data must have valid TTL logic levels before the serial clock falling edge. Data is always shifted into the OnCE serial port most significant bit (MSB) first. When the DSP is not in the debug mode, the DSI / OS0 pin provides information about the chip status if it is an output and used in conjunction with the OS1 pin.

— bidirectional. The DSCK/OS1 pin, when an input, is the pin through which the serial clock is supplied to the OnCE port. The serial clock provides pulses required to shift data into and out of the OnCE serial port. Data is clocked into the OnCE port on the falling edge and is clocked out of the OnCE serial port on the rising edge. If the DSCK/OS1 pin is an output and used in conjunction with the OS0 pin, it provides information about the chip status when the DSP is not in the debug mode.

serial output provides the data contained in one of the OnCE port con troller registers as specified by the last command received from the command controller. When idle, this pin is high. When the requested data is available, the DSO line will be asserted (negative true logic) for four T cycles (one instruction

cycle) to indicate that the serial sh ift register is ready to receive clocks in order to deliver the data. When the chip enters the debug mode du e to an external debug request (DR debug request (DEBUG), a hardware breakpoint occurrence or a trace/step occurrence, this l ine will be assert ed for three T cycles to indicate that the chip has entered the debug mode and is waiting for commands. Data is always shifted out the OnCE serial port with the most significant bit first.

(Debug Request) — input. The debug

request input provides a means of entering the debug mode of operation. This pin, when asserted, will cause the DSP to finish the current instructio n being executed, enter the debug mode, and wait for commands to be entered from the debug serial input line.

), an internal software

On-Chip Codec

AUX (Auxiliary) — input. This pin is select-

ed as the analog input to the A/D converter when the INS bit is set in the codec control register COCR. This pin should be left floating when the codec is not used.

BIAS (Bias current) — input. This input is

used to determine the bias current for the analog circuitry. Connecting a resistor between BIAS and GNDA will program the current bias generator. This pin should be left floating when the codec is not used.

MIC (Microphone) — input. This pin is se-

lected as the analog input to the A/D converter when the INS bit is cleared in

MOTOROLA DSP56156 Data Sheet 13

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Pin Descriptions

On-Chip Codec

Power, Ground, and Clock

Freescale Semiconductor, Inc.

nc...

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the codec control register COCR. This pin should be left floa ting when the codec is not used.

SPKP (Speaker Plus) — output. This pin is

the positive analog output from the onchip D/A converter. This pin should be left floating when the codec is not used.

SPKM (Speaker Minus) — output. This pin is

the negative analog output from the on-chip D/A converter. This pin should be left floating when the codec is not used.

VREF (Voltage Reference) — output. This

pin is the op-amp buffer output in the reference voltage generator. It has a value of ( ways be connected to the GNDA through two capacitors, even when the codec is not used.

VDIV (Voltage Division) — output. This

output pin is also the output to the onchip op-amp buffer in the reference voltage generator. It is connected to a resistor divider network located within the codec block which provides a voltage equal to ( be connected to the GND via a capacitor when the codec is used and should be left floating when the codec is not used.

. This pin should al-

CCA

. This pin shou ld

CCA

Power, Ground, and Clock

VCC(Power) — Power pins

GND (Ground) — Ground pins

(Synthesizer Power) — This pin sup-

CCS

plies a quiet power source to the PhaseLocked Loop (PLL) to provide greater frequency stability.

GNDS (Synthesizer Ground) — This pin sup-

plies a quiet ground source to the PLL to provide greater frequency stability.

(Analog Power) — This pin is the posi-

CCA

tive analog supply input. It should be connected to V

GNDA (Analog Ground) — This pin is the an-

alog ground return. It should be connected to digital GND when the codec is not used.

EXTAL (External Clock) — input. This input

should be driven by an external clock or by an external oscillator. After being squared, the input frequency can be used as the DSP core internal clock. In that case, it is divided by two to produce a four phase instruction cycle cl ock, t he minimum inst ruction t ime being t wo input clock periods. Th is i nput frequen cy is also used, after division, as input clock for the on-chip codec and the onchip PLL.

CLKO (Clock Output) — output. This pin

outputs a buffered clock signal. By programming two bits (CS1-CS0) inside the PLL Control Register (PLCR), the user can select between outputting a squared version of the signal applied to EXTAL, a squared version of the signal applied to EXTAL divided by 2, and a delayed version of the DSP core master clock. The clock frequency on this pin can be disabled by setting the Clockout Disable bit (CD; bit 7) of the Operating Mode Register (OMR). When disabled, the pin can be left floating.

SXFC (External Filter Capacitor) — This pin

adds an external capacitor to the PLL filter circuit. A low leakage capacitor should be connected between and located very close to SXFC and V

when the codec is not used.

CCS

14 DSP56156 Data Sheet MOTOROLA

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Electrical Characteristics and Timing

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CAUTION:

The DSP56156 is fabricated in high density HCMOS with TTL compatible inputs and CMOS compatible outputs.

Supply Voltage V All Input Voltages V Current Drain per Pin ex cludi ng V Storage Temperature T

Exceeding maximum electrical ratings will permanently damage or

disable the chip, or impair the chip’s long term reliability.

Table 4 Maximum Electrical Ratings (GND = 0 Vdc)

Rating Symbol Value Unit

and GND I 10 mA

stg

Table 5 Operating Conditions

Supply Voltage

Min Max Min Max

4.5 5.5 -40 115

Table 6 Thermal Characteri stics of CQFP and TQFP Packages

Junction Temperature

(°C)

-0.3 to +7.0 V

GND - 0.5 to VCC + 0.5 V

-55 to +150 °C

Thermal Resistance

Characteristics

Junction to Ambient Θ Junction to Case (estimated) Θ

NOTE: This device contains protective circuitry to guard against damage due to high static voltage or electrical

fields. Howeve r, normal precaution s are advised to av oid application o f any voltages hi gher than maximu m rated voltages to t his high-i mpedance c ircuit. R eliabili ty of opera tion is en hanced if unused in puts ar e tied to an appropriate logic voltage level (e.g., either GND or V

MOTOROLA DSP56156 Data Sheet 15

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Symbol

Value

Rating

CQFP TQFP

40 49 °C/W

78°C/W

Electrical Charac teristics and Timing

Analog I/O Characteristics

= 5.0 V dc ± 10%, TJ = -40° to +125°C)

The analog I/O characteristics of this device are listed in Ta ble 7. For additional information regarding the use of analog signals, see “Design Considerations” at the end of this document.

Characteristic Min Typ Max Unit

Input Impedance on MIC and AUX (See Note 1) 46 78 1400 kΩ

nc...

Input Capacitance on MIC and AUX ——10pF Peak Input Voltage on the MIC/AUX Input for Full Scale

Linearity (0.14 dBm0): 6 dB - MGS1 - 0 = 00 (See Note 2) 0 dB - MGS1 - 0 = 01

Freescale Semiconductor, Inc.

Table 7 Analog I/O Characteris ti cs

6 dB - MGS1 - 0 = 10 17 dB - MGS1 - 0 = 11

— — — —

1.414

0.707 354 100

Vp mVp mVp

cale Semiconductor,

Frees

Internal Input Gain Variation; G = -6 dB, 0 dB, 6 dB or 17 dB (±0.83 dB variation due to 10% variation on V

VREF Output Voltage 1.8 2 2.2 V VREF Output Current — — ±1 mA DC Offset Between SPKP and SPKM — — 100 mV Allowable Differential Load Capacitance on

SPKP and SPKM (with 1 kΩ in series) Allowable Single-ended Load Capacitance on

SPKP or SPKM (with 0.5 kΩ in series) Maximum Single-ended Signal Output Level — — 1 Vp Maximum Differential Signal Output Level — — 2 Vp Single-ended Load Resistance 500 — — Ω Differential Load Resistance 1 — — kΩ Resistance BIAS — 10

Internal Output Volume Control Variation VC = -20, -15, -10, -5, 0, 6, 12, 18, 24, 30, 35 dB (± 0.83 dB variation due to 10% variation on V

)

G - 0.83 G G + 0.83 dB

0 — 0.05 µF

(See Note 3)

VC - 0.83 VC VC + 0.83 dB

— 100

0.1

—kΩ

(See

Note 4)

µF

NOTES: 1. Minimum value reached for a Codec clock of 3 MHz, typical for 2 MHz and maximum for 100 kHz

2. 0 dBm0 corresponds to 3.14 dB below the input saturation level

3. AC coupling is necessary in single-ended mode when the load resistor is not tied to VREF

4. ± 10%

16 DSP56156 Data Sheet MOTOROLA

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Electrical Characteristics and Timing

A/D and D/A Performance

= 5.0 V dc ± 10%, T

CCA

The A/D and D/A performance of the codec section are given in Table 8 with an example presented in Figure 4.

= -40° to +125°C)

Table 8 A/D and D/A Performance of Codec

nc...

cale Semiconductor,

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Characteristic

Analog to Digital Section Signal to Nois e plus Distortion Ratio (S/N+T)

Digital to Analog Sect ion Sign al to Noise plus Distortion Ratio (S/N+T)

NOTES: 1. 0 dB gain on the A/D and D/A; Co dec clock a t 1.538 MHz with 12 8 decima tion/interpol ation ratio and

tested at 1502 Hz

2. 0 dBm0 corresponds to -3.14 dB below the input saturation level

S/N

S/N+T

Level Min

0 dBm0

(See Note 2)

-50 dBm0 15 20 — dB 0 dB 55 65 — dB

-50 dB 15 20 — dB

13 MHz

55 65 —dB

2 MHz

÷ 6.5

÷ 13

÷13

Typ

(See Note 1)

CODEC

Codec

1 MHz

PLL

÷(12+1)x4

÷(12+1)*4

Max

COCR=$E400

Unit

52 MHz

S in dB

Signal in dB

Figure 4 Example: S/N and S/N+T Performance for the A/D Section

MOTOROLA DSP56156 Data Sheet 17

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Electrical Charac teristics and Timing

Other On-Chip Codec Characteristics

= 5.0 V dc ± 10%, T

CCA

The analog I/O characteristics of this device are shown in Table 9.

Table 9 Analog I/O Characteristics of On-Chip Codec

Characteristic Min Typ Max Unit

Freescale Semiconductor, Inc.

= -40° to +125°C, CL = 50 pF + 1 TTL Load)

nc...

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Codec Master Clock 0.1 2.048 3 MHz Codec Sampli ng Rate 78 16000 37000 Hz A/D Section Group Delay ——0.2msec

D/A Section Group Delay — — 0.2 msec

18 DSP56156 Data Sheet MOTOROLA

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DC Electrical Characteristics and Timing

DC Electrical Characteristics

(GND = 0 V dc)

= 5.0 V dc ± 10%, TJ = -40° to +125°C, CL = 50 pF + 1 TTL Load)

The DC electrical characteristics of this device ar e shown in Table 10.

Table 10 DC Electrical Characteristics

Characteristic Symbol Min Typ Max Unit

nc...

cale Semiconductor,

Frees

Input High Voltage except EXTAL, RESET

Input Low Voltage except EXTAL, MODA, MODB, MODC

Input High Voltage

EXTAL DC coupled EXTAL AC coupled (See Note 1)

Input Low Voltage

EXTAL DC coupled

EXTAL AC coupled (See Note 1) Input High Voltage RESET Input High Voltage MODA, MODB, MODC V Input Low Voltage MODA, MODB, MODC V Input Leakage Current

RESET

Three-State (Off-State) Input Current

Output High Voltage (I Output High Voltage (I Output Low Voltage (I Output Low Voltage (IOL = 3.2 mA

, MODA, MODB, MODC, TA, DR, BR

(@2.4 V/0.5 V)

R/W

IOL = 1.6 mA; Open Drain

IOL = 6.7 mA, TXD IOL = 6.7 mA)

HREQ

, MODA, MODB, MODC

EXTAL

= -10 µA) V

= -0.4 mA) V

= 10 µA) V

IHC

ILC

IHR

IHM

ILM

TSI -10 — 10 µA

OHC

OLC

2.0 — V

-0.5 — 0.8 V

70% of V

VCC -0.1 — — V

-0.5

2.5 — V

3.5 — V

-0.5 — 2.0 V

-100

-1

2.4 — — V ——0.1V ——0.4V

— —

—

20% of V

VCC-1

100

V V

µA µA

Input Capacitance (See Note 2) C

NOTES: 1. When EXTAL is AC coupled, V

2. Input capacitance is periodically sampled and not 100% tested in production.

MOTOROLA DSP56156 Data Sheet 19

For More Information On This Product,

IHC

- V

Š 1 V must be true.

ILC

—10—pF

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AC Electrical Characteristics and Timing

Clock Operation Timing

AC Electrical Characteristics

(GND = 0 V dc)

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The timing waveforms in the AC Electrical Charact eristics ar e tested with a V

0.5 V and a V

minimum of 2.4 V for all pins, except EXTAL, RESET, MODA, MODB and

maximum of

MODC. These five pins are tes ted using the in put levels set forth in the DC Elect rical Charac - teristics. AC timing spec ifications whi ch are r efer enced to a device i nput signal ar e measured

in production with respect to the 50% point of the respective input signal’s transition. The DSP56156 output levels are measured with the production test machine V

and VOH refer-

ence levels set at 0.8 V and 2.0 V respectively.

Clock Operation Timing

The system clock to the DSP56156 must be externally supplied to EXTAL as illustrated in Figure 6.

Table 11 Clock Operation Timing

40 MHz 50 MHz 60 MHz

Num Characteristics Sym

Min Max Min Max Min Max

1 Frequency of Operation (EXTAL) f 0 40 0 50 0 60 MHz 2 Instruction Cycle Time = 2T

3 Wait State Time = T 4 EXTAL Cycle Period T 5 EXTAL Rise Time (See Note 1) — 4 — 3 — 3 ns 6 EXTAL Fall Time (See Note 1) — 4 — 3 — 3 ns 7 EXTAL Width High

48-52% duty cycle (See Notes 2, 3, 4)

8 EXTAL Width Low

48%-52% duty cycle (See Notes 2, 3, 4)

= 2T — 25 × 20 × 16.6 × ns

CYC

50 ×40×33×ns

25 × 20 × 16.6 × ns

12 × 9.6 × 8 × ns

Unit

NOTES: 1. Rise and fall time may b e relaxed to 12 ns maxi mum if the EXTAL input freq uency is less than o r equal

to 20 MHz. If the EXTAL input frequency is between 20 MHz and 40 MHz, rise and fall time should meet the specified values in the 40 MHz column (4 ns maximum).

2. The duty cycle may be rela xed to 43-57% i f the EXTAL input frequency is l ess than or equ al to 20 MHz. If the EXTAL input frequency is between 20 MHz and 40 MHz, the duty cycle should be such that T

and TL meet the specified values in the 40 MH z colum n (12 ns mi nim u m ).

3. T = I cycle of the external clock input.

4. Duty cycles and EXTAL widths are m easured at the EXTAL inp ut signal midpo int when AC coupled a nd at VCC/2 when not AC coupled.

20 DSP56156 Data Sheet MOTOROLA

/ 4 is used in the electrical characteristics. The exact length of each T is affected by the duty

CYC

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EXTAL

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7 8

Figure 5 External Clock Timing

Other Clock and PLL Operation Timing

AC Electrical Characteristics and Timing

Clock Operation Timing

PLL

IHC

90%

Midpoint

10%

ILC

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Clock and PLL timings are listed i n Table 12 and the clocking configurations ar e i llustrated i n Figure 6.

Table 12 Clock and PLL Timing

Characteristics Min Max Unit

PLL Output frequency 10 Max Fosc

EXTAL Input Clock Amplitude (See Note 2) 1 V

NOTES: 1. Maximum DSP operating frequency. See Table 11.

2. An AC coupling capacitor is required on EXTAL if the levels are out of the normal CMOS level

EXTAL

range (V

100 KΩ

>20% of V

ILC

÷ 1 to ÷ 16

ED3-ED0

or V

IHC

<70% of VCC).

SXFC

PFD

10 nF

XFC

(See Note 1)

0.01 µF

0.1 µF

CCS

VCO

MHz

Vpp

GNDS

PLLE=1

Fosc

1000 pF

CLKO

CS1-CS0

÷ 2

÷ 6.5

GSM

PLL

CODEC

÷ 1 to ÷ 16

YD3-YD0

÷ 4

internal phase PH0 at Fosc

PLLE=0

Figure 6 Clocking Configurations

MOTOROLA DSP56156 Data Sheet 21

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AC Electrical Characteristics and Timing

Reset, Stop, Wait, Mode Select, and Interrupt Timing

(VCC = 5.0 V dc ± 10%, T

cyc = Clock cycle =

/2 instruction cycle = 2 T cycles

ws = Number of wait states progra mmed into external b us acces s using BCR (WS = 0 - 3 1)

Table 13 Reset, Stop, Wait, Mode Select, and Interrupt Timing

Num Characteristics

10 RESET

nc...

cale Semiconductor,

Control Signals High Impedance

11 Minimum Stabilization Duration

(See Note 1) OMR bit 6=0

12 Asynchronous RESET Deassertion to

First External Address Output (See Note 7)

13 Synchronous Reset Setup Time from

RESET CLKO

14 Synchronous Reset Delay Time from

CLKO High to the First External Access

(See Note 7) 15 Mode Select Setup Time 16 Mode Select Hold Time 17 Edge-triggered Interrupt Request Width 18 Delay from IRQA, IRQB Assertion to

External Data Memory Access Out Valid

- Caused by First Interrupt

Frees

- Caused by First Interrupt

Assertion to Address, Data and

OMR bit 6=1

Deassertion to Rising Edge of

Instruction Fetch Instruction Execution

= -40° to +125°C, CL = 50 pF + 1 TTL Load)

40 MHz 50 MHz 60 MHz

Min Max Mi n Max Min Max

—25—23—21ns

600KT

60T

16T 18T+20 16T 18T+17 16T 18T+15 ns

7 cyc-4 6 cyc-3 5 cyc-2 ns

16T+3 16T+20 16T+ 3 16T+18 16T+3 16T+16 ns

22 — 20 — 18 — ns

0—0—0—ns

13 — 11 — 9 — ns

11T+4

19T+4

— —

—

600KT

60T

11T+4

19T+4

— —

—

600KT

60T

11T+3

19T+3

Unit

— —

—

ns ns

19 Delay from IRQA, IRQB Assertion to

General Purpose Output Valid Cause d

by the Execution of the First Interrupt

Instruction 20 Delay from External Data Memory

Address Output Valid Caused by First

Interrupt Instruction Execution to Inter-

rupt Request Deassertion for Level Sen-

sitive Fast Interrupts (See Note 2)

22 DSP56156 Data Sheet MOTOROLA

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22T+5

—5T-26

—

cyc × ws

22T+4 — 22T+3 — ns

—5T-24

cyc × ws

—5T-22

cyc × ws

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AC Electrical Characteristics and Timing

Reset, Stop, Wait, Mode Select, and Interrupt Timing

(VCC = 5.0 V dc ± 10%, TJ = -40° to +125°C, CL = 50 pF + 1 TTL Load)

Table 13 Reset, Stop, Wait, Mode Select, and Interrupt Timing (continued)

40 MHz 50 MHz 60 MHz

Num Characteristics

Min Max Min Max Min Max

21 Delay from General-Purpose

Output Valid Caused by the Execution of the First Interrupt Instruction to IRQA, IRQB

Deassertion for Level

Sensitive Fast Interru pts — If

nc...

2nd Interrupt Instruction is:

Single Cycle

(See Note 2)

Two Cycles

— —

cyc - 29

3 cyc - 29

— —

cyc - 27

3 cyc - 27

— —

cyc - 26

3 cyc - 26nsns

Unit

cale Semiconductor,

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22 Synchronous setup time from

, IRQB assertion to

IRQA Synchronous falling edge of CLKO (See Notes 5 and 6)

23 Falling Edge of CLKO to First

Interrupt Vector Address Out Valid after Synchronous recovery from Wait State (See Notes 3 and 5)

24 IRQA Width Assertion to

Recover from Stop State (See Note 4)

25 Delay from IRQA Assertion to

Fetch of first instruction (exiting Stop) (See Notes 1 and 3) OMR bit 6=0

OMR bit 6=1

28 Duration for Level Sensitive

IRQA

Assertion to Cause the Fetch of First IRQA Instruction (exiting Stop) (See Notes 1 and 3)

Interrupt

OMR bit 6=0 OMR bit 6=1

14 cyc-3 13 cyc-2 12 cyc-1 ns

27T+3 27T+20 27T+3 27T+18 27T+3 27T+16 ns

15 — 13 — 12 — ns

524303T+4

47T+4

524303T

47T

— —

524303T+3

47T+3

524303T

47T

— —

524303T+3

47T+3

524303T

47T

— —

ns ns

29 Delay from Level Sensitive

Assertion to First Inter-

IRQA rupt Vector Address Out Valid (exiting Stop) (See Notes 1 and 3)

OMR bit 6=0 OMR bit 6=1

MOTOROLA DSP56156 Data Sheet 23

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524303T+4

47T+4

— —

524303T+3

47T+3

— —

524303T+3

47T+3

— —

ns ns

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