Motorola DSP56012 User Manual

DSP56012UM/D Rev. 0 Published 11/98

DSP56012

24-Bit Digital Signal Processor

User’s Manual

Motorola, Incorporated Semiconductor Products Sector DSP Division 6501 William Cannon Drive West Austin, TX 78735-8598

DSP56012UM/D Rev. 0 Published 11/98

This document (and other documents) can be viewed on the World Wide Web at http://www.motorola-dsp.com.

This manual is one of a set of three documents. You need the following manuals to have complete product information: Family Manual, User’s Manual, and Technical Data.

OnCE





is a trademark of Motorola, Inc.

MOTOROLA INC., 1998

Order this document by DSP56012UM/AD

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

Table of Contents

1.1 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1.1.1 Manual Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

1.1.2 Manual Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

1.2 DSP56012 FEATURES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

1.3 DSP56012 ARCHITECTURAL OVERVIEW . . . . . . . . . . . . . 1-8

1.3.1 Peripheral Modules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

1.3.2 DSP Core Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

1.3.2.1 Data Arithmetic and Logic Unit (Data ALU) . . . . . . . . 1-11

1.3.2.2 Address Generation Unit (AGU). . . . . . . . . . . . . . . . . 1-11

1.3.2.3 Program Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . 1-12

1.3.2.4 Data Buses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12

1.3.2.5 Address Buses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12

1.3.2.6 Phase Lock Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . 1-12

1.3.2.7 On-Chip Emulation (OnCE) Port . . . . . . . . . . . . . . . . 1-13

1.3.3 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13

1.3.3.1 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13

1.3.3.2 X Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15

1.3.3.3 Y Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15

1.3.3.4 On-Chip Memory Configuration Bits . . . . . . . . . . . . . 1-15

1.3.3.5 Memory Configuration Bits. . . . . . . . . . . . . . . . . . . . . 1-16

1.3.3.6 External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

1.3.3.7 Bootstrap ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

1.3.3.8 Reserved Memory Spaces. . . . . . . . . . . . . . . . . . . . . 1-16

1.3.4 Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

1.3.4.1 Parallel Host Interface (HI). . . . . . . . . . . . . . . . . . . . . 1-18

1.3.4.2 Serial Host Interface (SHI). . . . . . . . . . . . . . . . . . . . . 1-18

1.3.4.3 Serial Audio Interface (SAI) . . . . . . . . . . . . . . . . . . . . 1-19

1.3.4.4 General Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . 1-19

1.3.4.5 Digital Audio Transmitter (DAX). . . . . . . . . . . . . . . . . 1-19

2.1 SIGNAL GROUPINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

2.2 POWER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2.3 GROUND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.4 PHASE LOCK LOOP (PLL). . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.5 INTERRUPT AND MODE CONTROL. . . . . . . . . . . . . . . . . . 2-8

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2.6 HOST INTERFACE (HI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

2.7 SERIAL HOST INTERFACE (SHI) . . . . . . . . . . . . . . . . . . . 2-13

2.8 SERIAL AUDIO INTERFACE (SAI) . . . . . . . . . . . . . . . . . . 2-16

2.8.1 SAI Receive Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16

2.8.2 SAI Transmit Section . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

2.9 GENERAL PURPOSE INPUT/OUTPUT (GPIO) . . . . . . . . 2-18

2.10 DIGITAL AUDIO INTERFACE (DAX) . . . . . . . . . . . . . . . . . 2-18

2.11 ONCE PORT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19

3.1 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.2 DSP56012 DATA AND PROGRAM MEMORY. . . . . . . . . . . 3-3

3.2.1 X and Y Data ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

3.2.2 Bootstrap ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

3.3 DSP56012 DATA AND PROGRAM MEMORY MAPS . . . . . 3-4

3.3.1 Reserved Memory Spaces. . . . . . . . . . . . . . . . . . . . . . . . 3-5

3.3.2 Dynamic Switch of Memory Configurations . . . . . . . . . . . 3-8

3.3.3 Internal I/O Memory Map . . . . . . . . . . . . . . . . . . . . . . . . 3-10

3.4 OPERATING MODE REGISTER (OMR) . . . . . . . . . . . . . . 3-12

3.4.1 DSP Operating Mode (MC, MB, MA)—Bits 4, 1, and 0 . 3-12

3.4.2 Program RAM Enable A and Program RAM Enable B (PEA and PEB)—Bits 2 and 33-12

3.4.3 Stop Delay (SD)—Bit 6. . . . . . . . . . . . . . . . . . . . . . . . . . 3-12

3.5 OPERATING MODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13

3.6 INTERRUPT PRIORITY REGISTER . . . . . . . . . . . . . . . . . 3-15

3.7 PHASE LOCK LOOP (PLL) CONFIGURATION. . . . . . . . . 3-19

3.8 OPERATION ON HARDWARE RESET . . . . . . . . . . . . . . . 3-20

4.1 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4.2 PORT B CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4.2.1 Port B Control (PBC) Register . . . . . . . . . . . . . . . . . . . . . 4-6

4.2.2 Port B Data Direction Register (PBDDR) . . . . . . . . . . . . . 4-7

4.2.3 Port B Data (PBD) Register . . . . . . . . . . . . . . . . . . . . . . . 4-7

4.3 PROGRAMMING THE GPIO . . . . . . . . . . . . . . . . . . . . . . . . 4-8

4.4 HOST INTERFACE (HI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

4.4.1 HI Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10

4.4.2 HI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11

4.4.3 HI—DSP Viewpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12

4.4.4 Programming Model—DSP Viewpoint . . . . . . . . . . . . . . 4-13

4.4.4.1 HI Control Register (HCR). . . . . . . . . . . . . . . . . . . . . 4-14

4.4.4.1.1 HCR HI Receive Interrupt Enable (HRIE)—Bit 0 . 4-15

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4.4.4.1.2 HCR HI Transmit Interrupt Enable (HTIE)—Bit 1 . 4-15

4.4.4.1.3 HCR HI Command Interrupt Enable (HCIE)—Bit 2 4-15

4.4.4.1.4 HCR HI Flag 2 (HF2)—Bit 3 . . . . . . . . . . . . . . . . . 4-15

4.4.4.1.5 HCR HI Flag 3 (HF3)—Bit 4 . . . . . . . . . . . . . . . . . 4-15

4.4.4.1.6 HCR Reserved—Bits 5, 6, and 7. . . . . . . . . . . . . . 4-16

4.4.4.2 HI Status Register (HSR). . . . . . . . . . . . . . . . . . . . . . 4-16

4.4.4.2.1 HSR HI Receive Data Full (HRDF)—Bit 0. . . . . . . 4-16

4.4.4.2.2 HSR HI Transmit Data Empty (HTDE)—Bit 1 . . . . 4-16

4.4.4.2.3 HSR HI Command Pending (HCP)—Bit 2. . . . . . . 4-17

4.4.4.2.4 HSR HI Flag 0 (HF0)—Bit 3 . . . . . . . . . . . . . . . . . 4-17

4.4.4.2.5 HSR HI Flag 1 (HF1)—Bit 4 . . . . . . . . . . . . . . . . . 4-17

4.4.4.2.6 HSR Reserved—Bits 5 and 6 . . . . . . . . . . . . . . . . 4-18

4.4.4.2.7 HSR DMA Status (DMA)—Bit 7 . . . . . . . . . . . . . . 4-18

4.4.4.3 HI Receive Data Register (HORX). . . . . . . . . . . . . . . 4-18

4.4.4.4 HI Transmit Data Register (HOTX) . . . . . . . . . . . . . . 4-19

4.4.4.5 Register Contents After Reset. . . . . . . . . . . . . . . . . . 4-19

4.4.4.6 DSP Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20

4.4.4.7 HI Usage Considerations—DSP Side . . . . . . . . . . . . 4-21

4.4.5 HI—Host Processor Viewpoint. . . . . . . . . . . . . . . . . . . . 4-21

4.4.5.1 Programming Model—Host Processor Viewpoint . . . 4-21

4.4.5.2 Host Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22

4.4.5.3 Interrupt Control Register (ICR). . . . . . . . . . . . . . . . . 4-24

4.4.5.3.1 ICR Receive Request Enable (RREQ)—Bit 0. . . . 4-24

4.4.5.3.2 ICR Transmit Request Enable (TREQ)—Bit 1 . . . 4-24

4.4.5.3.3 ICR Reserved—Bit 2. . . . . . . . . . . . . . . . . . . . . . . 4-25

4.4.5.3.4 ICR HI Flag 0 (HF0)—Bit 3 . . . . . . . . . . . . . . . . . . 4-25

4.4.5.3.5 ICR HI Flag 1 (HF1)—Bit 4 . . . . . . . . . . . . . . . . . . 4-26

4.4.5.3.6 ICR HI Mode Control (HM1 and HM0)—Bits 5 and 64-26

4.4.5.3.7 ICR Initialize Bit (INIT)—Bit 7 . . . . . . . . . . . . . . . . 4-27

4.4.5.4 HI Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27

4.4.5.5 Command Vector Register (CVR) . . . . . . . . . . . . . . . 4-29

4.4.5.5.1 CVR HI Vector (HV)—Bits 0–5 . . . . . . . . . . . . . . . 4-29

4.4.5.5.2 CVR Reserved—Bit 6 . . . . . . . . . . . . . . . . . . . . . . 4-30

4.4.5.5.3 CVR Host Command (HC)—Bit 7 . . . . . . . . . . . . . 4-30

4.4.5.6 Interrupt Status Register (ISR). . . . . . . . . . . . . . . . . . 4-30

4.4.5.6.1 ISR Receive Data Register Full (RXDF)—Bit 0. . . 4-30

4.4.5.6.2 ISR Transmit Data Register Empty (TXDE)—Bit 1 4-31

4.4.5.6.3 ISR Transmitter Ready (TRDY)—Bit 2 . . . . . . . . . 4-31

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4.4.5.6.4 ISR HI Flag 2 (HF2)—Bit 3 (read only) . . . . . . . . . 4-31

4.4.5.6.5 ISR HI Flag 3 (HF3)—Bit 4 (read only) . . . . . . . . . 4-31

4.4.5.6.6 ISR Reserved—Bit 5. . . . . . . . . . . . . . . . . . . . . . . 4-31

4.4.5.6.7 ISR DMA Status (DMA)—Bit 6 . . . . . . . . . . . . . . . 4-32

4.4.5.6.8 ISR Host Request (HOREQ)—Bit 7 . . . . . . . . . . . 4-32

4.4.5.7 Interrupt Vector Register (IVR) . . . . . . . . . . . . . . . . . 4-32

4.4.5.8 Receive Byte Registers (RXH, RXM, RXL) . . . . . . . . 4-32

4.4.5.9 Transmit Byte Registers (TXH, TXM, TXL) . . . . . . . . 4-33

4.4.5.10 Registers After Reset. . . . . . . . . . . . . . . . . . . . . . . . . 4-33

4.4.6 HI Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35

4.4.6.1 HI Data Bus (H0–H7). . . . . . . . . . . . . . . . . . . . . . . . . 4-35

4.4.6.2 HI Address (HOA2–HOA0) . . . . . . . . . . . . . . . . . . . . 4-35

4.4.6.3 HI Read/Write (HR/W) . . . . . . . . . . . . . . . . . . . . . . . . 4-35

4.4.6.4 HI Enable (HEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35

4.4.6.5 Host Request (HOREQ). . . . . . . . . . . . . . . . . . . . . . . 4-35

4.4.6.6 Host Acknowledge (HACK) . . . . . . . . . . . . . . . . . . . . 4-36

4.4.7 Servicing the HI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-37

4.4.7.1 HI—Host Processor Data Transfer . . . . . . . . . . . . . . 4-37

4.4.7.2 Host Interrupts using Host Request (HOREQ) . . . . . 4-38

4.4.7.3 Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-38

4.4.7.4 Servicing Non-DMA Interrupts. . . . . . . . . . . . . . . . . . 4-39

4.4.7.5 Servicing DMA Interrupts. . . . . . . . . . . . . . . . . . . . . . 4-41

4.4.8 Host Interface Application Examples . . . . . . . . . . . . . . . 4-42

4.4.8.1 HI Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-42

4.4.8.2 Polling/Interrupt Controlled Data Transfer . . . . . . . . . 4-45

4.4.8.2.1 Host to DSP—Data Transfer. . . . . . . . . . . . . . . . . 4-49

4.4.8.2.2 Host to DSP–Command Vector . . . . . . . . . . . . . . 4-51

4.4.8.2.3 Host to DSP—Bootstrap Loading Using the HI. . . 4-54

4.4.8.2.4 DSP to Host—Data Transfer. . . . . . . . . . . . . . . . . 4-56

4.4.8.3 DMA Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . 4-59

4.4.8.3.1 Host to DSP—Internal Processing . . . . . . . . . . . . 4-61

4.4.8.3.2 Host to DSP—DMA Procedure . . . . . . . . . . . . . . . 4-62

4.4.8.3.3 DSP to HI —Internal Processing. . . . . . . . . . . . . . 4-64

4.4.8.3.4 DSP to Host—DMA Procedure . . . . . . . . . . . . . . . 4-65

4.4.8.4 HI Port Usage Considerations—Host Side . . . . . . . . 4-65

4.4.8.4.1 Unsynchronized Reading of Receive Byte Registers4-65

4.4.8.4.2 Overwriting Transmit Byte Registers. . . . . . . . . . . 4-66

4.4.8.4.3 Synchronization of Status Bits from DSP to Host . 4-66

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4.4.8.4.4 Overwriting the Host Vector . . . . . . . . . . . . . . . . . 4-66

4.4.8.4.5 Cancelling a Pending Host Command interrupt . . 4-66

4.4.8.4.6 Coordinating Data Transfers. . . . . . . . . . . . . . . . . 4-67

4.4.8.4.7 Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-67

5.1 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

5.2 SERIAL HOST INTERFACE INTERNAL ARCHITECTURE. 5-4

5.3 SHI CLOCK GENERATOR. . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

5.4 SERIAL HOST INTERFACE PROGRAMMING MODEL . . . 5-5

5.4.1 SHI Input/Output Shift Register (IOSR)—Host Side. . . . . 5-8

5.4.2 SHI Host Transmit Data Register (HTX)—DSP Side . . . . 5-8

5.4.3 SHI Host Receive Data FIFO (HRX)—DSP Side. . . . . . . 5-9

5.4.4 SHI Slave Address Register (HSAR)—DSP Side . . . . . . 5-9

5.4.4.1 HSAR Reserved Bits—Bits 17–0,19 . . . . . . . . . . . . . . 5-9

5.4.4.2 HSAR I

C Slave Address (HA[6:3], HA1)—Bits 23–20,185-9

5.4.5 SHI Clock Control Register (HCKR)—DSP Side . . . . . . . 5-9

5.4.5.1 Clock Phase and Polarity (CPHA and CPOL)—Bits 1–05-10

5.4.5.2 HCKR Prescaler Rate Select (HRS)—Bit 2. . . . . . . . 5-11

5.4.5.3 HCKR Divider Modulus Select (HDM[5:0])—Bits 8–3 5-12

5.4.5.4 HCKR Reserved Bits—Bits 23–14, 11–9. . . . . . . . . . 5-12

5.4.5.5 HCKR Filter Mode (HFM[1:0]) — Bits 13–12. . . . . . . 5-12

5.4.6 SHI Control/Status Register (HCSR)—DSP Side. . . . . . 5-13

5.4.6.1 HCSR Host Enable (HEN)—Bit 0 . . . . . . . . . . . . . . . 5-13

5.4.6.1.1 SHI Individual Reset . . . . . . . . . . . . . . . . . . . . . . . 5-13

5.4.6.2 HCSR I

C/SPI Selection (HI2C)—Bit 1 . . . . . . . . . . . 5-13

5.4.6.3 HCSR Serial Host Interface Mode (HM[1:0])—Bits 3–25-14

5.4.6.4 HCSR Reserved Bits—Bits 23, 18, 16, and 4 . . . . . . 5-14

5.4.6.5 HCSR FIFO-Enable Control (HFIFO)—Bit 5 . . . . . . . 5-14

5.4.6.6 HCSR Master Mode (HMST)—Bit 6 . . . . . . . . . . . . . 5-14

5.4.6.7 HCSR Host-Request Enable (HRQE[1:0])—Bits 8–7 5-15

5.4.6.8 HCSR Idle (HIDLE)—Bit 9. . . . . . . . . . . . . . . . . . . . . 5-15

5.4.6.9 HCSR Bus-Error Interrupt Enable (HBIE)—Bit 10. . . 5-16

5.4.6.10 HCSR Transmit-Interrupt Enable (HTIE)—Bit 11. . . . 5-16

5.4.6.11 HCSR Receive Interrupt Enable (HRIE[1:0])—Bits 13–12. 5-16

5.4.6.12 HCSR Host Transmit Underrun Error (HTUE)—Bit 14 5-17

5.4.6.13 HCSR Host Transmit Data Empty (HTDE)—Bit 15 . . 5-17

5.4.6.14 Host Receive FIFO Not Empty (HRNE)—Bit 17 . . . . 5-18

5.4.6.15 Host Receive FIFO Full (HRFF)—Bit 19 . . . . . . . . . . 5-18

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5.4.6.16 Host Receive Overrun Error (HROE)—Bit 20 . . . . . . 5-18

5.4.6.17 Host Bus Error (HBER)—Bit 21. . . . . . . . . . . . . . . . . 5-18

5.4.6.18 HCSR Host Busy (HBUSY)—Bit 22. . . . . . . . . . . . . . 5-19

5.5 CHARACTERISTICS OF THE SPI BUS. . . . . . . . . . . . . . . 5-19

5.6 CHARACTERISTICS OF THE I

C BUS . . . . . . . . . . . . . . . 5-20

5.6.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20

5.6.2 I

C Data Transfer Formats. . . . . . . . . . . . . . . . . . . . . . . 5-22

5.7 SHI PROGRAMMING CONSIDERATIONS . . . . . . . . . . . . 5-23

5.7.1 SPI Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23

5.7.2 SPI Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24

5.7.3 I

5.7.3.1 Receive Data in I

5.7.3.2 Transmit Data In I

5.7.4 I

5.7.4.1 Receive Data in I

5.7.4.2 Transmit Data In I

C Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25

C Slave Mode . . . . . . . . . . . . . . . . 5-26

C Slave Mode . . . . . . . . . . . . . . . 5-27

C Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27

C Master Mode . . . . . . . . . . . . . . . 5-29

C Master Mode . . . . . . . . . . . . . . 5-29

5.7.5 SHI Operation During Stop. . . . . . . . . . . . . . . . . . . . . . . 5-30

6.1 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

6.2 SERIAL AUDIO INTERFACE INTERNAL ARCHITECTURE 6-4

6.2.1 Baud-Rate Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

6.2.2 Receive Section Overview . . . . . . . . . . . . . . . . . . . . . . . . 6-5

6.2.3 SAI Transmit Section Overview . . . . . . . . . . . . . . . . . . . . 6-6

6.3 SERIAL AUDIO INTERFACE PROGRAMMING MODEL. . . 6-8

6.3.1 Baud Rate Control Register (BRC). . . . . . . . . . . . . . . . . . 6-9

6.3.1.1 Prescale Modulus select (PM[7:0])—Bits 7–0 . . . . . . 6-10

6.3.1.2 Prescaler Range (PSR)—Bit 8. . . . . . . . . . . . . . . . . . 6-10

6.3.1.3 BRC Reserved Bits—Bits 15–9 . . . . . . . . . . . . . . . . . 6-10

6.3.2 Receiver Control/Status Register (RCS) . . . . . . . . . . . . 6-10

6.3.2.1 RCS Receiver 0 Enable (R0EN)—Bit 0. . . . . . . . . . . 6-10

6.3.2.2 RCS Receiver 1 Enable (R1EN)—Bit 1. . . . . . . . . . . 6-11

6.3.2.3 RCS Reserved Bit—Bits 13 and 2. . . . . . . . . . . . . . . 6-11

6.3.2.4 RCS Receiver Master (RMST)—Bit 3 . . . . . . . . . . . . 6-11

6.3.2.5 RCS Receiver Word Length Control (RWL[1:0])—Bits 4 and 5 6-11

6.3.2.6 RCS Receiver Data Shift Direction (RDIR)—Bit 6. . . 6-12

6.3.2.7 RCS Receiver Left Right Selection (RLRS)—Bit 7 . . 6-12

6.3.2.8 RCS Receiver Clock Polarity (RCKP)—Bit 8. . . . . . . 6-13

6.3.2.9 RCS Receiver Relative Timing (RREL)—Bit 9. . . . . . 6-13

viii Motorola

6.3.2.10 RCS Receiver Data Word Truncation (RDWT)—Bit 106-14

6.3.2.11 RCS Receiver Interrupt Enable (RXIE)—Bit 11. . . . . 6-15

6.3.2.12 RCS Receiver Interrupt Location (RXIL)—Bit 12. . . . 6-15

6.3.2.13 RCS Receiver Left Data Full (RLDF)—Bit 14 . . . . . . 6-16

6.3.2.14 RCS Receiver Right Data Full (RRDF)—Bit 15. . . . . 6-16

6.3.3 SAI Receive Data Registers (RX0 and RX1) . . . . . . . . . 6-17

6.3.4 Transmitter Control/Status Register (TCS). . . . . . . . . . . 6-17

6.3.4.1 TCS Transmitter 0 Enable (T0EN)—Bit 0 . . . . . . . . . 6-17

6.3.4.2 TCS Transmitter 1 Enable (T1EN)—Bit 1 . . . . . . . . . 6-17

6.3.4.3 TCS Transmitter 2 Enable (T2EN)—Bit 2 . . . . . . . . . 6-18

6.3.4.4 TCS Transmitter Master (TMST)—Bit 3. . . . . . . . . . . 6-18

6.3.4.5 TCS Transmitter Word Length Control (TWL[1:0])—Bits 4 & 5 6-18

6.3.4.6 TCS Transmitter Data Shift Direction (TDIR)—Bit 6 . 6-18

6.3.4.7 TCS Transmitter Left Right Selection (TLRS)—Bit 7. 6-19

6.3.4.8 TCS Transmitter Clock Polarity (TCKP)—Bit 8 . . . . . 6-19

6.3.4.9 TCS Transmitter Relative Timing (TREL)—Bit 9 . . . . 6-20

6.3.4.10 TCS Transmitter Data Word Expansion (TDWE)—Bit 106-20

6.3.4.11 TCS Transmitter Interrupt Enable (TXIE)—Bit 11 . . . 6-21

6.3.4.12 TCS Transmitter Interrupt Location (TXIL)—Bit 12 . . 6-22

6.3.4.13 TCS Reserved Bit—Bit 13 . . . . . . . . . . . . . . . . . . . . . 6-22

6.3.4.14 TCS Transmitter Left Data Empty (TLDE)—Bit 14 . . 6-22

6.3.4.15 TCS Transmitter Right Data Empty (TRDE)—Bit 15 . 6-23

6.3.5 SAI Transmit Data Registers (TX2, TX1 and TX0). . . . . 6-23

6.4 PROGRAMMING CONSIDERATIONS. . . . . . . . . . . . . . . . 6-24

6.4.1 SAI Operation During Stop. . . . . . . . . . . . . . . . . . . . . . . 6-24

6.4.2 Initiating a Transmit Session . . . . . . . . . . . . . . . . . . . . . 6-24

6.4.3 Using a Single Interrupt to Service Both Receiver and

Transmitter Sections6-24

6.4.4 SAI State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25

7.1 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3

7.2 GPIO PROGRAMMING MODEL . . . . . . . . . . . . . . . . . . . . . 7-3

7.3 GPIO REGISTER (GPIOR). . . . . . . . . . . . . . . . . . . . . . . . . . 7-3

7.3.1 GPIOR Data Bits (GD[7:0])—Bits 7–0 . . . . . . . . . . . . . . . 7-4

7.3.2 GPIOR Data Direction Bits (GDD[7:0])—Bits 15–8 . . . . . 7-4

7.3.3 GPIOR Control Bits (GC[7:0])—Bits 23–16 . . . . . . . . . . . 7-4

8.1 OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3

8.2 DAX SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4

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8.3 DAX FUNCTIONAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . 8-5

8.4 DAX PROGRAMMING MODEL . . . . . . . . . . . . . . . . . . . . . . 8-6

8.5 DAX INTERNAL ARCHITECTURE. . . . . . . . . . . . . . . . . . . . 8-6

8.5.1 DAX Audio Data Registers A and B (XADRA/XADRB) . . 8-7

8.5.2 DAX Audio Data Buffer (XADBUF). . . . . . . . . . . . . . . . . . 8-7

8.5.3 DAX Audio Data Shift Register (XADSR). . . . . . . . . . . . . 8-8

8.5.4 DAX Control Register (XCTR) . . . . . . . . . . . . . . . . . . . . . 8-8

8.5.4.1 DAX Enable (XEN)—Bit 0 . . . . . . . . . . . . . . . . . . . . . . 8-8

8.5.4.2 DAX Interrupt Enable (XIEN)—Bit 1 . . . . . . . . . . . . . . 8-8

8.5.4.3 DAX Stop Control (XSTP)—Bit 2. . . . . . . . . . . . . . . . . 8-8

8.5.4.4 DAX Clock Input Select (XCS[1:0])—Bits 3–4. . . . . . . 8-9

8.5.4.5 XCTR Reserved Bits—Bits 5-9, 16-23. . . . . . . . . . . . . 8-9

8.5.4.6 DAX Channel A Validity (XVA)—Bit 10 . . . . . . . . . . . . 8-9

8.5.4.7 DAX Channel A User Data (XUA)—Bit 11. . . . . . . . . . 8-9

8.5.4.8 DAX Channel A Channel Status (XCA)—Bit 12. . . . . . 8-9

8.5.4.9 DAX Channel B Validity (XVB)—Bit 13 . . . . . . . . . . . . 8-9

8.5.4.10 DAX Channel B User Data (XUB)—Bit 14. . . . . . . . . 8-10

8.5.4.11 DAX Channel B Channel Status (XCB)—Bit 15. . . . . 8-10

8.5.5 DAX Status Register (XSTR) . . . . . . . . . . . . . . . . . . . . . 8-10

8.5.5.1 DAX Audio Data Register Empty (XADE)—Bit 0. . . . 8-10

8.5.5.2 XSTR Reserved Bits—Bits 1, 5–23 . . . . . . . . . . . . . . 8-10

8.5.5.3 DAX Transmit Underrun Error Flag (XAUR)—Bit 2 . . 8-10

8.5.5.4 DAX Block Transfer Flag (XBLK)—Bit 3 . . . . . . . . . . 8-11

8.5.5.5 DAX Transmit In Progress (XTIP)—Bit 4. . . . . . . . . . 8-11

8.5.6 DAX Non-Audio Data Buffer (XNADBUF) . . . . . . . . . . . 8-12

8.5.7 DAX Parity Generator (PRTYG). . . . . . . . . . . . . . . . . . . 8-12

8.5.8 DAX Biphase Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12

8.5.9 DAX Preamble Generator. . . . . . . . . . . . . . . . . . . . . . . . 8-12

8.5.10 DAX Clock Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13

8.5.11 DAX State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14

8.6 DAX PROGRAMMING CONSIDERATIONS . . . . . . . . . . . 8-14

8.6.1 Initiating A Transmit Session . . . . . . . . . . . . . . . . . . . . . 8-14

8.6.2 Transmit Register Empty Interrupt Handling . . . . . . . . . 8-14

8.6.3 Block Transferred Interrupt Handling . . . . . . . . . . . . . . . 8-14

8.6.4 DAX Operation During Stop . . . . . . . . . . . . . . . . . . . . . . 8-15

A.1 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3

A.2 BOOTSTRAPPING THE DSP. . . . . . . . . . . . . . . . . . . . . . . . A-3

A.3 BOOTSTRAP PROGRAM LISTING . . . . . . . . . . . . . . . . . . . A-4

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B.1 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3

B.2 PERIPHERAL ADDRESSES . . . . . . . . . . . . . . . . . . . . . . . . B-3

B.3 INTERRUPT ADDRESSES . . . . . . . . . . . . . . . . . . . . . . . . . B-3

B.4 INTERRUPT PRIORITIES . . . . . . . . . . . . . . . . . . . . . . . . . . B-3

B.5 INSTRUCTION SET SUMMARY . . . . . . . . . . . . . . . . . . . . . B-3

B.6 PROGRAMMING SHEETS. . . . . . . . . . . . . . . . . . . . . . . . . . B-3

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xii Motorola

List of Figures

Figure 1-1 DSP56012 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9

Figure 2-1 DSP56012 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

Figure 3-1 Memory Maps for PEA = 0, PEB = 0. . . . . . . . . . . . . . . . . . . . . . 3-5

Figure 3-2 Memory Maps for PEA = 1, PEB = 0. . . . . . . . . . . . . . . . . . . . . . 3-6

Figure 3-3 Memory Maps for PEA = 0, PEB = 1. . . . . . . . . . . . . . . . . . . . . . 3-7

Figure 3-4 Memory Maps for PEA = 1, PEB = 1. . . . . . . . . . . . . . . . . . . . . . 3-8

Figure 3-5 Operating Mode Register (OMR) . . . . . . . . . . . . . . . . . . . . . . . 3-12

Figure 3-6 Interrupt Priority Register (Addr X:$FFFF) . . . . . . . . . . . . . . . . 3-16

Figure 3-7 PLL Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20

Figure 4-1 Port B Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

Figure 4-2 Parallel Port B Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

Figure 4-3 Port B GPIO Signals and Registers . . . . . . . . . . . . . . . . . . . . . . 4-5

Figure 4-4 Port B I/O Pin Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

Figure 4-5 Instructions to Write/Read Parallel Data with Port B. . . . . . . . . . 4-8

Figure 4-6 I/O Port B Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

Figure 4-7 HI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12

Figure 4-8 HI Programming Model–DSP Viewpoint . . . . . . . . . . . . . . . . . . 4-14

Figure 4-9 HI Flag Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18

Figure 4-10 Host Processor Programming Model–Host Side. . . . . . . . . . . . 4-23

Figure 4-11 HI Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24

Figure 4-12 HSR and HCR Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26

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Figure 4-13 Command Vector Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-29

Figure 4-14 Host Processor Transfer Timing. . . . . . . . . . . . . . . . . . . . . . . . .4-37

Figure 4-15 Interrupt Vector Register Read Timing . . . . . . . . . . . . . . . . . . . .4-40

Figure 4-16 HI Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-40

Figure 4-17 DMA Transfer Logic and Timing. . . . . . . . . . . . . . . . . . . . . . . . .4-41

Figure 4-18 HI Initialization Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-42

Figure 4-19 HI Initialization—DSP Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-43

Figure 4-20 HI Initialization—Host Side, Interrupt Mode . . . . . . . . . . . . . . . .4-44

Figure 4-21 HI Mode and INIT Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-45

Figure 4-22 HI Initialization—Host Side, Polling Mode. . . . . . . . . . . . . . . . . .4-46

Figure 4-23 HI Configuration—Host Side. . . . . . . . . . . . . . . . . . . . . . . . . . . .4-46

Figure 4-24 HI Initialization–Host Side, DMA Mode. . . . . . . . . . . . . . . . . . . .4-47

Figure 4-25 Bits Used for Host-to-DSP Transfer . . . . . . . . . . . . . . . . . . . . . .4-48

Figure 4-26 Data Transfer from Host to DSP. . . . . . . . . . . . . . . . . . . . . . . . .4-50

Figure 4-27 Host Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-52

Figure 4-28 Receive Data from Host—Main Program . . . . . . . . . . . . . . . . . .4-53

Figure 4-29 Receive Data from Host Interrupt Routine . . . . . . . . . . . . . . . . .4-53

Figure 4-30 Transmit/Receive Byte Registers . . . . . . . . . . . . . . . . . . . . . . . .4-54

Figure 4-31 Bootstrap Using the Host Interface. . . . . . . . . . . . . . . . . . . . . . .4-55

Figure 4-32 Bits Used for DSP to Host Transfer . . . . . . . . . . . . . . . . . . . . . .4-57

Figure 4-33 Data Transfer from DSP to Host. . . . . . . . . . . . . . . . . . . . . . . . .4-58

Figure 4-34 Main Program: Transmit 24-bit Data to Host . . . . . . . . . . . . . . .4-59

Figure 4-35 HI Hardware–DMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-60

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Figure 4-36 DMA Transfer and HI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . .4-61

Figure 4-37 Host to DSP DMA Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . .4-63

Figure 5-1 Serial Host Interface Block Diagram. . . . . . . . . . . . . . . . . . . . . . .5-4

Figure 5-2 SHI Clock Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-5

Figure 5-3 SHI Programming Model—Host Side . . . . . . . . . . . . . . . . . . . . . .5-5

Figure 5-4 SHI Programming Model—DSP Side . . . . . . . . . . . . . . . . . . . . . .5-6

Figure 5-5 SHI I/O Shift Register (IOSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-8

Figure 5-6 SPI Data-To-Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . .5-10

Figure 5-7 I Figure 5-8 I Figure 5-9 Acknowledgment on the I Figure 5-10 I Figure 5-11 I

C Bit Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-20

C Start and Stop Events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-21

C Bus . . . . . . . . . . . . . . . . . . . . . . . .5-21

C Bus Protocol For Host Write Cycle. . . . . . . . . . . . . . . . . . . .5-22

C Bus Protocol For Host Read Cycle. . . . . . . . . . . . . . . . . . . .5-22

Figure 6-1 SAI Baud-Rate Generator Block Diagram . . . . . . . . . . . . . . . . . .6-4

Figure 6-2 SAI Receive Section Block Diagram. . . . . . . . . . . . . . . . . . . . . . .6-5

Figure 6-3 SAI Transmit Section Block Diagram . . . . . . . . . . . . . . . . . . . . . .6-7

Figure 6-4 SAI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-8

Figure 6-5 Receiver Data Shift Direction (RDIR) Programming. . . . . . . . . .6-12

Figure 6-6 Receiver Left/Right Selection (RLRS) Programming . . . . . . . . .6-12

Figure 6-7 Receiver Clock Polarity (RCKP) Programming. . . . . . . . . . . . . .6-13

Figure 6-8 Receiver Relative Timing (RREL) Programming . . . . . . . . . . . .6-14

Figure 6-9 Receiver Data Word Truncation (RDWT) Programming. . . . . . .6-14

Figure 6-10 Transmitter Data Shift Direction (TDIR) Programming . . . . . . . .6-19

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Figure 6-11 Transmitter Left/Right Selection (TLRS) Programming . . . . . . .6-19

Figure 6-12 Transmitter Clock Polarity (TCKP) Programming. . . . . . . . . . . .6-20

Figure 6-13 Transmitter Relative Timing (TREL) Programming. . . . . . . . . . .6-20

Figure 6-14 Transmitter Data Word Expansion (TDWE) Programming. . . . .6-21

Figure 7-1 GPIO Control/Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-3

Figure 7-2 GPIO Circuit Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-5

Figure 8-1 Digital Audio Transmitter (DAX) Block Diagram . . . . . . . . . . . . . .8-4

Figure 8-2 DAX Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-7

Figure 8-3 DAX Relative Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-11

Figure 8-4 Preamble sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-13

Figure 8-5 Clock Multiplexer Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-13

Figure B-1 On-chip Peripheral Memory Map . . . . . . . . . . . . . . . . . . . . . . . . B-4

xvi Motorola

List of Tables

Table 1-1 High True / Low True Signal Conventions. . . . . . . . . . . . . . . . . . 1-6

Table 1-2 DSP56012 Internal Memory Configurations . . . . . . . . . . . . . . . . 1-7

Table 1-3 Interrupt Starting Addresses and Sources . . . . . . . . . . . . . . . 1-13

Table 1-4 Internal Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . 1-15

Table 1-5 On-chip Peripheral Memory Map . . . . . . . . . . . . . . . . . . . . . . . 1-17

Table 2-1 DSP56012 Functional Signal Groupings . . . . . . . . . . . . . . . . . . 2-3

Table 2-2 Power Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

Table 2-3 Grounds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

Table 2-4 Phase Lock Loop Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

Table 2-5 Interrupt and Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8

Table 2-6 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10

Table 2-7 Serial Host Interface (SHI) Signals . . . . . . . . . . . . . . . . . . . . . 2-13

Table 2-8 Serial Audio Interface (SAI) Receive Signals . . . . . . . . . . . . . . 2-16

Table 2-9 Serial Audio Interface (SAI) Transmit Signals. . . . . . . . . . . . . . 2-17

Table 2-10 General Purpose I/O (GPIO) Signals . . . . . . . . . . . . . . . . . . . . 2-18

Table 2-11 Digital Audio Interface (DAX) Signals . . . . . . . . . . . . . . . . . . . . 2-18

Table 2-12 On-Chip Emulation Port (OnCE) Signals . . . . . . . . . . . . . . . . 2-19

Table 3-1 Internal Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

Table 3-2 Internal I/O Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

Table 3-3 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13

Table 3-4 Interrupt Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16

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Table 3-5 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-17

Table 4-1 HI Registers after Reset—DSP CPU Side . . . . . . . . . . . . . . . .4-19

Table 4-2 HOREQ Pin Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-25

Table 4-3 HI Mode Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-26

Table 4-4 HOREQ Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-28

Table 4-5 HI Registers after Reset (Host Side) . . . . . . . . . . . . . . . . . . . . .4-34

Table 4-6 Port B Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-36

Table 5-1 SHI Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-7

Table 5-2 SHI Internal Interrupt Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . .5-7

Table 5-3 SHI Noise Reduction Filter Mode . . . . . . . . . . . . . . . . . . . . . . . .5-12

Table 5-4 SHI Data Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-14

Table 5-5 HREQ Function In SHI Slave Modes . . . . . . . . . . . . . . . . . . . . .5-15

Table 5-6 HCSR Receive Interrupt Enable Bits . . . . . . . . . . . . . . . . . . . .5-17

Table 6-1 SAI Interrupt Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . .6-9

Table 6-2 SAI Internal Interrupt Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . .6-9

Table 6-3 Receiver Word Length Control . . . . . . . . . . . . . . . . . . . . . . . . . .6-11

Table 6-4 Transmitter Word Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-18

Table 7-1 GPIO Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-4

Table 8-1 DAX Interrupt Vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-6

Table 8-2 DAX Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-6

Table 8-3 Clock Source Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-9

Table 8-4 Preamble Bit Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-12

Table B-1 Interrupt Starting Addresses and Sources . . . . . . . . . . . . . . . . . B-5

xviii Motorola

Table B-2 Interrupt Priorities Within an IPL . . . . . . . . . . . . . . . . . . . . . . . . B-6

Table B-3 Instruction Set Summary (Sheet 1 of 7). . . . . . . . . . . . . . . . . . . B-8

Motorola xix

xx Motorola

SECTION 1

OVERVIEW

MOTOROLA DSP56012 User’s Manual 1-1

Overview

1.1 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1.1.1 Manual Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

1.1.2 Manual Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5

1.2 DSP56012 FEATURES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

1.3 DSP56012 ARCHITECTURAL OVERVIEW . . . . . . . . . . . . . 1-8

1.3.1 Peripheral Modules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

1.3.2 DSP Core Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10

1.3.3 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13

1.3.4 Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16

1-2 DSP56012 User’s Manual MOTOROLA

Overview

Introduction

1.1 INTRODUCTION

This manual describes in detail the DSP56012 24-bit Digital Signal Processor (DSP), its memory, operating modes, and peripheral modules. This manual is intended to be used with the

Technical Data

Processing Unit (CPU), programming models, and the instruction set. The data sheet provides electrical specifications, timing, pinouts, and packaging descriptions. These documents, as well as Motorola’s DSP development tools, can be obtained through a local Motorola Semiconductor Sales Office or authorized distributor.

To receive the latest information, access the Motorola DSP home page located at

http://www.motorola-dsp.com

DSP56000 Family Manual

sheet (DSP56012/D). The family manual describes the Central

(DSP56KFAMUM/AD) and the

DSP56012

The DSP56012 is a high-performance programmable DSP specifically developed for Digital Versatile Disk (DVD), High-Definition Television (HDTV), and advanced set-top audio decoding. Flexible peripheral modules and interface software allow simple connection to a wide variety of video and audio system decoders. The memory configuration and peripherals differentiate this DSP from the other 56000 family members. The DSP56012 also provides the following on-chip peripherals to support its target applications:

• Parallel Host Interface (HI)— a byte-wide parallel port with Direct Memory

Access (DMA) support

Serial Host Interface (SHI) —simple communications and control interface

• between a host processor and the DSP

Serial Audio Interface (SAI) —user-programmable interface that provides

• support for a wide variety of serial audio formats to support a number of standard audio devices

Dedicated General Purpose Input/Output (GPIO) Signals —eight additional

• individually controlled input or output signals

Digital Audio Transmitter (DAX) —outputs digital audio data in AES/EBU,

• CP-340, and IEC958 formats

The DSP56012 has the power and ease-of-programming required for stand-alone, embedded applications. The versatile, on-board peripherals allow the DSP to be connected easily to almost any other processor with little or no additional logic.

MOTOROLA DSP56012 User’s Manual 1-3

Overview Introduction

1.1.1 Manual Organization

This manual includes the following sections:

•

Section 1—Overview furnishes a description of the manual organization and

provides a brief description of the DSP56012.

Section 2—Signal Descriptions describes the DSP56012 signals and signal

• groupings.

Section 3—Memory, Operating Modes, and Interrupts describes the internal

• memory organization, operating modes, interrupt processing, and chip initialization during hardware reset.

Section 4—Parallel Host Interface describes the parallel Host Interface (HI) port,

• its registers, and its controls.

Section 5—Serial Host Interface describes the operation, registers, and control of

• the Serial Host Interface (SHI).

Section 6—Serial Audio Interface describes the operation of the Serial Audio

• Interface (SAI), its registers, and its controls.

Section 7—Digital Audio Transmitter describes the Digital Audio Transmitter

• (DAX) functionality, architecture, registers, and programming considerations.

Section 8—Serial Audio Interface describes the operation of the Serial Audio

• Interface (SAI), its registers, and its controls.

Appendix A—Bootstrap Code Listings lists the code used to bootstrap the

• DSP56012.

Appendix B—Programming Reference provides a quick reference for the

• instructions and registers used by the DSP56012. These sheets are provided with the expectation that they be photocopied and used by programmers when programming the registers.

1-4 DSP56012 User’s Manual MOTOROLA

Overview

Introduction

1.1.2 Manual Conventions

The following conventions are used in this manual:

• The word “reset” is used in three different contexts in this manual. There is a reset pin that is always written as “RESET”, there is a reset instruction that is always written as “RESET”, and the word reset, used to refer to the reset function, is written in lower case (with a leading capital letter as grammar dictates.)

• Bits within a register are indicated AA[n:0] when more than one bit is involved in a description. For purposes of description, the bits are presented as if they are contiguous within the register; however, this is not always the case. Refer to the programming model diagrams or to the programming sheets to see the exact location of bits within a register.

• When a bit is described as “set”, its value is 1. When a bit is described as “cleared”, its value is 0.

• Hex (hexadecimal) values are indicated with a dollar sign ($) preceding the hex value, as in “$FFFB is the X memory address for the Interrupt Priority Register (IPR).”

• Code examples are displayed in a monospaced font, as shown in

Example 1-1

Example 1-1 Sample Code Listing

movep #0,x:EOR0 ; drive 2nd read trigger

bset #ERTS,x:ECSR ; set read triggers by reading EDDR

do #(N-2),end_OL ; loop to drive more (N-2) triggers

• Pins or signals listed in code examples that are asserted low have a tilde (~) in front of their names.

• The word “assert” means that a high true (active high) signal is pulled high (to

) or that a low true (active low) signal is pulled low (to ground).

• The word “deassert” means that a high true signal is pulled low (to ground) or that a low true signal is pulled high (to V

• Overbars are used to indicate a signal that is active when pulled to ground (see Table 1-1 Therefore, references to the RESET

). For example, the RESET pin is active when pulled to ground.

pin will always have an overbar. Such pins

and signals are also said to be “active low” or “low true.”

MOTOROLA DSP56012 User’s Manual 1-5

Overview DSP56012 Features

Table 1-1 High True / Low True Signal Conventions

Signal/Symbol Logic State Signal State Voltage

Notes: 1. PIN is a generic term for any pin on the device.

2. Ground is an acceptable low voltage level. See the appropriate data sheet for the range of acceptable low voltage levels (typically a TTL logic low).

3. V

is an acceptable high voltage level. See the appropriate data sheet for the range of

acceptable high voltage levels (typically a TTL logic high).

True Asserted

False Deasserted

True Asserted

False Deasserted

1.2 DSP56012 FEATURES

• Digital Signal Processing Core – Efficient, object-code compatible, 24-bit DSP56000 family DSP engine

Ground

– 40.5 Million Instructions Per Second (MIPS)—24.69 ns instruction cycle at

81 MHz – Highly parallel instruction set with unique DSP addressing modes – Two 56-bit accumulators including extension byte – Parallel 24 ×

24-bit multiply-accumulate in 1 instruction cycle (2 clock

cycles) – Double precision 48 ×

48-bit multiply with 96-bit result in 6 instruction

cycles – 56-bit addition/subtraction in 1 instruction cycle – Fractional and integer arithmetic with support for multi-precision

arithmetic – Hardware support for block-floating point Fast Fourier Transforms (FFT) – Hardware nested DO loops – Zero-overhead fast interrupts (2 instruction cycles)

1-6 DSP56012 User’s Manual MOTOROLA

Overview

DSP56012 Features

– PLL-based clocking with a wide range of frequency multiplications (1 to

4096) and power saving clock divider (2

: i = 0 to 15), which reduces clock

noise

– Four 24-bit internal data buses and three 16-bit internal address buses for

simultaneous accesses to one program and two data memories

• Memory – Modified Harvard architecture allows simultaneous access to program and

data memories

– 15360 ×

24-bit on-chip Program ROM1

– 4096 × 24-bit on-chip X-data RAM and 3584 × 24-bit on-chip X-data ROM* – 4352 × 24-bit on-chip Y-data RAM and 2048 × 24-bit on-chip Y-data ROM* – 256 × 24-bit on-chip Program RAM and 32 × 24-bit bootstrap ROM – As much as 2304 × 24 bits of X- and Y-data RAM can be switched to

Program RAM, giving a total of 2560 × 24 bits of Program RAM

Table 1-2 lists the memory configurations of the DSP56012.

Table 1-2 DSP56012 Internal Memory Configurations

No Switch

(PEA=0, PEB=0)

P: RAM 0.25 K 1.0 K 1.75 K 2.5 K X: RAM 4.0 K 3.25 K 3.25 K 2.5 K Y: RAM 4.25 K 4.25 K 3.5 K 3.5 K P: ROM 15 K 15 K 15 K 15 K X: ROM 3.5 K 3.5 K 3.5 K 3.5 K Y: ROM 2.0 K 2.0 K 2.0 K 2.0 K

Switch A

(PEA=1, PEB=0)

Switch B

(PEA=0, PEB=1)

(PEA=1, PEB=1)

• Peripheral and Support Circuits – SAI includes:

• Two receivers and three transmitters

• Master or slave capability

S, Sony, and Matshushita audio protocol implementations

•I

Switch A+B

1.These ROMs may be factory programmed with data/program provided by the application developer.

MOTOROLA DSP56012 User’s Manual 1-7

Overview DSP56012 Architectural Overview

• Two sets of SAI interrupt vectors

– SHI features:

• Single master capability

• SPI and I2C protocols

• 10-word receive FIFO

• Support for 8-, 16- and 24-bit words.

– Byte-wide Parallel Host Interface with DMA support capable of

reconfiguration as fifteen General Purpose Input/Output (GPIO) lines

– DAX features one serial transmitter capable of supporting S/PDIF, IEC958,

CP-340, and AES/EBU formats. – Eight dedicated, independent, programmable GPIO lines – On-chip peripheral registers memory mapped in data memory space – OnCE™ port for unobtrusive, processor speed-independent debugging – Software programmable PLL-based frequency synthesizer for the core

clock – Power saving Wait and Stop modes – Fully static, HCMOS design for operating frequencies from 81 MHz down

to DC – 100-pin plastic Thin Quad Flat Pack (TQFP) surface-mount package – 5 V power supply

1.3 DSP56012 ARCHITECTURAL OVERVIEW

The DSP56012 is a member of the 24-bit DSP56000 family. The DSP is composed of the 24-bit DSP56000 core, memory, and a set of peripheral modules, as shown in Figure 1-1. The 24-bit DSP56000 core is composed of a Data Arithmetic Logic Unit (ALU), an Address Generation Unit (AGU), a Program Controller, an On-Chip Emulation (OnCE) port, and a PLL designed to allow the DSP to run at full speed while using a low-speed clock. The DSP56000-family architecture, upon which the DSP56012 is built, was designed to maximize throughput in data-intensive digital signal processing applications. The result is a dual-natured, expandable architecture with sophisticated on-chip peripherals and versatile GPIO.

1-8 DSP56012 User’s Manual MOTOROLA

Overview

DSP56012 Architectural Overview

Parallel

Host

Interface

(HI)

24-Bit

DSP56000

Core

Internal

OnCETM Port

Clock

PLL

Gen.

EXTAL

Data Bus

Switch

General Purpose

I/O

(GPIO)

Controller

Interface

Program Interrupt

IRQA

Serial Audio

(SAI)

Address

Generation

Program Control Unit

, IRQB, NMI, RESET

Serial

Host

Interface

(SHI)

Unit

Program

Decode

Controller

5 2

Digital

Audio

Transmitter

(DAX)

GDB PDB XDB

YDB

Generator

Program

Address

PAB XAB YAB

Program

Memory

24 × 24 + 56 → 56-Bit MAC

Two 56-Bit Accumulators

X Data

Memory

Data ALU

16-Bit Bus 24-Bit Bus

Y Data

Memory

Expansion

Area

Figure 1-1 DSP56012 Block Diagram

The DSP56000 core is dual-natured in that there are two independent data memory spaces, two address arithmetic units, and a Data ALU that has two accumulators and two shifter/limiters. The duality of the architecture makes it easier to write software for DSP applications. For example, data is naturally partitioned into coefficient and data spaces for filtering and transformations, and into real and imaginary spaces for performing complex arithmetic.

Note: Although the DSP56000 core has built-in support for external memory

expansion, the DSP56012 does not implement this function. For DSP56012 applications, external memory expansion is a function of the host processor.

The DSP56000 architecture is especially suited for audio applications since its arithmetic operations are executed on 24-bit or 48-bit data words. This is a significant advantage for audio over 16-bit and 32-bit architectures—16-bit DSP architectures have insufficient precision for CD-quality sound, and while 32-bit DSP architectures possess the necessary precision, with extra silicon and cost overhead they are not suitable for high-volume, cost-driven audio applications

MOTOROLA DSP56012 User’s Manual 1-9

Overview DSP56012 Architectural Overview

1.3.1 Peripheral Modules

The following peripheral modules are included on the DSP56012:

• Parallel Host Interface—The Host Interface (HI) provides a byte-wide parallel

interface for parallel data transfer between the DSP56012 and a host processor or another parallel peripheral device. The HI will operate with 8-, 16-, and 24-bit words

• Serial Host Interface (SHI)—The Serial Host Interface provides a fast, yet

simple serial interface to connect the DSP56012 to a host processor or to another serial peripheral device. Two serial protocols are available: the Motorola Serial Peripheral Interface (SPI) bus and the Philips Inter Integrated-circuit Control (I 24-bit words and the receiver contains an optimal 10-word First-In, First-Out (FIFO) register to reduce the receive interrupt rate.

• Serial Audio Interface (SAI)—The SAI provides a synchronous serial

interface that allows the DSP56012 to communicate using a wide range of standard serial data formats used by audio manufacturers at bit rates up to one third the DSP core clock rate (e.g., 27 MHz for an 81 MHz clock). There are three synchronized data transmission lines and two synchronized data reception lines, all of which are double-buffered.

C) bus. The SHI will operate with 8-, 16-, and

• General Purpose Input/Output (GPIO)—The GPIO has eight dedicated

signal lines that can be independently programmed to be inputs, standard TTL outputs, open collector outputs, or disconnected.

• Digital Audio Transmitter (DAX)—The DAX is a serial audio interface

module that outputs digital audio data in AES/EBU, CP-340, and IEC958 formats.

1.3.2 DSP Core Processor

The 24-bit DSP56000 core is composed of a Data ALU, an AGU, a program controller, and the buses that connect them together. The OnCE port and a PLL are integral parts of this processor. Figure 1-1 on page 1-9 illustrates the DSP block diagram, showing the components of the core processor, as well as the peripherals specific to the DSP56012. The following paragraphs present a brief overview of the DSP56000 core processor. For more thorough detail, refer to the

DSP56000 Family Manual

1-10 DSP56012 User’s Manual MOTOROLA

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