Page 1
Freescale Semiconductor, Inc.
SECTION 8
DIGITAL AUDIO TRANSMITTER
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MOTOROLA DSP56011 User’s Manual 8-1
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Digital Audio Transmitter
Freescale Semiconductor, Inc.
8.1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
8.2 DAX SIGNALS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
8.3 DAX FUNCTIONAL OVERVIEW. . . . . . . . . . . . . . . . . . . . . . 8-5
8.4 DAX PROGRAMMING MODEL. . . . . . . . . . . . . . . . . . . . . . . 8-6
8.5 DAX INTERNAL ARCHITECTURE . . . . . . . . . . . . . . . . . . . . 8-6
8.6 DAX PROGRAMMING CONSIDERATIONS. . . . . . . . . . . . 8-14
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8-2 DSP56011 User’s Manual MOTOROLA
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Digital Audio Transmitter
Overview
8.1 OVERVIEW
The Digital Audio Transmitter (DAX) is a serial audio interface module that outputs
digital audio data in the AES/EBU, CP-340 and IEC958 formats. Some of the key
features of the DAX are listed below.
Operates on a frame basis —The DAX can handle one frame (consisting of
•
two sub-frames) of audio and non-audio data at a time.
Double-buffered audio and non-audio data —The DAX data path is
•
double-buffered so the next frame data can be stored in the DAX without
affecting the frame currently being transmitted.
Programmable clock source —Users can select the DAX clock source, and this
•
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selection configures the DAX to operate in Slave or Master mode.
Supports both Master mode and Slave mode in a digital audio network —If
•
the user selects a divided DSP core clock, the DAX will operate in the Master
mode. If the user selects an external clock source, the DAX will operate in the
Slave mode.
cale Semiconductor,
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The accessible DAX registers are all mapped in the X I/O memory space. This allows
programmers to access the DAX using standard instructions and addressing modes.
Interrupts generated by the DAX can be handled with a fast interrupt for cases in
which the non-audio data does not change from frame to frame. When the DAX
interrupt is disabled, it can still be served by a “polling” technique. A block diagram
of the DAX is shown in
Note: The shaded registers in Figure 8-1 are directly accessible by DSP instructions.
Figure 8-1 .
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×
Digital Audio Transmitter
DAX Signals
Freescale Semiconductor, Inc.
Global Data Bus
023
XSTR
XNADBUF
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DAX
State
Machine
Figure 8-1 Digital Audio Transmitter (DAX) Block Diagram
8.2 DAX SIGNALS
The DAX has two signal lines:
•
cale Semiconductor,
DAX Digital Audio Output (ADO) —The ADO pin sends audio and
non-audio data in the AES/EBU, CP340, and IEC958 formats in a biphase
mark format. ADO stays high when the DAX is disabled, and during
hardware reset and software reset.
XCTR
Upload
023
26
C-U-V
MUX
Control
Signals
XADSR
PRTYG
Clocks
DAX
023
023
XADRA
Upload Upload
MUX
Biphase
Encoder
MUX
Preamble
Generator
DAX
Clock
MUX
XADRB
XADBUF
MUX
DSP
Core Clock
023
ADO
ACI
AA0606k
Frees
DAX Clock Input (ACI) —When the DAX clock is configured to be supplied
•
externally, the external clock is applied to the ACI pin. The frequency of the
external clock must be 256 times, 384 times, or 512 times the audio sampling
frequency (256
Fs, 384 × Fs, or 512 × Fs). The ACI pin is high impedance
during hardware reset and software reset.
Note: If the DAX is not used, connect the ACI pin to ground through an external
pull-down resistor to ensure a stable logic level at the input.
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Digital Audio Transmitter
DAX Functional Overview
8.3 DAX FUNCTIONAL OVERVIEW
The DAX consists of:
• Audio Data Register A and Audio Data Register B (XADRA and XADRB), one
for each channel
• Audio Data Buffer (XADBUF)
• Non-Audio Data Buffer (XNADBUF)
• Audio and non-audio Data Shift Register (XADSR)
• Control Register (XCTR)
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• Status Register (XSTR)
• Parity Generator (PRTYG)
• Preamble generator
• Biphase encoder
• Clock multiplexer
• Control state machine
One frame of audio data and non-audio data (stored in XADRA/XADRB and XCTR,
respectively) is transferred to the XADSR (for Channel A) and to the
XADBUF/XNADBUF registers (for Channel B) at the beginning of a frame
transmission. This is called an “upload.” At this time the DAX Audio Data register
Empty (XADE) flag is set, and, if DAX interrupt is enabled, an interrupt request is
sent to the DSP core. The interrupt handling routine then stores the next frame of
audio data in the XADRA/XADRB and the non-audio data bits in the XCTR.
At the beginning of a frame transmission, one of the 8-bit Channel A preambles
(Z-preamble for the first sub-frame in a block, or X-preamble otherwise) is generated
in the preamble generator, and then shifted out to the ADO pin in the first eight time
slots. The preamble is generated in biphase mark format. The twenty-four audio and
three non-audio data bits in the XADSR are shifted out to the biphase encoder, which
shifts them out through the ADO pin in the biphase mark format in the next fifty-four
time slots. The parity generator calculates an even parity over the 27 bits of audio and
non-audio data, and then outputs the result through the biphase encoder to the ADO
pin at the last two time slots. This is the end of the first (Channel A) sub-frame
transmission.
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Digital Audio Transmitter
DAX Programming Model
The second sub-frame transmission (Channel B) starts with the preamble generator
generating the Channel B preamble (Y-preamble). At the same time, Channel B audio
and non-audio data is transferred to the XADSR shift-register from the XADBUF and
XNADBUF registers. The generated Y-preamble is output immediately after the
Channel A parity and is followed by the audio and non-audio data in the XADSR,
which is in turn followed by the calculated parity for Channel B. This completes a
frame transmission. When the Channel B parity is sent, the audio data for the next
frame, stored in the XADRA/XADRB and the non-audio data bits from the XCTR,
are uploaded.
8.4 DAX PROGRAMMING MODEL
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The programmer-accessible DAX registers are shown in Figure 8-2 on page 8-7. The
registers are described in the following subsections. The Interrupt Vector table for the
DAX is shown in
Table 8-1 . The internal interrupt priority is shown in Table 8-2 .
Table 8-1 DAX Interrupt Vectors
Condition Address Description
XADE & XAUR P:$0050 DAX Transmit Underrun Error
XADE & XBLK P:$0052 DAX Block Transferred
XADE P:$0056 DAX Transmit Register Empty
Table 8-2 DAX Interrupt Priority
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Priority Interrupt
highest DAX Transmit Underrun Error
DAX Block Transferred
lowest DAX Transmit Register Empty
8.5 DAX INTERNAL ARCHITECTURE
Hardware components shown in Figure 8-1 on page 8-4 are described in the
following sub-sections. The DAX programming model is illustrated in
8-6 DSP56011 User’s Manual MOTOROLA
Figure 8-2 .
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Digital Audio Transmitter
DAX Internal Architecture
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23
23
15
XCB
XUB14XVB13XCA12XUA
23 0
Reserved bit
1118 17 161920
10
XVA
XADRA
XADRB
36 579
4
XSTP XIEN
XCS0
XCS1
3
47918 17 161920
XAUR
XBLK
XTIP
X:$FFDC
Accessed Alternately
0
122122 8
122122 8
XEN
06 513 12 11 101415
XADE
XCTR
X:$FFDE
XSTR
X:$FFDF
AA0607k
Figure 8-2 DAX Programming Mode
8.5.1 DAX Audio Data Registers A and B (XADRA/XADRB)
XADRA and XADRB are 24-bit write-only registers. One frame of audio data, which
is to be transmitted in the next frame slot, is stored in these registers. The XADRA
and the XADRB are mapped to the same X Memory I/O address. Successive write
accesses to this address will access XADRA and XADRB alternately. When a new
frame transmission starts, write access to the XADRA is enabled to ensure that
accessing the XADRA always occurs first within an interrupt service. When the
XADRB is accessed, the XADE bit in the XSTR is cleared.
8.5.2 DAX Audio Data Buffer (XADBUF)
XADBUF is a 24-bit register that holds Channel B audio data for the current frame
while Channel A audio and non-audio data are being transmitted. At the beginning
of a frame transmission, audio data stored in the XADRA is directly transferred to
the XADSR for Channel A transmission, and at the same time the Channel B audio
data stored in XADRB is transferred to the XADBUF. The Channel B audio data in
the XADBUF is transferred to the XADSR at the beginning of the Channel B
transmission. This double buffering mechanism provides more cycles to write the
next audio data to XADRA and XADRB. This register is not directly accessible by
DSP instructions.
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Digital Audio Transmitter
DAX Internal Architecture
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8.5.3 DAX Audio Data Shift Register (XADSR)
The XADSR is a 27-bit shift register that shifts the 24-bit audio data and the 3-bit
non-audio data for one sub-frame. The contents of XADRA are directly transferred to
the XADSR at the beginning of the frame transmission (at the beginning of the
Channel A sub-frame transmission). At the same time, the three bits of non-audio
data(V-bit, U-bit and C-bit) for Channel A in the DAX control register is transferred
to the three highest-order bits of the XADSR. At the beginning of the Channel B
transmission, audio and non-audio data for Channel B is transferred from the
XADBUF and the XNADBUF to the XADSR for shifting. The data in the XADSR is
shifted toward the lowest-order bit at the fifth to thirty-first bit slot of each sub-frame
transmission. This register is not directly accessible by DSP instructions.
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8.5.4 DAX Control Register (XCTR)
The XCTR is a 24-bit read/write register that controls the DAX operation. It also
holds the three bits of non-audio data for a frame. The contents of the XCTR are
shown in
paragraphs.
8.5.4.1 DAX Enable (XEN)—Bit 0
When the XEN bit is set, the DAX is enabled. If the DAX Stop (XSTP) control bit is set,
XEN is sampled at every frame boundary, thus clearing XEN during the middle of a
frame transmission will stop transmission at the next frame boundary. If XSTP is
cleared, clearing XEN stops the DAX immediately (individual reset).
Note: This bit is cleared by software reset and hardware reset.
cale Semiconductor,
8.5.4.2 DAX Interrupt Enable (XIEN)—Bit 1
When the XIEN bit is set, the DAX interrupt is enabled and sends an interrupt
request signal to the DSP if the XADE status bit is set. When this bit is cleared, the
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DAX interrupt is disabled.
Note: This bit is cleared by software reset and hardware reset.
8.5.4.3 DAX Stop Control (XSTP)—Bit 2
The XSTP bit selects how the DAX is disabled. When this bit is cleared, disabling the
DAX (by clearing XEN) stops the frame transmission immediately. When this bit is
set, disabling the DAX is done at the next frame boundary after finishing the current
frame transmission.
Figure 8-2 on page 8-7. The XCTR bits are described in the following
Note: This bit is cleared by software reset and hardware reset.
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Digital Audio Transmitter
DAX Internal Architecture
8.5.4.4 DAX Clock Input Select (XCS[1:0])—Bits 3–4
The XCS[1:0] bits select the source of the DAX clock and/or its frequency. Table 8-3
shows the configurations selected by these bits. These bits should be changed only
when the DAX is disabled.
Table 8-3 Clock Source Selection
XCS1 XCS0 DAX Clock Source
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00
01
10
11
DSP Core Clock (f = 1024
ACI Pin, f = 256
ACI Pin, f = 384
ACI Pin, f = 512
×
×
×
fs
fs
fs
×
fs)
Note: The XCS bits are cleared by software reset and hardware reset.
8.5.4.5 XCTR Reserved Bits—Bits 5-9, 16-23
These XCTR bits are reserved and unused. They read as 0s and should be written
with 0s for future compatibility.
8.5.4.6 DAX Channel A Validity (XVA)—Bit 10
The value of the XVA bit is transmitted as the twenty-ninth bit (Bit 28) of Channel A
sub-frame in the next frame.
Note: This bit is not affected by any of the DAX reset states.
8.5.4.7 DAX Channel A User Data (XUA)—Bit 11
The value of the XUA bit is transmitted as the thirtieth bit (Bit 29) of the Channel A
sub-frame in the next frame.
Note: This bit is not affected by any of the DAX reset states.
8.5.4.8 DAX Channel A Channel Status (XCA)—Bit 12
The value of the XCA bit is transmitted as the thirty-first bit (Bit 30) of the Channel A
sub-frame in the next frame.
Note: This bit is not affected by any of the DAX reset states.
8.5.4.9 DAX Channel B Validity (XVB)—Bit 13
The value of the XVB bit is transmitted as the twenty-ninth bit (Bit 28) of the Channel
B sub-frame in the next frame.
Note: This bit is not affected by any of the DAX reset states.
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Digital Audio Transmitter
DAX Internal Architecture
8.5.4.10 DAX Channel B User Data (XUB)—Bit 14
The value of the XUB bit is transmitted as the thirtieth bit (Bit 29) of the Channel B
sub-frame in the next frame.
Note: This bit is not affected by any of the DAX reset states.
8.5.4.11 DAX Channel B Channel Status (XCB)—Bit 15
The value of the XCB bit is transmitted as the thirty-first bit (Bit 30) of the Channel B
sub-frame in the next frame.
Note: This bit is not affected by any of the DAX reset states.
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8.5.5 DAX Status Register (XSTR)
I
The XSTR is a 24-bit read-only register that contains the DAX status flags. The
contents of the XSTR are shown in
described in the following paragraphs.
8.5.5.1 DAX Audio Data Register Empty (XADE)—Bit 0
When cleared, the XADE status flag indicates that the DAX audio data registers are
empty (and ready to receive the next audio data). This bit is set at the beginning of
every frame transmission (more precisely, when an audio data upload from the
XADRA/XADRB to XADSR/XADBUF occurs). When XADE is set and the DAX
interrupt is enabled (XIEN = 1), a DAX interrupt request with the Transmit Data
Empty interrupt vector is sent to the DSP core.
Note: XADE is cleared by writing data to XADRA and XADRB. It is cleared by
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8.5.5.2 XSTR Reserved Bits—Bits 1, 5–23
These XSTR bits are reserved and unused. They read as 0s, and should be written
Frees
with 0s to ensure compatibility with future device versions.
8.5.5.3 DAX Transmit Underrun Error Flag (XAUR)—Bit 2
The XAUR status flag is set when the DAX audio data registers (XADRA/XADRB)
are empty (XADE = 1) and the next audio data upload occurs. When a DAX
underrun error occurs, the previous data will be re-transmitted. This bit alone does
not cause any interrupts. However, it causes a change in the interrupt vector that is
sent to DSP core, if an interrupt is generated. This allows programmers to write an
exception handling routine for this special case.
software reset and hardware reset, and by the Stop state.
Figure 8-2 on page 8-7. The XSTR bits are
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Digital Audio Transmitter
DAX Internal Architecture
Note: The XAUR bit is cleared by reading the XSTR register with XAUR set,
followed by writing data to XADRA and XADRB. It is also cleared by software
reset and hardware reset, and by the Stop state.
8.5.5.4 DAX Block Transfer Flag (XBLK)—Bit 3
The XBLK flag indicates that the frame being transmitted is the last frame in a block.
This bit is set at the beginning of the transmission of the last frame (the 191st frame).
This bit does not cause any interrupt. However, it causes a change in the interrupt
vector sent to DSP core in the event of an interrupt, so that a different interrupt
routine can be called (providing the next non-audio data structures for the next block
as well as storing audio data for the next frame). Writing to XADRA and XADRB
clears this bit.
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Note: Software reset, hardware reset, and the Stop state clear XBLK.
The relative timing of transmit frames and XADE and XBLK flags is shown in
Figure 8-3 on page 8-11.
#000 #001 #008#007#006#005#004#003#002 #009 #010 #021#011 #018#017#016#015#014#013#012 #019 #020 #022 #023
Frame
XADE
XBLK
Frame
#024 #025 #032#031#030#029#028#027#026 #033 #034 #045#035 #042#041#040#039#038#037#036 #043 #044 #046 #047
XADE
XBLK
Frame
#168 #169 #176#175#174#173#172#171#170 #177 #178 #189#179 #186#185#184#183#182#181#180 #187 #188 #190 #191
XADE
XBLK
AA0608
Figure 8-3 DAX Relative Timing
8.5.5.5 DAX Transmit In Progress (XTIP)—Bit 4
The XTIP status flag indicates that the DAX is enabled and transmitting data. When
XTIP is set, it indicates that the DAX is active. When XTIP is cleared, it indicates that
the DAX is inactive. This bit provides programmers with the means to determine
whether the DAX is active or inactive. Since the DAX can be active and transmitting
data even after the XEN bit in the XCTR has been cleared (with XSTP = 1), it can be
necessary to know when the DAX actually becomes inactive. This bit is set a moment
after the DAX is enabled (XEN = 1). It is cleared either immediately (by clearing the
XEN bit, when XSTP = 0), or it is cleared at the next frame boundary (if XSTP = 1).
Note: Software reset, hardware reset, and the Stop state clear XTIP immediately.
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DAX Internal Architecture
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8.5.6 DAX Non-Audio Data Buffer (XNADBUF)
The XNADBUF is a 3-bit register that temporarily holds Channel B non-audio data
(XVB, XUB and XCB) for the current transmission while the Channel A data is being
transmitted. This mechanism provides programmers more instruction cycles to store
the next frame’s non-audio data to the XCB, XUB, XVB, XCA, XUA and XVA bits in
the XCTR. The data in the XNADBUF register is transferred to the XADSR along with
the contents of the XADBUF register at the beginning of Channel B transmission.
Note: The XNADBUF register is not directly accessible by DSP instructions.
8.5.7 DAX Parity Generator (PRTYG)
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The PRTYG generates the parity bit for the sub-frame being transmitted. The
generated parity bit ensures that sub-frame bits four to thirty-one will carry an even
number of 1s and 0s.
8.5.8 DAX Biphase Encoder
The DAX biphase encoder encodes each audio and non-audio bit into its biphase
mark format, and shifts this encoded data out to the ADO output pin synchronous to
the biphase clock.
8.5.9 DAX Preamble Generator
cale Semiconductor,
The DAX preamble generator automatically generates one of three preambles in the
8-bit preamble shift register at the beginning of each sub-frame transmission, and
Frees
shifts it out. The generated preambles always start with “0”. Bit patterns of
preambles generated in the preamble generator are shown in Table 8-4. The
preamble bits are already in the biphase mark format.
Table 8-4 Preamble Bit Patterns
Preamble Bit Pattern Channel
X 00011101 A
Y 00011011 B
Z 00010111 A (first in block)
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Digital Audio Transmitter
DAX Internal Architecture
There is no programmable control for the preamble selection. The first sub-frame to
be transmitted (immediately after the DAX is enabled) is the beginning of a block,
and therefore it has a “Z” preamble. This is followed by the second sub-frame, which
has an “Y” preamble. After that, “X” and “Y” preambles are transmitted alternately
until the end of the block transfer (192 frames transmitted). See Figure 8-4 for an
illustration of the preamble sequence.
DAX
Enabled
Here
Z Y X Y X Y X Y Z Y X Y
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First Block (384 Sub-frames) Second Block
AA0609k
Figure 8-4 Preamble sequence
8.5.10 DAX Clock Multiplexer
The DAX clock multiplexer selects one of the clock sources and generates the biphase
clock (128 × Fs) and shift clock (64 × Fs). The clock source can be selected from the
following options (see also Section 8.5.4.4 on page 8-9).
• The internal DSP core clock—assumes 1024 × Fs
• DAX clock input pin(ACI)—512 × Fs
• DAX clock input pin(ACI)—384 × Fs
• DAX clock input pin(ACI)—256 × Fs
Figure 8-5 shows how each clock is divided to generate the biphase and bit shift
clocks.
DSP Core Clock
(1024 × Fs)
ACI Pin
{256,384,512} × Fs
MOTOROLA DSP56011 User’s Manual 8-13
1/4
0
MUX
1
MUX
(XCS1 or XCS0)
1/2
1/2
2/3
0
MUX
1
XCS1
1
0
XCS0
Figure 8-5 Clock Multiplexer Diagram
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1/2
Biphase
Clock
(128 × Fs)
Bit Shift
Clock
× Fs)
(64
AA0610
Page 14
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Digital Audio Transmitter
DAX Programming Considerations
Note: For proper operation of the DAX, the DSP core clock frequency must be at
least five times higher than the DAX bit shift clock frequency (64 × Fs).
8.5.11 DAX State Machine
The DAX state machine generates a set of sequencing signals used in the DAX.
8.6 DAX PROGRAMMING CONSIDERATIONS
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8.6.1 Initiating A Transmit Session
To initiate the DAX operation, follow this procedure:
1. Write the audio data in the XADRA/XADRB registers
2. Write the non-audio data and transmit mode to the corresponding bits in the
XCTR register; ensure that the XEN bit remains cleared
3. Set the XEN bit in the XCTR; transmission begins
8.6.2 Transmit Register Empty Interrupt Handling
When the XIEN bit is set and the DAX is active, a Transmit Audio Data register
cale Semiconductor,
Empty interrupt (XADE = 1) is generated once at the beginning of every frame
transmission. Typically, within an XADE interrupt, one frame of audio data to be
transmitted in the next frame is stored in the XADRA and the XADRB by two
consecutive MOVEP instructions within a fast interrupt routine. This clears the
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XADE bit in the XSTR.
8.6.3 Block Transferred Interrupt Handling
An interrupt with the XBLK vector indicates the end of a block transmission and can
require some computation to provide the next non-audio data structures that are to
be transmitted within the next block. Within the routine, the next audio data can be
stored in the XADRA/XADRB registers, and the next non-audio data can also be
stored in the XCTR.
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Digital Audio Transmitter
DAX Programming Considerations
8.6.4 DAX Operation During Stop
The DAX operation cannot continue when the DSP is in the Stop state since no DSP
clocks are active. While the DSP is in the Stop state, the DAX will remain in the
individual reset state and the status flags are initialized as described for resets. No
DAX control bits are affected. It is recommended that the DAX be disabled, by
clearing the XEN bit in the XCTR, before the DSP enters the Stop state.
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Digital Audio Transmitter
DAX Programming Considerations
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