Motorola DSP56009 User Manual

DSP56009

24-Bit Digital Signal Processor

User’s Manual

Motorola, Incorporated
Semiconductor Products Sector
DSP Division
6501 William Cannon Drive West
Austin, TX 78735-8598

This document (and other documents) can be viewed on the World Wide
Web at http://www.motorola-dsp.com.

This manual is one of a set of three documents. You need the following
manuals to have complete product information: Family Manual, User’s
Manual, and Technical Data.

OnCE





is a trademark of Motorola, Inc.

MOTOROLA INC., 1996

Order this document by DSP56009UM/AD

Motorola reserves the right to make changes without further notice to any products
herein to improve reliability, function, or design. Motorola does not assume any
liability arising out of the application or use of any product or circuit described
herein; neither does it convey any license under its patent rights nor the rights of
others. Motorola products are not authorized for use as components in life support
devices or systems intended for surgical implant into the body or intended to
support or sustain life. Buyer agrees to notify Motorola of any such intended end use
whereupon Motorola shall determine availability and suitability of its product or
products for the use intended. Motorola and
Motorola, Inc. Motorola, Inc. is an Equal Employment Opportunity /Affirmative
Action Employer.

are registered trademarks of

OVERVIEW

SIGNAL DESCRIPTIONS

MEMORY, OPERATING MODES, AND INTERRUPTS

EXTERNAL MEMORY INTERFACE

SERIAL HOST INTERFACE

SERIAL AUDIO INTERFACE

1

2

3

4

5

6

GENERAL PURPOSE I/O

BOOTSTRAP CODE CONTENTS

PROGRAMMING REFERENCE

APPLICATION EXAMPLES

INDEX

7

A

B

C

I

1

2

3

4

5

6

OVERVIEW

SIGNAL DESCRIPTIONS

MEMORY, OPERATING MODES, AND INTERRUPTS

EXTERNAL MEMORY INTERFACE

SERIAL HOST INTERFACE

SERIAL AUDIO INTERFACE

7

A

B

C

GENERAL PURPOSE I/O

BOOTSTRAP CODE CONTENTS

PROGRAMMING SHEETS

APPLICATION EXAMPLES

I

INDEX

TABLE OF CONTENTS

SECTION 1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1

1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-3

1.1.1 Manual Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-4

1.1.2 Manual Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5

1.2 DSP56009 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6

1.3 DSP56009 ARCHITECTURAL OVERVIEW . . . . . . . . . . . . .1-8

1.3.1 Memory and Peripheral Modules. . . . . . . . . . . . . . . . . . .1-10

1.3.2 DSP Core Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-10

1.3.2.1 Data Arithmetic and Logic Unit (ALU). . . . . . . . . . . . .1-11

1.3.2.2 Address Generation Unit (AGU) . . . . . . . . . . . . . . . . .1-11

1.3.2.3 Program Control Unit . . . . . . . . . . . . . . . . . . . . . . . . .1-12

1.3.2.4 Data Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-12

1.3.2.5 Address Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-12

1.3.2.6 Phase Lock Loop (PLL). . . . . . . . . . . . . . . . . . . . . . . .1-12

1.3.2.7 On-Chip Emulation (OnCE) Port. . . . . . . . . . . . . . . . .1-13

1.3.3 Memories. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-13

1.3.3.1 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-13

1.3.3.2 X Data Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-15

1.3.3.3 Y Data Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-15

1.3.3.4 On-Chip Memory Configuration Bits . . . . . . . . . . . . . .1-15

1.3.3.5 Bootstrap ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-15

1.3.3.6 External Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-16

1.3.3.7 Reserved Memory Spaces . . . . . . . . . . . . . . . . . . . . .1-16

1.3.4 Input/Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-16

1.3.4.1 External Memory Interface . . . . . . . . . . . . . . . . . . . . .1-18

1.3.4.2 Serial Host Interface (SHI) . . . . . . . . . . . . . . . . . . . . .1-18

1.3.4.3 Serial Audio Interface (SAI). . . . . . . . . . . . . . . . . . . . .1-19

1.3.4.4 General Purpose Input/Output . . . . . . . . . . . . . . . . . .1-19

MOTOROLA DSP56009 User’s Manual iii

SECTION 2 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . 2-1

2.1 SIGNAL GROUPINGS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

2.2 POWER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2.3 GROUND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2.4 CLOCK AND PLL SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.5 EXTERNAL MEMORY INTERFACE (EMI) . . . . . . . . . . . . . . 2-7

2.6 INTERRUPT AND MODE CONTROL. . . . . . . . . . . . . . . . . 2-10

2.7 SERIAL HOST INTERFACE (SHI) . . . . . . . . . . . . . . . . . . . 2-14

2.8 SERIAL AUDIO INTERFACE (SAI). . . . . . . . . . . . . . . . . . . 2-18

2.8.1 SAI Receiver Section . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18

2.8.2 SAI Transmitter Section . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

2.9 GENERAL PURPOSE I/O. . . . . . . . . . . . . . . . . . . . . . . . . . 2-21

2.10 ON-CHIP EMULATION (ONCETM) PORT. . . . . . . . . . . . . . 2-22

SECTION 3 MEMORY, OPERATING MODES,

AND INTERRUPTS. . . . . . . . . . . . . . . . . . . . . . . . . 3-1

3.1 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.2 DSP56009 DATA AND PROGRAM MEMORY . . . . . . . . . . . 3-3

3.2.1 X Data ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

3.2.2 Y Data ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

3.2.3 Program ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

3.2.4 Bootstrap ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

3.2.5 Reserved Memory Spaces . . . . . . . . . . . . . . . . . . . . . . . . 3-5

3.3 DSP56009 DATA AND PROGRAM MEMORY MAPS . . . . . 3-5

3.3.1 Dynamic Switching of Memory Configurations . . . . . . . . . 3-8

3.3.2 Internal I/O Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

3.4 OPERATING MODE REGISTER (OMR). . . . . . . . . . . . . . . 3-11

3.4.1 DSP Operating Mode (MC, MB, MA)—Bits 4, 1, and 0. . 3-11

3.4.2 Program RAM Enable A (PEA)—Bit 2 . . . . . . . . . . . . . . 3-11

3.4.3 Program RAM Enable B (PEB)—Bit 3 . . . . . . . . . . . . . . 3-12

3.4.4 Stop Delay (SD)—Bit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12

3.5 OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12

3.6 INTERRUPT PRIORITY REGISTER. . . . . . . . . . . . . . . . . . 3-14

3.7 PHASE LOCK LOOP (PLL) CONFIGURATION . . . . . . . . . 3-18

3.8 HARDWARE RESET OPERATION. . . . . . . . . . . . . . . . . . . 3-19

iv DSP56009 User’s Manual MOTOROLA

SECTION 4 EXTERNAL MEMORY INTERFACE . . . . . . . . . . . .4-1

4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3

4.1.1 Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-3

4.1.2 EMI Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4

4.2 EMI PROGRAMMING MODEL . . . . . . . . . . . . . . . . . . . . . . .4-5

4.2.1 EMI Base Address Registers (EBAR0 and EBAR1) . . . . .4-7

4.2.2 EMI Write Offset Register (EWOR) . . . . . . . . . . . . . . . . . .4-7

4.2.3 EMI Offset Register (EOR) . . . . . . . . . . . . . . . . . . . . . . . .4-8

4.2.4 EMI Data Write Registers (EDWR) . . . . . . . . . . . . . . . . . .4-9

4.2.5 EMI Data Read Register (EDRR) . . . . . . . . . . . . . . . . . . .4-9

4.2.6 EMI Data Register Buffer (EDRB) . . . . . . . . . . . . . . . . . . .4-9

4.2.7 EMI Control/Status Register (ECSR). . . . . . . . . . . . . . . .4-10

4.2.7.1 EMI Data Bus Width (EBW)—Bit 0 . . . . . . . . . . . . . . .4-10

4.2.7.2 EMI Word Length (EWL[2:0])—Bits 16,2, and 1 . . . . .4-11

4.2.7.3 EMI Addressing Mode (EAM[3:0])—Bits 6–3 . . . . . . .4-12

4.2.7.4 EMI Increment EBAR After Read (EINR)—Bit 7. . . . .4-16

4.2.7.5 EMI Increment EBAR After Write (EINW)—Bit 8 . . . .4-16

4.2.7.6 EMI Interrupt Select (EIS[1:0])—Bits 9–10 . . . . . . . . .4-17

4.2.7.7 EMI Memory-Wrap Interrupt Enable

(EMWIE)—Bit 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-17

4.2.7.8 EMI Data Write Register Empty (EDWE)—Bit 12. . . .4-18

4.2.7.9 EMI Data Read Register Full (EDRF)—Bit 13 . . . . . .4-18

4.2.7.10 EMI Data Register Buffer and Data Read Register

Full (EBDF)—Bit 14. . . . . . . . . . . . . . . . . . . . . . . . . . .4-18

4.2.7.11 EMI Busy (EBSY)—Bit 15. . . . . . . . . . . . . . . . . . . . . .4-19

4.2.7.12 EMI Read Trigger Select (ERTS)—Bit 17. . . . . . . . . .4-19

4.2.7.13 EMI DRAM Memory Timing (EDTM)—Bit 18 . . . . . . .4-19

4.2.7.14 EMI SRAM Memory Timing

(ESTM[3:0])— Bits 19–22. . . . . . . . . . . . . . . . . . . . . .4-20

4.2.7.15 EMI Enable (EME)—Bit 23 . . . . . . . . . . . . . . . . . . . . .4-21

4.2.8 EMI Refresh Control Register (ERCR) . . . . . . . . . . . . . .4-21

4.2.8.1 EMI Refresh Clock Divider (ECD[7:0])—Bits 0–7 . . . .4-22

4.2.8.2 ERCR Reserved Bits—Bits 8–17, 21 . . . . . . . . . . . . .4-22

4.2.8.3 EMI Refresh Clock Prescaler

(EPS[1:0])—Bits 18–19. . . . . . . . . . . . . . . . . . . . . . . .4-22

4.2.8.4 EMI One-Shot Refresh (EOSR)—Bit 20 . . . . . . . . . . .4-22

MOTOROLA DSP56009 User’s Manual v

4.2.8.5 EMI Refresh Enable when Debugging (ERED)—Bit 22. . .
4-22

4.2.8.6 ERCR Refresh Enable (EREF)—Bit 23 . . . . . . . . . . . 4-23

4.3 EMI ADDRESS GENERATION. . . . . . . . . . . . . . . . . . . . . . 4-23

4.3.1 SRAM Absolute Addressing . . . . . . . . . . . . . . . . . . . . . . 4-24

4.3.2 SRAM Relative Addressing. . . . . . . . . . . . . . . . . . . . . . . 4-25

4.3.3 DRAM Relative Addressing. . . . . . . . . . . . . . . . . . . . . . . 4-27

4.3.4 DRAM Absolute Addressing . . . . . . . . . . . . . . . . . . . . . . 4-30

4.4 DRAM REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31

4.4.1 DRAM Refresh Without Using The Internal Refresh

Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31

4.4.2 DRAM Refresh OnCE‰ Port Debug Mode

Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32

4.4.3 Using The Internal Refresh Timer. . . . . . . . . . . . . . . . . . 4-33

4.4.3.1 “On Line” Refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33

4.4.3.2 “Off Line” Refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-34

4.4.4 Software Controlled Refresh. . . . . . . . . . . . . . . . . . . . . . 4-34

4.4.5 DRAM Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 4-35

4.5 EMI OPERATING CONSIDERATIONS. . . . . . . . . . . . . . . . 4-38

4.5.1 EMI Triggering and Pipelining. . . . . . . . . . . . . . . . . . . . . 4-38

4.5.2 Read Data Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-40

4.5.3 Write-Data Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-43

4.5.4 EMI Operation During Stop. . . . . . . . . . . . . . . . . . . . . . . 4-45

4.5.5 EMI Operation During Wait. . . . . . . . . . . . . . . . . . . . . . . 4-45

4.6 DATA-DELAY STRUCTURE. . . . . . . . . . . . . . . . . . . . . . . . 4-46

4.7 EMI-TO-MEMORY CONNECTION . . . . . . . . . . . . . . . . . . . 4-48

4.8 EMI TIMING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-50

4.8.1 Timing Diagrams for DRAM Addressing Modes . . . . . . . 4-51

4.8.1.1 Fast Timing Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-52

4.8.1.2 Slow Timing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-58

4.8.2 Timing Diagrams for SRAM Addressing Modes . . . . . . . 4-64

SECTION 5 SERIAL HOST INTERFACE. . . . . . . . . . . . . . . . . . 5-1

5.1 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

5.2 SERIAL HOST INTERFACE INTERNAL ARCHITECTURE . 5-4

5.2.1 SHI Clock Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

vi DSP56009 User’s Manual MOTOROLA

5.3 SERIAL HOST INTERFACE PROGRAMMING MODEL . . . .5-5

5.3.1 SHI Input/Output Shift Register (IOSR)—Host Side . . . . .5-8

5.3.2 SHI Host Transmit Data Register (HTX)—DSP Side. . . . . 5-8

5.3.3 SHI Host Receive Data FIFO (HRX)—DSP Side . . . . . . .5-9

5.3.4 SHI Slave Address Register (HSAR)—DSP Side . . . . . . . 5-9

5.3.4.1 HSAR Reserved Bits—Bits 17–0,19. . . . . . . . . . . . . . .5-9

5.3.4.2 HSAR I2C Slave Address

(HA[6:3], HA1)—Bits 23–20,18. . . . . . . . . . . . . . . . . . .5-9

5.3.5 SHI Clock Control Register (HCKR)—DSP Side. . . . . . . .5-9

5.3.5.1 Clock Phase and Polarity

(CPHA and CPOL)—Bits 1–0 . . . . . . . . . . . . . . . . . . .5-10

5.3.5.2 HCKR Prescaler Rate Select (HRS)—Bit 2 . . . . . . . .5-11

5.3.5.3 HCKR Divider Modulus Select

(HDM[5:0])—Bits 8–3 . . . . . . . . . . . . . . . . . . . . . . . . .5-12

5.3.5.4 HCKR Reserved Bits—Bits 23–14, 11–9 . . . . . . . . . .5-12

5.3.5.5 HCKR Filter Mode (HFM[1:0]) — Bits 13–12 . . . . . . .5-12

5.3.6 SHI Control/Status Register (HCSR)—DSP Side . . . . . .5-13

5.3.6.1 HCSR Host Enable (HEN)—Bit 0 . . . . . . . . . . . . . . . .5-13

5.3.6.2 HCSR I2C/SPI Selection (HI2C)—Bit 1. . . . . . . . . . . .5-13

5.3.6.3 HCSR Serial Host Interface Mode

(HM[1:0])—Bits 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . .5-14

5.3.6.4 HCSR Reserved Bits—Bits 23, 18, 16, and 4. . . . . . .5-14

5.3.6.5 HCSR FIFO-Enable Control (HFIFO)—Bit 5. . . . . . . .5-14

5.3.6.6 HCSR Master Mode (HMST)—Bit 6 . . . . . . . . . . . . . .5-14

5.3.6.7 HCSR Host-Request Enable

(HRQE[1:0])—Bits 8–7 . . . . . . . . . . . . . . . . . . . . . . . .5-15

5.3.6.8 HCSR Idle (HIDLE)—Bit 9 . . . . . . . . . . . . . . . . . . . . .5-15

5.3.6.9 HCSR Bus-Error Interrupt Enable (HBIE)—Bit 10 . . .5-16

5.3.6.10 HCSR Transmit-Interrupt Enable (HTIE)—Bit 11 . . . .5-16

5.3.6.11 HCSR Receive Interrupt Enable

(HRIE[1:0])—Bits 13–12 . . . . . . . . . . . . . . . . . . . . . . .5-16

5.3.6.12 HCSR Host Transmit Underrun Error

(HTUE)—Bit 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-17

5.3.6.13 HCSR Host Transmit Data Empty (HTDE)—Bit 15. . .5-17

5.3.6.14 Host Receive FIFO Not Empty (HRNE)—Bit 17 . . . . .5-18

5.3.6.15 Host Receive FIFO Full (HRFF)—Bit 19. . . . . . . . . . .5-18

MOTOROLA DSP56009 User’s Manual vii

5.3.6.16 Host Receive Overrun Error (HROE)—Bit 20 . . . . . . 5-18

5.3.6.17 Host Bus Error (HBER)—Bit 21 . . . . . . . . . . . . . . . . . 5-18

5.3.6.18 HCSR Host Busy (HBUSY)—Bit 22 . . . . . . . . . . . . . . 5-19

5.4 CHARACTERISTICS OF THE SPI BUS . . . . . . . . . . . . . . . 5-19

5.4.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19

5.5 CHARACTERISTICS OF THE I2C BUS . . . . . . . . . . . . . . . 5-20

5.5.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20

5.5.2 I2C Data Transfer Formats . . . . . . . . . . . . . . . . . . . . . . . 5-22

5.6 SHI PROGRAMMING CONSIDERATIONS . . . . . . . . . . . . 5-23

5.6.1 SPI Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24

5.6.2 SPI Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25

5.6.3 I2C Slave Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26

5.6.3.1 Receive Data in I2C Slave Mode . . . . . . . . . . . . . . . . 5-26

5.6.3.2 Transmit Data In I2C Slave Mode. . . . . . . . . . . . . . . . 5-27

5.6.4 I2C Master Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28

5.6.4.1 Receive Data in I2C Master Mode . . . . . . . . . . . . . . . 5-29

5.6.4.2 Transmit Data In I2C Master Mode. . . . . . . . . . . . . . . 5-30

5.6.5 SHI Operation During Stop . . . . . . . . . . . . . . . . . . . . . . . 5-31

SECTION 6 SERIAL AUDIO INTERFACE . . . . . . . . . . . . . . . . . 6-1

6.1 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

6.2 SERIAL AUDIO INTERFACE INTERNAL ARCHITECTURE 6-4

6.2.1 Baud-Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

6.2.2 Receive Section Overview . . . . . . . . . . . . . . . . . . . . . . . . 6-5

6.2.3 SAI Transmit Section Overview . . . . . . . . . . . . . . . . . . . . 6-6

6.3 SERIAL AUDIO INTERFACE PROGRAMMING MODEL . . . 6-8

6.3.1 Baud Rate Control Register (BRC). . . . . . . . . . . . . . . . . . 6-9

6.3.1.1 Prescale Modulus select (PM[7:0])—Bits 7–0 . . . . . . 6-10

6.3.1.2 Prescaler Range (PSR)—Bit 8. . . . . . . . . . . . . . . . . . 6-10

6.3.1.3 BRC Reserved Bits—Bits 15–9 . . . . . . . . . . . . . . . . . 6-10

6.3.2 Receiver Control/Status Register (RCS). . . . . . . . . . . . . 6-10

6.3.2.1 RCS Receiver 0 Enable (R0EN)—Bit 0 . . . . . . . . . . . 6-10

6.3.2.2 RCS Receiver 1 Enable (R1EN)—Bit 1 . . . . . . . . . . . 6-11

6.3.2.3 RCS Reserved Bit—Bits 13 and 2 . . . . . . . . . . . . . . . 6-11

6.3.2.4 RCS Receiver Master (RMST)—Bit 3 . . . . . . . . . . . . 6-11

viii DSP56009 User’s Manual MOTOROLA

6.3.2.5 RCS Receiver Word Length Control

(RWL[1:0])—Bits 4 and 5 . . . . . . . . . . . . . . . . . . . . . .6-11

6.3.2.6 RCS Receiver Data Shift Direction (RDIR)—Bit 6 . . .6-12

6.3.2.7 RCS Receiver Left Right Selection (RLRS)—Bit 7 . . .6-12

6.3.2.8 RCS Receiver Clock Polarity (RCKP)—Bit 8 . . . . . . .6-13

6.3.2.9 RCS Receiver Relative Timing (RREL)—Bit 9 . . . . . .6-13

6.3.2.10 RCS Receiver Data Word Truncation

(RDWT)—Bit 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-14

6.3.2.11 RCS Receiver Interrupt Enable (RXIE)—Bit 11 . . . . .6-15

6.3.2.12 RCS Receiver Interrupt Location (RXIL)—Bit 12 . . . .6-15

6.3.2.13 RCS Receiver Left Data Full (RLDF)—Bit 14 . . . . . . .6-16

6.3.2.14 RCS Receiver Right Data Full (RRDF)—Bit 15 . . . . .6-16

6.3.3 SAI Receive Data Registers (RX0 and RX1). . . . . . . . . .6-17

6.3.4 Transmitter Control/Status Register (TCS) . . . . . . . . . . .6-17

6.3.4.1 TCS Transmitter 0 Enable (T0EN)—Bit 0. . . . . . . . . .6-17

6.3.4.2 TCS Transmitter 1 Enable (T1EN)—Bit 1. . . . . . . . . .6-17

6.3.4.3 TCS Transmitter 2 Enable (T2EN)—Bit 2. . . . . . . . . .6-18

6.3.4.4 TCS Transmitter Master (TMST)—Bit 3 . . . . . . . . . . .6-18

6.3.4.5 TCS Transmitter Word Length Control

(TWL[1:0])—Bits 4 & 5 . . . . . . . . . . . . . . . . . . . . . . . .6-18

6.3.4.6 TCS Transmitter Data Shift Direction (TDIR)—Bit 6. .6-18

6.3.4.7 TCS Transmitter Left Right Selection (TLRS)—Bit 7 .6-19

6.3.4.8 TCS Transmitter Clock Polarity (TCKP)—Bit 8. . . . . .6-19

6.3.4.9 TCS Transmitter Relative Timing (TREL)—Bit 9. . . . .6-20

6.3.4.10 TCS Transmitter Data Word Expansion

(TDWE)—Bit 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-20

6.3.4.11 TCS Transmitter Interrupt Enable (TXIE)—Bit 11. . . .6-21

6.3.4.12 TCS Transmitter Interrupt Location (TXIL)—Bit 12. . .6-22

6.3.4.13 TCS Reserved Bit—Bit 13. . . . . . . . . . . . . . . . . . . . . .6-22

6.3.4.14 TCS Transmitter Left Data Empty (TLDE)—Bit 14 . . .6-22

6.3.4.15 TCS Transmitter Right Data Empty (TRDE)—Bit 15. .6-23

6.3.5 SAI Transmit Data Registers (TX2, TX1 and TX0) . . . . .6-23

6.4 PROGRAMMING CONSIDERATIONS . . . . . . . . . . . . . . . .6-24

6.4.1 SAI Operation During Stop . . . . . . . . . . . . . . . . . . . . . . .6-24

6.4.2 Initiating a Transmit Session . . . . . . . . . . . . . . . . . . . . . .6-24

MOTOROLA DSP56009 User’s Manual ix

6.4.3 Using a Single Interrupt to Service Both Receiver

and Transmitter Sections . . . . . . . . . . . . . . . . . . . . . . . . 6-24

6.4.4 SAI State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25

SECTION 7 GENERAL PURPOSE INPUT/OUTPUT. . . . . . . . . 7-1

7.1 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3

7.2 GPIO PROGRAMMING MODEL. . . . . . . . . . . . . . . . . . . . . . 7-3

7.3 GPIO REGISTER (GPIOR) . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3

7.3.1 GPIOR Data Bits (GD[3:0])—Bits 3–0. . . . . . . . . . . . . . . . 7-4

7.3.2 GPIOR Reserved Bits—Bits 4–7, 12–15, and 20–23 . . . . 7-4

7.3.3 GPIOR Data Direction Bits (GDD[3:0])—Bits 11–8. . . . . . 7-4

7.3.4 GPIOR Control Bits (GC[3:0])—Bits 19–16. . . . . . . . . . . . 7-4

APPENDIX A BOOTSTRAP ROM CONTENTS . . . . . . . . . . . . . . A-1

A.1 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3

A.2 BOOTSTRAPPING THE DSP. . . . . . . . . . . . . . . . . . . . . . . . A-3

A.3 BOOTSTRAP PROGRAM LISTING . . . . . . . . . . . . . . . . . . . A-4

A.4 BOOTSTRAP FLOW CHART . . . . . . . . . . . . . . . . . . . . . . . . A-7

APPENDIX B PROGRAMMING REFERENCE . . . . . . . . . . . . . . . B-1

B.1 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3

B.2 PERIPHERAL ADDRESSES. . . . . . . . . . . . . . . . . . . . . . . . . B-3

B.3 INTERRUPT ADDRESSES. . . . . . . . . . . . . . . . . . . . . . . . . . B-3

B.4 INTERRUPT PRIORITIES. . . . . . . . . . . . . . . . . . . . . . . . . . . B-3

B.5 INSTRUCTION SET SUMMARY. . . . . . . . . . . . . . . . . . . . . . B-3

B.6 PROGRAMMING SHEETS . . . . . . . . . . . . . . . . . . . . . . . . . . B-3

APPENDIX C APPLICATION EXAMPLES . . . . . . . . . . . . . . . . . . C-1

C.1 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .C-3

C.2 TYPICAL SYSTEM TOPOLOGY. . . . . . . . . . . . . . . . . . . . . . C-3

C.3 TYPICAL AUDIO APPLICATION. . . . . . . . . . . . . . . . . . . . . . C-4

C.4 PROGRAM OVERLAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . .C-5

C.5 SINGLE DELAY LINE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-5

C.6 EARLY REFLECTION FILTER . . . . . . . . . . . . . . . . . . . . . . . C-6

C.7 TWO CHANNEL COMB FILTER. . . . . . . . . . . . . . . . . . . . . .C-7

C.8 3-TAP FIR FILTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-10

x DSP56009 User’s Manual MOTOROLA

LIST OF FIGURES

Figure 1-1 DSP56009 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9

Figure 2-1 DSP56009 SIgnals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

Figure 3-1 Memory Maps for PEA = 0, PEB = 0. . . . . . . . . . . . . . . . . . . . . . 3-6

Figure 3-2 Memory Maps for PEA = 1, PEB = 0. . . . . . . . . . . . . . . . . . . . . . 3-6

Figure 3-3 Memory Maps for PEA = 0, PEB = 1. . . . . . . . . . . . . . . . . . . . . . 3-7

Figure 3-4 Memory Maps for PEA = 1, PEB = 1. . . . . . . . . . . . . . . . . . . . . . 3-7

Figure 3-5 Operating Mode Register (OMR). . . . . . . . . . . . . . . . . . . . . . . . 3-11

Figure 3-6 Interrupt Priority Register (Address X:$FFFF). . . . . . . . . . . . . . 3-14

Figure 3-7 PLL Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18

Figure 4-1 EMI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

Figure 4-2 EMI Control/Status Register (ECSR). . . . . . . . . . . . . . . . . . . . . . 4-8

Figure 4-3 EMI Refresh Control Register (ERCR) . . . . . . . . . . . . . . . . . . . 4-21

Figure 4-4 EMI Address Generation Block Diagram. . . . . . . . . . . . . . . . . . 4-23

Figure 4-5 Refresh Timer Functional Diagram.. . . . . . . . . . . . . . . . . . . . . . 4-33

Figure 4-6 Timing Diagram of a DRAM Refresh Cycle (Fast). . . . . . . . . . . 4-37

Figure 4-7 Timing Diagram Of a DRAM Refresh Cycle (Slow). . . . . . . . . . 4-37

Figure 4-8 EMI Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39

Figure 4-9 Illustration of the Data-Delay Structure . . . . . . . . . . . . . . . . . . . 4-46

Figure 4-10 DRAM for Data Delay Buffers and for SRAM for Bootstrap . . . 4-48

Figure 4-11 SRAM for Data Delay Buffers and for Bootstrap. . . . . . . . . . . . 4-49

MOTOROLA DSP56009 User’s Manual xi

Figure 4-12 Replacing DRAMs with SRAMs for Large Arrays. . . . . . . . . . . . 4-50

Figure 4-13 Fast Read or Write DRAM Access Timing—1 . . . . . . . . . . . . . . 4-52

Figure 4-14 Fast Read or Write DRAM Access Timing—2 . . . . . . . . . . . . . . 4-53

Figure 4-15 Fast Read or Write DRAM Access Timing—3 . . . . . . . . . . . . . . 4-54

Figure 4-16 Fast Read or Write DRAM Access Timing—4 . . . . . . . . . . . . . . 4-55

Figure 4-17 Fast Read or Write DRAM Access Timing—5 . . . . . . . . . . . . . . 4-56

Figure 4-18 Fast Read or Write DRAM Access Timing—6 . . . . . . . . . . . . . . 4-57

Figure 4-19 Slow Read or Write DRAM Access Timing—1. . . . . . . . . . . . . . 4-58

Figure 4-20 Slow Read or Write DRAM Access Timing—2. . . . . . . . . . . . . . 4-59

Figure 4-21 Slow Read or Write DRAM Access Timing—3. . . . . . . . . . . . . . 4-60

Figure 4-22 Slow Read or Write DRAM Access Timing—4. . . . . . . . . . . . . . 4-61

Figure 4-23 Slow Read or Write DRAM Access Timing—5. . . . . . . . . . . . . . 4-62

Figure 4-24 Slow Read or Write DRAM Access Timing—6. . . . . . . . . . . . . . 4-63

Figure 4-25 SRAM Read/Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-64

Figure 5-1 Serial Host Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . . 5-4

Figure 5-2 SHI Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

Figure 5-3 SHI Programming Model—Host Side. . . . . . . . . . . . . . . . . . . . . . 5-5

Figure 5-4 SHI Programming Model—DSP Side. . . . . . . . . . . . . . . . . . . . . . 5-6

Figure 5-5 SHI I/O Shift Register (IOSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8

Figure 5-6 SPI Data-To-Clock Timing Diagram. . . . . . . . . . . . . . . . . . . . . . 5-10

Figure 5-7 I2C Bit Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20

Figure 5-8 I2C Start and Stop Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21

xii DSP56009 User’s Manual MOTOROLA

Figure 5-9 Acknowledgment on the I2C Bus. . . . . . . . . . . . . . . . . . . . . . . . 5-22

Figure 5-10 I2C Bus Protocol For Host Write Cycle . . . . . . . . . . . . . . . . . . . 5-23

Figure 5-11 I2C Bus Protocol For Host Read Cycle . . . . . . . . . . . . . . . . . . . 5-23

Figure 6-1 SAI Baud-Rate Generator Block Diagram. . . . . . . . . . . . . . . . . . 6-4

Figure 6-2 SAI Receive Section Block Diagram . . . . . . . . . . . . . . . . . . . . . . 6-5

Figure 6-3 SAI Transmit Section Block Diagram . . . . . . . . . . . . . . . . . . . . . 6-7

Figure 6-4 SAI Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8

Figure 6-5 Receiver Data Shift Direction (RDIR) Programming . . . . . . . . . 6-12

Figure 6-6 Receiver Left/Right Selection (RLRS) Programming. . . . . . . . . 6-12

Figure 6-7 Receiver Clock Polarity (RCKP) Programming . . . . . . . . . . . . . 6-13

Figure 6-8 Receiver Relative Timing (RREL) Programming. . . . . . . . . . . . 6-14

Figure 6-9 Receiver Data Word Truncation (RDWT) Programming . . . . . . 6-14

Figure 6-10 Transmitter Data Shift Direction (TDIR) Programming . . . . . . . 6-19

Figure 6-11 Transmitter Left/Right Selection (TLRS) Programming. . . . . . . 6-19

Figure 6-12 Transmitter Clock Polarity (TCKP) Programming . . . . . . . . . . . 6-20

Figure 6-13 Transmitter Relative Timing (TREL) Programming . . . . . . . . . . 6-20

Figure 6-14 Transmitter Data Word Expansion (TDWE) Programming . . . . 6-21

Figure 7-1 GPIO Control/Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3

Figure 7-2 GPIO Circuit Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5

MOTOROLA DSP56009 User’s Manual xiii

LIST OF TABLES

Table 1-1 High True / Low True Signal Conventions . . . . . . . . . . . . . . . . . . 1-6

Table 1-2 Interrupt Starting Addresses and Sources. . . . . . . . . . . . . . . . . 1-13

Table 1-3 Internal Memory Configurations. . . . . . . . . . . . . . . . . . . . . . . . . 1-15

Table 1-4 On-chip Peripheral Memory Map . . . . . . . . . . . . . . . . . . . . . . . . 1-16

Table 2-1 DSP56009 Functional Group Signal Allocations . . . . . . . . . . . . . 2-3

Table 2-2 Power Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

Table 2-3 Grounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

Table 2-4 Clock and PLL Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

Table 2-5 External Memory Interface (EMI) Signals. . . . . . . . . . . . . . . . . . . 2-7

Table 2-6 EMI Operating States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9

Table 2-7 Interrupt and Mode Control Signals . . . . . . . . . . . . . . . . . . . . . . 2-10

Table 2-8 Serial Host Interface (SHI) signals. . . . . . . . . . . . . . . . . . . . . . . 2-14

Table 2-9 Serial Audio Interface (SAI) Receiver signals . . . . . . . . . . . . . . 2-18

Table 2-10 Serial Audio Interface (SAI) Transmitter signals . . . . . . . . . . . . 2-20

Table 2-11 General Purpose I/O (GPIO) Signals. . . . . . . . . . . . . . . . . . . . . 2-21

Table 2-12 On-Chip Emulation Port Signals. . . . . . . . . . . . . . . . . . . . . . . . . 2-22

Table 3-1 Internal Memory Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

Table 3-2 Internal I/O Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

Table 3-3 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13

Table 3-4 Interrupt Priorities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15

xiv DSP56009 User’s Manual MOTOROLA

Table 3-5 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16

Table 4-1 EMI Interrupt Vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

Table 4-2 EMI Internal Interrupt Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

Table 4-3 EMI Memory Accesses and Locations Per Word . . . . . . . . . . . 4-10

Table 4-4 EMI Word Length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11

Table 4-5 EMI Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12

Table 4-6 EMI Maximum SRAM Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13

Table 4-7 EMI Maximum DRAM Size (Relative Addressing). . . . . . . . . . . 4-14

Table 4-8 EMI Maximum DRAM Size (Absolute Addressing) . . . . . . . . . . 4-15

Table 4-9 EMI Read/Write Interrupt Select . . . . . . . . . . . . . . . . . . . . . . . . 4-17

Table 4-10 EMI DRAM Timing (clock cycles per word transfer) . . . . . . . . . 4-19

Table 4-11 EMI SRAM Timing (clock cycles per word transfer) . . . . . . . . . 4-20

Table 4-12 Relative Addressing Extension Bits. . . . . . . . . . . . . . . . . . . . . . 4-24

Table 4-13 Word Address to Physical Address Mapping for SRAM . . . . . . 4-26

Table 4-14 Word-Address-to-Physical-Address Mapping for DRAM. . . . . . 4-28

Table 4-15 Address Generation For DRAM Relative Addressing . . . . . . . . 4-29

Table 4-16 Word-to-Physical-Address Mapping for DRAM Absolute

Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31

Table 4-17 Typical DRAM Refresh Timing Requirements. . . . . . . . . . . . . . 4-35

Table 4-18 Continuous Refresh: Timings And Settings For EPS[1:0] and

ECD[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-36

Table 4-19 Burst Refresh: Timings And Settings For EPS[1:0] and

ECD[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-36

MOTOROLA DSP56009 User’s Manual xv

Table 4-20 Maximum DSP Clock Frequencies When Using DRAM . . . . . . 4-50

Table 4-21 Maximum DSP Clock Frequencies When Using SRAM. . . . . . . 4-51

Table 4-22 Maximum DSP Clock Frequencies When Using EPROM . . . . . 4-51

Table 5-1 SHI Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

Table 5-2 SHI Internal Interrupt Priorities. . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

Table 5-3 SHI Noise Reduction Filter Mode. . . . . . . . . . . . . . . . . . . . . . . . 5-12

Table 5-4 SHI Data Size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14

Table 5-5 HREQ Function In SHI Slave Modes . . . . . . . . . . . . . . . . . . . . . 5-15

Table 5-6 HCSR Receive Interrupt Enable Bits . . . . . . . . . . . . . . . . . . . . . 5-17

Table 6-1 SAI Interrupt Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9

Table 6-2 SAI Internal Interrupt Priorities. . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9

Table 6-3 Receiver Word Length Control. . . . . . . . . . . . . . . . . . . . . . . . . . 6-11

Table 6-4 Transmitter Word Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18

Table 7-1 GPIO Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4

xvi DSP56009 User’s Manual MOTOROLA

SECTION 1

OVERVIEW

MOTOROLA DSP56009 User’s Manual 1-1

Overview

1.1 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

1.2 DSP56009 FEATURES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6

1.3 DSP56009 ARCHITECTURAL OVERVIEW . . . . . . . . . . . . . 1-8

1-2 DSP56009 User’s Manual MOTOROLA

Overview

Introduction

1.1 INTRODUCTION

This manual describes in detail the DSP56009 24-bit Digital Signal Processor (DSP),
its memory, operating modes, and peripheral modules. This manual is intended to be
used with the DSP56000 Family Manual (DSP56KFAMUM/AD) and the DSP56009
Technical Data sheet (DSP56009/D). The family manual describes the Central
Processing Unit (CPU), programming models, and the instruction set. The data sheet
provides electrical specifications, timing, pinouts, and packaging descriptions. These
documents, as well as Motorola’s DSP development tools, can be obtained through a
local Motorola Semiconductor Sales Office or authorized distributor.

To receive the latest information, access the Motorola DSP home page located at

http://www.motorola-dsp.com

The DSP56009 is a high-performance audio DSP based on the DSP56000 core
architecture and implemented in the same scalable technology as the DSP56002,
DSP56004, DSP56005, DSP56007, and other 24-bit DSP56000 modular products.
Because of its processing power and large memory capacity, it supports a variety of
digital audio decompression functions, such as Dolby AC-3® Surround, MPEG1
Layer 2, and Digital Theater Systems™ (DTS). The DSP56009 also provides the
following on-chip peripherals to support these audio functions:

• External Memory Interface (EMI)— interfaces DRAM, SRAM, and EPROM;

the DRAM interface is specifically designed to provide access to a large,
inexpensive memory space, such as that required by many audio applications

• Serial Host Interface (SHI)—simple communications and control interface

between a host processor and the DSP

• Serial Audio Interface (SAI)—user-programmable interface that provides

support for a wide variety of serial audio formats to support a number of
standard audio devices

• Dedicated General Purpose Input/Output (GPIO) Signals— four additional

individually controlled input or output signals

The DSP56009 has the power and ease-of-programming required for stand-alone,
embedded applications. The versatile, on-board peripherals allow the DSP to be
easily connected to almost any other processor with little or no additional logic. The
low pin-count (80 pins) allows the DSP56009 to be available in a small, inexpensive
package.

MOTOROLA DSP56009 User’s Manual 1-3

Overview
Introduction

1.1.1 Manual Organization

This manual includes the following sections:

• Section 1—Overview furnishes an description of the manual organization and

provides a brief description of the DSP56009.

• Section 2—Signal Descriptions describes the DSP56009 signals and signal

groupings.

• Section 3—Memory, Operating Modes, and Interrupts describes the internal

memory organization, operating modes, interrupt processing, and chip
initialization during hardware reset.

• Section 4—External Memory Interface describes the External Memory Interface

(EMI) port (Port A), its registers, and its controls.

• Section 5—Serial Host Interface describes the operation, registers, and control of

the Serial Host Interface (SHI).

• Section 6—Serial Audio Interface describes the operation of the Serial Audio

Interface (SAI), its registers, and its controls.

• Section 7—General Purpose I/O describes the four dedicated General Purpose

Input/Output (GPIO) pins, the GPIO registers, and GPIO control.

• Appendix A—Bootstrap Code Listings lists the code used to bootstrap the

DSP56009.

• Appendix B—Programming Reference provides a quick reference for the

instructions and registers used by the DSP56009. These sheets are provided
with the expectation that they be photocopied and used by programmers
when programming the registers.

• Appendix C—Application Examples provides a selection of typical circuit block

diagrams and coding examples.

1-4 DSP56009 User’s Manual MOTOROLA

Overview

Introduction

1.1.2 Manual Conventions

The following conventions are used in this manual:

• The word “reset” is used in three different contexts in this manual. There is a
reset pin that is always written as “RESET,” there is a reset instruction that is
always written as “RESET”, and the word reset, used to refer to the reset
function, is written in lower case (with a leading capital letter as grammar
dictates.)

• Bits within a register are indicated AA[n:0] when more than one bit is
involved in a description. For purposes of description, the bits are presented
as if they are contiguous within the register; however, this is not always the
case. Refer to the programming model diagrams or to the programming sheets
to see the exact location of bits within a register.

• When a bit is described as “set,” its value is 1. When a bit is described as
“cleared,” its value is 0.

• Hex (hexadecimal) values are indicated with a dollar sign ($) preceding the
hex value, as in “$FFFB is the X memory address for the Interrupt Priority
Register (IPR).”

• Code examples are displayed in a monospaced font, as shown in
Example 1-1.

Example 1-1 Sample Code Listing

movep #0,x:EOR0 ; drive 2nd read trigger

bset #ERTS,x:ECSR ; set read triggers by reading EDDR

do #(N-2),end_OL ; loop to drive more (N-2) triggers

• Pins or signals listed in code examples that are asserted low have a tilde (~) in
front of their names.

• The word “assert” means that a high true (active high) signal is pulled high (to
VCC) or that a low true (active low) signal is pulled low (to ground).

• The word “deassert” means that a high true signal is pulled low (to ground) or
that a low true signal is pulled high (to VCC).

• Overbars are used to indicate a signal that is active when pulled to ground
(see Table 1-1). For example, the RESET pin is active when pulled to ground.
Therefore, references to the RESET pin will always have an overbar. Such pins
and signals are also said to be “active low” or “low true.”

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Table 1-1 High True / Low True Signal Conventions

Signal/Symbol Logic State Signal State Voltage

1

PIN

1

PIN

1

PIN

1

PIN

Note: PIN is a generic term for any pin on the device.
Note: Ground is an acceptable low voltage level. See the appropriate data sheet for the range of

acceptable low voltage levels (typically a TTL logic low).

Note: VCC is an acceptable high voltage level. See the appropriate data sheet for the range of

acceptable high voltage levels (typically a TTL logic high).

True Asserted

False Deasserted

True Asserted

False Deasserted

3

V

CC

Ground

Ground

3

V

CC

2

2

1.2 DSP56009 FEATURES

The DSP56009 consists of the DSP56000 core, program and data memory, and
peripherals useful for embedded control applications. The following paragraphs
provide a list of DSP56009 features and a brief description of its core and peripheral
components.

• General Features
– Harvard architecture, with four 24-bit internal data buses and three 16-bit

internal address buses, permitting simultaneous accesses to program
memory and two data memories

– Software-programmable, Phase Lock Loop (PLL) frequency synthesizer for

the core clock with a wide range of frequency multiplications (1 to 4096)
and power-saving clock divider (2i, where i = 0 to 15) for reduced clock
noise

– On-Chip Emulation (OnCE) port for unobtrusive, comprehensive,

processor speed-independent hardware/software debugging
– Stop and Wait low-power standby modes
– Efficient, object code compatible, 24-bit 56000-family DSP engine

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– Up to 40.5 Million Instructions Per Second (MIPS)—24.69 ns instruction

cycle at 81 MHz
– Up to 324 Million Operations Per Second (MOPS) at 81 MHz
– On-chip peripheral registers memory-mapped in data memory space
– Three external interrupt request pins
– Data Arithmetic Logic Unit (ALU), Program Control (PC), and Address

Generation Unit (AGU) all integral to the core processor
– Bootstrap loading from SHI or EMI (in absolute SRAM mode)
– Completely pin-compatible with DSP56004 and DSP56007 for easy

upgrades
– Fully static, HCMOS design for operating frequencies from 81 MHz down

to DC
– 80-pin plastic Quad Flat Pack surface-mount package; 14 × 14 × 2.45 mm;

0.65 mm lead pitch
– Highly parallel instruction set with unique DSP addressing modes
– Two 56-bit accumulators, including extension byte
– Parallel 24 × 24-bit multiply-accumulate in 1 instruction cycle (2 clock

cycles)

– Double precision 48 × 48-bit multiply with 96-bit result in 6 instruction

cycles
– 56-bit addition/subtraction in 1 instruction cycle
– Fractional and integer arithmetic with support for multiprecision

arithmetic
– Hardware support for block-floating point Fast Fourier Transforms (FFTs)
– Zero-overhead fast interrupts (2 instruction cycles)
– Nested hardware DO loops

• Memory Modules:

– On-chip 4352 × 24-bit Y data RAM and 1792 × 24-bit Y data ROM
– On-chip 4608 × 24-bit X data RAM and 3072 × 24-bit X data ROM
– On-chip 10240 × 24-bit Program ROM
– On-chip 512 × 24-bit Program RAM and 64 × 24-bit bootstrap ROM

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– Up to 2304 × 24-Bit from X and Y data RAM can be switched to Program

RAM for a total of 2816 × 24-bit Program RAM

• Peripheral modules:
– External Memory Interface (EMI), implemented as a peripheral,

supporting:

• Direct connection of page-mode DRAMs: 64 K × 4 bits, 64 K × 8 bits, 256
K × 4 bits, 256 K × 8 bits, 1 M × 4 bits, 1 M × 8 bits, 4 M × 4 bits, and 4 M
× 8 bits

• SRAMs (one to four): 256 K × 8 bits

• Bootstrap from EPROM

• Data bus may be 4 or 8 bits wide

• Data words may be 8, 12, 16, 20, or 24 bits wide

– Serial Host Interface (SHI): SPI and I2C protocols, single master capability,

10-word receive FIFO register, support for 8-, 16-, and 24-bit words

– Serial Audio Interface (SAI) includes two receivers and three transmitters,

master or slave capability, and implementation of Philips, Sony, and
Matsushita audio protocols; two complete sets of SAI interrupt vectors

– Four independent, programmable GPIO lines

1.3 DSP56009 ARCHITECTURAL OVERVIEW

The DSP56009 is a member of the 24-bit DSP56000 family. The DSP is composed of
the 24-bit DSP56000 core, memory, and a set of peripheral modules as shown in
Figure 1-1 on page 1-9. The 24-bit DSP56000 core is composed of a Data ALU, an
Address Generation Unit (AGU), a Program Controller, an On-Chip Emulation
(OnCE) port, and a PLL designed to allow the DSP to run at full speed while using a
low-speed clock. The DSP56000-family architecture, upon which the DSP56009 is
built, was designed to maximize throughput in data-intensive digital signal
processing applications. The result is a dual-natured, expandable architecture with
sophisticated on-chip peripherals and versatile GPIO.

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24-Bit

DSP56000

Core

Internal

Data
Bus

Switch

OnCETM Port

Clock

PLL

Gen.

4

General

Purpose

I/O

(GPIO)

Interrupt

Control

9

Serial
Audio

Interface

(SAI)

Generation

Program Control Unit

Serial

Host

Interface

(SHI)

Address

Unit

GDB
PDB
XDB

YDB

Program

Decode

Controller

5 29

External
Memory

Interface

(EMI)

Program
Address

Generator

PAB
XAB
YAB

Program

Memory

24 × 24 + 56 → 56-Bit MAC

Two 56-Bit Accumulators

X Data

Memory

Data ALU

16-Bit Bus
24-Bit Bus

Y Data

Memory

43

IRQA, IRQB
NMI, RESET

4

AA0248k

Figure 1-1 DSP56009 Block Diagram

The DSP56000 core is dual-natured in that there are two independent, expandable
data memory spaces, two address arithmetic units, and a Data ALU that has two
accumulators and two shifter/limiters. The duality of the architecture makes it easier
to write software for DSP applications. For example, data is naturally partitioned into
coefficient and data spaces for filtering and transformations, and into real and
imaginary spaces for performing complex arithmetic.

The DSP56000 architecture is especially suited for audio applications since its
arithmetic operations are executed on 24-bit or 48-bit data words. This is a significant
advantage for audio over 16-bit and 32-bit architectures: 16-bit DSP architectures
have insufficient precision for CD-quality sound, and while 32-bit DSP architectures
possess the necessary precision, with extra silicon and cost overhead they are not
suitable for high-volume, cost-driven audio applications.

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1.3.1 Memory and Peripheral Modules

The following memory and peripheral modules are included on the DSP56009:

• External Memory Interface (EMI)—The EMI provides simple connection to

external DRAM and/or SRAM and/or EPROM memories. This memory
interface is designed to provide a simple and inexpensive connection to large
DRAM memories (up to two 4 M × 4 bits) for audio delay lines. The port is
configurable as either 4 or 8 bits wide, providing a convenient interface to
standard DRAM, EPROM, and SRAM parts. Data word packing/unpacking is
automatic to simplify and accelerate converting between memory word size
and data word size. Absolute addressing can be used for random memory
access, program bootstrap, overlays, and to access external peripherals.
Relative addressing, assisted by base-offset registers, can easily be used to set
up delay lines.

• Serial Host Interface (SHI)—The SHI provides a fast, yet simple serial

interface to connect the DSP56009 to a host processor or to another serial
peripheral device. Two serial protocols are available: the Motorola Serial
Peripheral Interface (SPI) bus and the Philips Inter Integrated-circuit Control
(I2C) bus. The SHI will operate with 8-, 16-, and 24-bit words and the receiver
has an optimal 10-word FIFO register to reduce the receive interrupt rate.

• Serial Audio Interface (SAI)—The SAI provides a synchronous serial

interface that allows the DSP56009 to communicate using a wide range of
standard serial data formats used by audio manufacturers at bit rates up to
one-third the DSP core clock rate (e.g., 27 MHz for a 81 MHz clock). There are
three synchronized data transmission lines and two synchronized data
reception lines, all of which are double-buffered.

• General Purpose Input/Output (GPIO)—The GPIO has four dedicated

signals that can be independently programmed to be inputs, standard TTL
outputs, open collector outputs, or disconnected.

1.3.2 DSP Core Processor

The 24-bit DSP56000 core is composed of a Data ALU, an AGU, a Program Controller
(PC), and the buses that connect them together. The OnCE port and a PLL are
integral parts of this processor. Figure 1-1 on page 1-9 illustrates the DSP block
diagram, showing the components of the core processor, as well as the peripherals
specific to the DSP56009. The following paragraphs present a brief overview of the
DSP56000 core processor. For more thorough detail, refer to the DSP56000 Family
Manual.

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1.3.2.1 Data Arithmetic and Logic Unit (ALU)

The Data Arithmetic and Logic Unit (ALU) has been designed to be fast and provide
the capability to process signals having a wide dynamic range. Special circuitry has
been provided to facilitate the processing of data overflows and round-off errors. The
Data ALU performs all of the arithmetic and logical operations on data operands.
The Data ALU consists of four 24-bit input registers, two 48-bit accumulator
registers (also usable as four 24-bit accumulators), two 8-bit accumulator extension
registers, an accumulator shifter, two data shifter/limiters, and a parallel
single-cycle non-pipelined Multiply-Accumulator (MAC). Data ALU operations use
fractional two’s-complement arithmetic. Data ALU registers may be read or written
over the X Data Bus (XDB) and Y Data Bus (YDB) as 24- or 48-bit operands. The 24-bit
data words provide 144 dB of dynamic range. This is sufficient for most real-world
applications, including high-quality audio applications, since the majority of
Analog-to-Digital (A/D) and Digital-to-Analog (D/A) converters are 16 bits or less,
and certainly not greater than 24 bits. The 56-bit accumulation internal to the Data
ALU provides 336 dB of internal dynamic range, assuring no loss of precision due to
intermediate processing.

Two data shifter/limiters provide special post-processing on data reads (from the
ALU accumulator registers and directed to the XDB or YDB). The data shifters are
capable of shifting data one bit to the left or to the right as well as passing the data
unshifted. Each data shifter has a 24-bit output with overflow indication. The data
shifters are controlled by scaling-mode bits. These shifters permit no-overhead
dynamic scaling of fixed point data by simply programming the scaling mode bits.
This permits block floating-point algorithms to be implemented efficiently. For
example, Fast Fourier Transform (FFT) routines can use this feature to selectively
scale each butterfly pass. Saturation arithmetic is accommodated to minimize errors
due to overflow. Overflow occurs when a source operand requires more bits for
accurate representation than there are available in the destination. To minimize the
error due to overflow, “limiting” causes the maximum (or minimum, if negative)
value to be written to the destination with an error flag.

1.3.2.2 Address Generation Unit (AGU)

The Address Generation Unit (AGU) performs all address storage and effective
address calculations necessary to access data operands in memory. It implements
three types of arithmetic to update addresses—linear, modulo, and reverse carry.
This unit operates in parallel with other chip resources to minimize address
generation overhead. The AGU contains eight address registers R[7:0] (i.e., Rn), eight
offset registers N[7:0] (i.e., Nn), and eight modifier registers M[7:0] (i.e., Mn). The Rn
are 16-bit registers that may contain an address or data. Each Rn register may
provide addresses to the X memory Address Bus (XAB), Y memory Address Bus
(YAB), and the Program Address Bus (PAB). The Nn and Mn registers are 16-bit
registers that are normally used to update the Rn registers, but may be used for data.

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AGU registers may be read from or written to via the Global Data Bus as 16-bit
operands. The AGU has two modulo arithmetic units that can generate two
independent 16-bit addresses every instruction cycle for any two of the XAB, YAB, or
PAB.

1.3.2.3 Program Control Unit

The program control unit performs instruction prefetch, instruction decoding,
hardware DO loop control, and exception processing. It contains six directly
addressable registers—the Program Counter (PC), Loop Address (LA), Loop Counter
(LC), Status Register (SR), Operating Mode Register (OMR), and Stack Pointer (SP).
The program control unit also contains a 15 level by 32-bit system stack memory. The
16-bit PC can address 65,536 (64 K) locations in program memory space.

1.3.2.4 Data Buses

Data movement on the chip occurs over four bidirectional 24-bit buses—the X Data
Bus (XDB), the Y Data Bus (YDB), the Program Data Bus (PDB), and the Global Data
Bus (GDB). Certain instructions concatenate XDB and YDB to form a 48-bit data bus.
Data transfers between the Data ALU and the two data memories, X and Y, occur
over the XDB and YDB, respectively. These transfers can occur simultaneously on the
DSP, maximizing data throughput. All other data transfers, such as I/O transfers to
internal peripherals, occur over the GDB. Instruction word pre-fetches take place
over the PDB in parallel with data transfers. Transfers between buses are
accomplished through the internal bus switch.

1.3.2.5 Address Buses

Addresses are specified for internal X data memory and Y data memory using two
unidirectional 16-bit buses—the X Address Bus (XAB) and the Y Address Bus (YAB).
program memory addresses are specified using the 16-bit Program Address Bus
(PAB).

1.3.2.6 Phase Lock Loop (PLL)

The Phase Lock Loop (PLL) reduces the need for multiple oscillators in a system
design, thus reducing the overall system cost. An additional benefit of the PLL is that
it permits the use of a low-frequency external clock with no sacrifice of processing
speed. The PLL converts the low-frequency external clock to the high speed internal
clock needed to run the DSP at maximum speed. This diminishes the electromagnetic
interference generated by high frequency clocking. The PLL performs frequency
multiplication to allow the processor to use almost any available external system
clock for full-speed operation. It also improves the synchronous timing of the
processor’s external memory port, significantly reducing the timing skew between
EXTAL and the internal chip phases when the Multiplication Factor (MF) ≤ 4. The
PLL is unique in that it provides a low power divider on its output, which can reduce
or restore the chip operating frequency without losing the PLL lock.

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1.3.2.7 On-Chip Emulation (OnCE) Port

The On-Chip Emulation (OnCE) port provides a sophisticated debugging tool that
allows simple, inexpensive, and speed-independent access to the processor’s internal
registers and peripherals. The OnCE port tells the application programmer the exact
status of most of the on-chip registers, memory locations, and buses, as well as
storing the addresses of the last five instructions that were executed.

1.3.3 Memories

The three independent memory spaces of the DSP56009—X data, Y data, and
program—and their configurations are discussed briefly here. See Section 3,

Memory, Operating Modes, and Interrupts for more detail.

1.3.3.1 Program Memory

The on-chip program memory is 24-bits wide. Addresses are received from the
Program Control Logic (usually the Program Counter) over the Program Address
Bus (PAB). Program memory may be written using MOVEM instructions. The
interrupt vectors are located in the bottom 128 locations of program memory.
Table 1-2 lists the interrupt vector addresses and indicates the Interrupt Priority
Level (IPL) of each interrupt source.

Program RAM has many advantages. It provides a means to develop code efficiently.
Programs can be changed dynamically, allowing efficient overlaying of DSP software
algorithms. In this way the on-chip Program RAM operates as a fixed cache, thereby
minimizing accesses to slower external memory.

The Bootstrap mode, described in Appendix A, provides a convenient, low-cost
method to load the DSP56009 Program RAM from a single, inexpensive EPROM
connected to the EMI, or through the SHI, using either SPI or I2C formats, after a
power-on reset.

Table 1-2 Interrupt Starting Addresses and Sources

Interrupt

Starting Address

P:$0000 3 Hardware RESET
P:$0002 3 Stack Error
P:$0004 3 Trace
P:$0006 3 SWI
P:$0008 0–2 IRQA

IPL Interrupt Source

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Table 1-2 Interrupt Starting Addresses and Sources (Continued)

Interrupt

Starting Address

P:$000A 0–2 IRQB
P:$000C Reserved

P:$000E Reserved
P:$0010 0–2 SAI Left Channel Transmitter if TXIL = 0
P:$0012 0–2 SAI Right Channel Transmitter if TXIL = 0
P:$0014 0–2 SAI Transmitter Exception if TXIL = 0
P:$0016 0–2 SAI Left Channel Receiver if RXIL = 0

P:$0018 0–2 SAI Right Channel Receiver if RXIL = 0
P:$001A 0–2 SAI Receiver Exception if RXIL = 0
P:$001C Reserved

P:$001E 3 NMI

P:$0020 0–2 SHI Transmit Data

P:$0022 0–2 SHI Transmit Underrun Error

P:$0024 0–2 SHI Receive FIFO Not Empty

P:$0026 Reserved

P:$0028 0–2 SHI Receive FIFO Full
P:$002A 0–2 SHI Receive Overrun Error
P:$002C 0–2 SHI Bus Error

P:$002E Reserved

P:$0030 0–2 EMI Write Data

P:$0032 0–2 EMI Read Data

P:$0034 0–2 EMI EBAR0 Memory Wrap

P:$0036 0–2 EMI EBAR1 Memory Wrap

P:$0038 Reserved
P:$003A Reserved
P:$003C Reserved

P:$003E 3 Illegal Instruction
P: $0040 0–2 SAI Left Channel Transmitter if TXIL = 1
P: $0042 0–2 SAI Right Channel Transmitter if TXIL = 1
P: $0044 0–2 SAI Transmitter Exception if TXIL = 1
P: $0046 0–2 SAI Left Channel Receiver if RXIL = 1
P: $0048 0–2 SAI Right Channel Receiver if RXIL = 1

IPL Interrupt Source

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Table 1-2 Interrupt Starting Addresses and Sources (Continued)

Overview

Interrupt

Starting Address

P: $004A 0–2 SAI Receiver Exception if RXIL = 1
P: $004C Reserved

: :

P: $007E Reserved

IPL Interrupt Source

1.3.3.2 X Data Memory

The on-chip X data memory is 24 bits wide. Addresses are received from the XAB,

and data transfers to the Data ALU occur on the XDB.

1.3.3.3 Y Data Memory

The on-chip Y data memory is 24 bits wide. Addresses are received from the YAB,

and data transfers to the Data ALU occur on the YDB.

1.3.3.4 On-Chip Memory Configuration Bits

Through the use of bits PEA and PEB in the OMR, four different memory

configurations are possible. These configurations provide appropriate memory sizes

for a variety of applications (see Table 1-3). Section 3 provides detailed information

about memory configuration.

Table 1-3 Internal Memory Configurations

No Switch

(PEA = 0,

PEB = 0)

Program RAM 0.5 K 1.25 K 2.0 K 2.75 K

X data RAM 4.5 K 3.75 K 3.75 K 3.0 K
Y data RAM 4.25 K 4.25 K 3.5 K 3.5 K

Program ROM 10.0 K 10.0 K 10.0 K 10.0 K

X data ROM 3.0 K 3.0 K 3.0 K 3.0 K
Y data ROM 1.75 K 1.75 K 1.75 K 1.75 K

Switch A
(PEA = 1,

PEB = 0)

Switch B
(PEA = 0,

PEB = 1)

Switch A + B

(PEA = 1,

PEB = 1)

1.3.3.5 Bootstrap ROM

The bootstrap ROM occupies locations 0–31 ($0–$1F) and 256–287 ($100–$11F) in two

areas in the memory map on the DSP56009. The bootstrap ROM is

factory-programmed to perform the bootstrap operation following hardware reset; it

either jumps to the user’s ROM starting address (P:$2000) or downloads up to 512

words of user program from either the EMI port or the SHI port (in SPI or I2C

format). The bootstrap ROM activity is controlled by the bits MA, MB, and MC,

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which are located in the OMR. When in the Bootstrap mode, the first 512 words of
Program RAM are read-disabled but write-accessible. The contents of the bootstrap
ROM are listed in Appendix A.

1.3.3.6 External Memory

The DSP56009 does not extend internal memory off chip. However, external memory
can be added using the EMI. See Section 4, External Memory Interface for a detailed
description of the EMI.

1.3.3.7 Reserved Memory Spaces

The memory spaces marked as reserved should not be accessed by the user. They are
reserved for the expansion of future versions or variants of this DSP. Write
operations to the reserved range are ignored. Read operations from addresses in the
reserved range (with values greater than or equal to $2C00 in X memory space and
$2700 in Y memory space, and values from the reserved area of program memory
space), return the value $000005, which is the opcode for the ILLEGAL instruction. If
a read access is performed from the reserved area below address $2000 in X or Y data
memory, the resulting data will be undetermined. If an instruction fetch is attempted
from addresses in the reserved area, the value returned is $000005, which is the
opcode for the ILLEGAL instruction, causing an illegal instruction interrupt service.

1.3.4 Input/Output

A variety of system configurations are facilitated by the DSP56009 Input/Output
(I/O) structure. Each I/O interface has its own control, status, and double-buffered
data registers that are memory-mapped in the X data memory space (see Table 1-4).

Table 1-4 On-chip Peripheral Memory Map

Address Register

X:$FFFF Interrupt Priority Register (IPR)
X:$FFFE Reserved
X:$FFFD PLL Control Register (PCTL)
X:$FFFC Reserved
X:$FFFB Reserved
X:$FFFA Reserved
X:$FFF9 Reserved
X:$FFF8 Reserved
X:$FFF7 GPIO Control/Data Register (GPIOR)

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Table 1-4 On-chip Peripheral Memory Map (Continued)

Address Register

X:$FFF6 EMI Write Offset Register (EWOR)
X:$FFF5 Reserved
X:$FFF4 Reserved
X:$FFF3 SHI Receive FIFO/Transmit Register (HRX/HTX)

Overview

X:$FFF2

X:$FFF1 SHI Host Control/Status Register (HCSR)
X:$FFF0 SHI Host Clock Control Register (HCKR)
X:$FFEF EMI Refresh Control Register (ERCR)
X:$FFEE EMI Data Register 1 (EDRR1/EDWR1)
X:$FFED EMI Offset Register 1 (EOR1)
X:$FFEC EMI Base Address Register 1 (EBAR1)
X:$FFEB EMI Control/Status Register (ECSR)
X:$FFEA EMI Data Register 0 (EDRR0/EDWR0)
X:$FFE9 EMI Offset Register 0 (EOR0)
X:$FFE8 EMI Base Address Register 0 (EBAR0)
X:$FFE7 SAI TX2 Data Register (TX2)
X:$FFE6 SAI TX1 Data Register (TX1)
X:$FFE5 SAI TX0 Data Register (TX0)
X:$FFE4 SAI TX Control/status Register (TCS)
X:$FFE3 SAI RX1 Data Register (RX1)

SHI I2C Slave Address Register (HSAR)

X:$FFE2 SAI RX0 Data Register (RX0)
X:$FFE1 SAI RX Control/Status Register (RCS)
X:$FFE0 SAI Baud Rate Control Register (BRC)
X:$FFDF Reserved
: :
X:$FFC0 Reserved

The EMI, SHI, and SAI also have several dedicated interrupt vector addresses and

control bits to enable and disable interrupts (see Table 1-2 on page 1-13). These

interrupt vectors minimize the overhead associated with servicing an interrupt by

immediately executing the appropriate service routine. Each interrupt can be

programmed to one of three maskable priority levels.

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1.3.4.1 External Memory Interface

The External Memory Interface (EMI) is an I/O interface that enables the DSP to
access external dynamic and/or static memory with little or no additional logic. The
EMI is implemented as a buffered peripheral rather than a transparent extension to
internal memory. This interface facilitates the storage of audio samples for digital
reverberation algorithms and permits simple implementation of large data delay
buffers in external memory. The EMI on the DSP56009 is designed to connect directly
to Dynamic RAM (DRAM) of the following sizes:

• One or two 256 K × 4 bit chips

• One or two 1 M × 4 bit chips

• One or two 4 M × 4 bits chips

When using Static RAM (SRAM), the EMI may directly access up to 256 K × 8 bits.
The external data bus width may be 4 or 8 bits. Data words of 8, 12, 16, 20 or 24 bits
may be stored and retrieved via the EMI with automatic packing and unpacking. In
addition, the EMI may be selected to operate in the SRAM/EPROM absolute
addressing mode. This allows connection to external memory devices for program
bootstrap and data storage, as well as general parallel access to peripheral devices.

1.3.4.2 Serial Host Interface (SHI)

The Serial Host Interface (SHI) provides a serial path for communication and
program/coefficient data transfers between the DSP and an external host processor
or other serial peripheral devices. This interface can connect directly to one of two
well-known and widely-used synchronous serial buses: the Serial Peripheral
Interface (SPI) bus defined by Motorola and the Inter Integrated-circuit Control (I2C)
bus defined by Philips. The SHI handles both SPI and I2C bus protocols as required
from a slave or a single-master device. In order to minimize DSP overhead, the SHI
supports single-, double-, and triple-byte data transfers. An optimal ten-word receive
FIFO register reduces the DSP overhead for data reception.

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1.3.4.3 Serial Audio Interface (SAI)

The DSP can communicate with other devices through the SAI. The SAI provides a

synchronous full-duplex serial port for serial connection with a variety of audio

devices such as Analog-to-Digital (A/D) converters, Digital-to-Analog (D/A)

converters, Compact Disk (CD) devices, etc. The SAI implements a wide range of

serial data formats in use by audio manufacturers. Examples are:

• I2S format (Philips)

• CDP format (Sony)

• MEC format (Matsushita)

• Most industry-standard serial A/D and D/A formats

The SAI consists of independent transmit and receive sections and a common baud

rate generator. The transmitter consists of three transmitters controlled by one

transmitter controller. This enables simultaneous data transmission to as many as

three stereo audio devices, or transmission of three separate stereo pairs of audio

channels. The receiver consists of two receivers and a single receive controller. This

enables simultaneous data reception from up to two stereo audio devices. The

transmit and receive sections are fully asynchronous and may transmit and receive at

different rates.

1.3.4.4 General Purpose Input/Output

The General Purpose Input/Output (GPIO) signals are used for control and

handshake functions between the DSP and external circuitry. The GPIO port has four

dedicated signals (GPIO0–GPIO3) that are controlled through a memory-mapped

register. Associated with each GPIO signal is a data bit, a control bit, and a data

direction bit that configures the pin as an input or an output, open-collector or

normal. See Section 7 for detailed information about GPIO operation.

MOTOROLA DSP56009 User’s Manual 1-19

Overview
DSP56009 Architectural Overview

1-20 DSP56009 User’s Manual MOTOROLA

SECTION 2

SIGNAL DESCRIPTIONS

MOTOROLA DSP56009 User’s Manual 2-1

Signal Descriptions

2.1 SIGNAL GROUPINGS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

2.2 POWER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2.3 GROUND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5

2.4 CLOCK AND PLL SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

2.5 EXTERNAL MEMORY INTERFACE (EMI) . . . . . . . . . . . . . . 2-7

2.6 INTERRUPT AND MODE CONTROL. . . . . . . . . . . . . . . . . 2-10

2.7 SERIAL HOST INTERFACE (SHI) . . . . . . . . . . . . . . . . . . . 2-14

2.8 SERIAL AUDIO INTERFACE (SAI). . . . . . . . . . . . . . . . . . . 2-18

2.9 GENERAL PURPOSE I/O. . . . . . . . . . . . . . . . . . . . . . . . . . 2-21

2.10 ON-CHIP EMULATION (OnCETM) PORT. . . . . . . . . . . . . . 2-22

2-2 DSP56009 User’s Manual MOTOROLA

Signal Descriptions

Signal Groupings

2.1 SIGNAL GROUPINGS

The DSP56009 input and output signals are organized into the nine functional

groups, as shown in Table 2-1. The individual signals are illustrated in Figure 2-1.

Table 2-1 DSP56009 Functional Group Signal Allocations

Functional Group Number of Signals

Power (VCC) 9 Table 2-2
Ground (GND) 13 Table 2-3
Phase Lock Loop (PLL) 3 Table 2-4
External Memory Interface (EMI) 29 Table 2-5 and

Interrupt and Mode Control 4 Table 2-7
Serial Host Interface (SHI) 5 Table 2-8
Serial Audio Interface (SAI) 9 Table 2-9 and

General Purpose Input/Output (GPIO) 4 Table 2-11
On-Chip Emulation (OnCE) port 4 Table 2-12

Total 80

Detailed

Description

Table 2-6

Table 2-10

MOTOROLA DSP56009 User’s Manual 2-3

Signal Descriptions
Signal Groupings

Power Inputs

V

CCP

V

CCQ

V

CCA

V

CCD

V

CCS

Ground

GND

GND

GND

GND

GND

PCAP

PINIT

EXTAL

MA0–MA14

MD0–MD7

MA15/MCS3
MA16/MCS2/MCAS
MA17/MCS1/MRAS

MCS0

MWR

MRD

DSP56009

3
2

2

Port B

Serial Host

Interface

P

3

Q

4

A

2

D

3

S

Port C

MOSI/HA0
SS/HA2

MISO/SDA
SCK/SCL
HREQ

Serial Audio

Interface

WSR
SCKR

PLL

Rec0
Rec1

SDI0
SDI1

WST

15

SCKT
SDO0Tran0

8

Tran1
Tran2

SDO1
SDO2

Port A

External Memory

Interface

GPIO

4

GPIO0–GPIO3

MODC/NMI

MODB/IRQB
MODA/IRQA

RESET

Figure 2-1 DSP56009 SIgnals

2-4 DSP56009 User’s Manual MOTOROLA

Mode/Interrupt
Control

Reset

80 signals

OnCE™

Port

DSCK/OS1
DSI/OS0
DSO
DR

AA0249G

2.2 POWER

Table 2-2 Power Inputs

Power Name Description

Signal Descriptions

Power

V

CCP

PLL Power —V
(PLL). The voltage should be well-regulated and the input should be
provided with an extremely low impedance path to the VCC power rail.

V

CCQ

Quiet Power—V
logic. This input must be tied externally to all other chip power inputs.
The user must provide adequate external decoupling capacitors.

V

CCA

Address Bus Power —V
address bus I/O drivers. This input must be tied externally to all other
chip power inputs. The user must provide adequate external decoupling
capacitors.

V

CCD

Data Bus Power —V
bus I/O drivers. This input must be tied externally to all other chip
power inputs. The user must provide adequate external decoupling
capacitors.

V

CCS

Serial Interface Power —V
SAI. This input must be tied externally to all other chip power inputs. The
user must provide adequate external decoupling capacitors.

2.3 GROUND

provides isolated power for the Phase Lock Loop

CCP

provides isolated power for the internal processing

CCQ

provides isolated power for sections of the

CCA

provides isolated power for sections of the data

CCD

provides isolated power for the SHI and

CCS

Table 2-3 Grounds

Ground Name Description

GND

P

PLL Ground —GNDP is ground dedicated for PLL use. The connection
should be provided with an extremely low-impedance path to ground.
V

should be bypassed to GND

CCP

by a 0.47 µF capacitor located as close

P

as possible to the chip package.

GND

Q

Quiet Ground —GNDQ provides isolated ground for the internal
processing logic. This connection must be tied externally to all other chip
ground connections. The user must provide adequate external
decoupling capacitors.

GND

A

Address Bus Ground —GNDA provides isolated ground for sections of
the address bus I/O drivers. This connection must be tied externally to all
other chip ground connections. The user must provide adequate external
decoupling capacitors.

MOTOROLA DSP56009 User’s Manual 2-5

Signal Descriptions
Clock and PLL signals

Table 2-3 Grounds (Continued)

Ground Name Description

GND

GND

D

S

Data Bus Ground —GNDD provides isolated ground for sections of the
data bus
I/O drivers. This connection must be tied externally to all other chip
ground connections. The user must provide adequate external
decoupling capacitors.

Serial Interface Ground —GNDS provides isolated ground for the SHI and SAI.
This connection must be tied externally to all other chip ground connections. The
user must provide adequate external decoupling capacitors.

2.4 CLOCK AND PLL SIGNALS

Note: While the PLL on this DSP is identical to the PLL described in the DSP56000

Family Manual, two of the signals have not been implemented externally.

Specifically, there is no PLOCK signal or CKOUT signal available. Therefore,
the internal clock is not directly accessible and there is no external indication
that the PLL is locked. These signals were omitted to reduce the number of
pins and allow this DSP to be put in a smaller, less expensive package.

Table 2-4 Clock and PLL Signals

Signal

Name

EXTAL Input Input External Clock/Crystal —This input should be connected

Signal

Type

State

during

Reset

Signal Description

to an external clock source. If the PLL is enabled, this
signal is internally connected to the on-chip PLL. The PLL
can multiply the frequency on the EXTAL pin to generate
the internal DSP clock. The PLL output is divided by two
to produce a four-phase instruction cycle clock, with the
minimum instruction time being two PLL output clock
periods. If the PLL is disabled, EXTAL is divided by two
to produce the four-phase instruction cycle clock.

2-6 DSP56009 User’s Manual MOTOROLA

External Memory Interface (EMI)

Table 2-4 Clock and PLL Signals (Continued)

Signal Descriptions

Signal

Name

PCAP Input Input PLL Filter Capacitor—This input is used to connect a

PINIT Input Input PLL Initialization (PINIT)—During the assertion of

Signal

Type

State

during

Reset

Signal Description

high-quality (high “Q” factor) external capacitor needed
for the PLL filter. The capacitor should be as close as
possible to the DSP with heavy, short traces connecting
one terminal of the capacitor to PCAP and the other
terminal to V
specified in the DSP56009 Technical Data sheets.

When short lock time is critical, low dielectric absorption
capacitors such as polystyrene, polypropylene, or teflon
are recommended.

If the PLL is not used (i.e., it remains disabled at all
times), there is no need to connect a capacitor to the
PCAP pin. It may remain unconnected, or be tied to
either Vcc or GND.

hardware reset, the value on the PINIT line is written into
the PEN bit of the PCTL register. When set, the PEN bit
enables the PLL by causing it to derive the internal clocks
from the PLL voltage controlled oscillator output. When
the bit is cleared, the PLL is disabled and the DSP’s
internal clocks are derived from the clock connected to
the EXTAL signal. After hardware RESET is deasserted,
the PINIT signal is ignored.

. The required capacitor value is

CCP

2.5 EXTERNAL MEMORY INTERFACE (EMI)

Table 2-5 External Memory Interface (EMI) Signals

Signal Name

MA0–MA14 Output Table 2-6 Memory Address Lines 0–14—MA0–MA10

MOTOROLA DSP56009 User’s Manual 2-7

Signal

Type

State

during

Reset

Signal Description

provide the multiplexed row/column
addresses for DRAM accesses and MA0–MA14
provide the non-multiplexed address lines 0–14
for SRAM accesses.

Signal Descriptions
External Memory Interface (EMI)

Table 2-5 External Memory Interface (EMI) Signals (Continued)

Signal Name

MA15/MCS3 Output Table 2-6 Memory Address Line 15 (MA15)/Memory

MA16/MCS2/
MCAS

MA17/MCS1/
MRAS

Signal

Type

Output Table 2-6 Memory Address Line 16 (MA16)/Memory

Output Table 2-6 Memory Address Line 17 (MA17)/Memory

State

during

Reset

Signal Description

Chip Select 3 (MCS3)—This line functions as

the non-multiplexed address line 15 or as
memory chip select 3 for SRAM accesses.

Chip Select 2 (MCS2)/Memory Column
Address Strobe (MCAS)— This line functions

as the non-multiplexed address line 16 or as
memory chip select 2 for SRAM accesses. This
line also functions as the Memory Column
Address Strobe (MCAS) during DRAM
accesses.

Chip Select 1 (MCS1)/Memory Row Address
Strobe (MRAS)—This line functions as the

non-multiplexed address line 17 or as chip
select 1 for SRAM accesses. This line also
functions as the Memory Row Address Strobe
during DRAM accesses.

MCS0 Output Table 2-6 Memory Chip Select 0—This line functions as

memory chip select 0 for SRAM accesses.

MWR Output Table 2-6 Memory Write Strobe—This line is asserted

when writing to external memory.

MRD Output Table 2-6 Memory Read Strobe—This line is asserted

when reading external memory.

MD0–MD7 Bi-

directional

Tri-stated Data Bus—These signals provide the

bidirectional data bus for EMI accesses. They
are inputs during reads from external memory,
outputs during writes to external memory, and
tri-stated if no external access is taking place. If
the data bus width is defined as four bits wide,
only signals MD0–MD3 are active, while signals
MD4–MD7 remain tri-stated. While tri-stated,
MD0–MD7 are disconnected from the pins and
do not require external pull-ups.

2-8 DSP56009 User’s Manual MOTOROLA

External Memory Interface (EMI)

.

Table 2-6 EMI Operating States

Operating Mode

Signal Descriptions

Signal Function

MA0–MA14 —

MA15/MCS3

MA15

MCS3

MA16/MCS2/

MCAS

MA16

MCS2

MCAS:
DRAM
refresh
disabled
DRAM
refresh
enabled

MA17/MCS1/

MRAS

MA17

MCS1

Hardware

Reset

Software

Reset

Driven High Previous

State

Driven High

Driven High

Driven High

Driven High

Driven High

Driven High

Driven High

Driven High

Driven High

Driven High

Driven High

Driven High

Driven High

Driven High

Driven High

Driven High

Individual

Reset

Stop Mode

Previous State Previous State

Previous State

Driven High

Previous State

Driven High

Driven High

Driven Low

Previous State

Driven High

Previous State

Driven High

Previous State

Driven High

Driven High

Driven High

Previous State

Driven High

MRAS:
DRAM
refresh
disabled

Driven High

Driven High

Driven High

Driven High
DRAM
refresh
enabled

Driven High

Driven High

Driven Low

Driven High

MCS0 — Driven High Driven High Driven High Driven High

MWR — Driven High Driven High Driven High Driven High

MRD — Driven High Driven High Driven High Driven High

MOTOROLA DSP56009 User’s Manual 2-9

Signal Descriptions
Interrupt and Mode Control

2.6 INTERRUPT AND MODE CONTROL

The interrupt and mode control signals select the DSP’s operating mode as it comes
out of hardware reset and receives interrupt requests from external sources after
reset.

Table 2-7 Interrupt and Mode Control Signals

Signal

Name

MODA

Signal

Type

Input Input

State during

Reset

(MODA)

Signal Description

Mode Select A—This input signal has three

functions:

• to work with the MODB and MODC signals
to select the DSP’s initial operating mode,

• to allow an external device to request a DSP
interrupt after internal synchronization, and

• to turn on the internal clock generator when
the DSP in the Stop processing state, causing
the DSP to resume processing.

MODA is read and internally latched in the DSP
when the processor exits the Reset state. The logic
state present on the MODA, MODB, and MODC pins
selects the initial DSP operating mode. Several clock
cycles after leaving the Reset state, the MODA signal
changes to the external interrupt request IRQA. The
DSP operating mode can be changed by software
after reset.

IRQA

2-10 DSP56009 User’s Manual MOTOROLA

External Interrupt Request A (IRQA)—The IRQA
input is a synchronized external interrupt request. It
may be programmed to be level-sensitive or
negative-edge-triggered. When the signal is edge
triggered, triggering occurs at a voltage level and is
not directly related to the fall time of the interrupt
signal. However, as the fall time of the interrupt
signal increases, the probability that noise on IRQA
will generate multiple interrupts also increases.

While the DSP is in the Stop mode, asserting IRQA
gates on the oscillator and, after a clock stabilization
delay, enables clocks to the processor and
peripherals. Hardware reset causes this input to
function as MODA.

Signal Descriptions

Interrupt and Mode Control

Table 2-7 Interrupt and Mode Control Signals (Continued)

Signal

Name

MODB

IRQB

Signal

Type

Input Input

State during

Reset

(MODB)

Signal Description

Mode Select B— This input signal has two functions:

• to work with the MODA and MODC signals
to select the DSP’s initial operating mode, and

• to allow an external device to request a DSP
interrupt after internal synchronization.

MODB is read and internally latched in the DSP
when the processor exits the Reset state. The logic
state present on the MODA, MODB, and MODC pins
selects the initial DSP operating mode. Several clock
cycles after leaving the Reset state, the MODB signal
changes to the external interrupt request IRQB. The
DSP operating mode can be changed by software
after reset.

External Interrupt Request B (IRQB)—The IRQB
input is a synchronized external interrupt request. It
may be programmed to be level-sensitive or
negative-edge-triggered. When the signal is
edge-triggered, triggering occurs at a voltage level
and is not directly related to the fall time of the
interrupt signal. However, as the fall time of the
interrupt signal increases, the probability that noise
on IRQB will generate multiple interrupts also
increases. Hardware reset causes this input to
function as MODB.

MOTOROLA DSP56009 User’s Manual 2-11

Signal Descriptions
Interrupt and Mode Control

Table 2-7 Interrupt and Mode Control Signals (Continued)

Signal

Name

MODC/
NMI

Signal

Type

Input,
edge­triggered

State during

Reset

Input
(MODC)

Signal Description

Mode Select C—This input signal has two functions:

• to work with the MODA and MODB signals
to select the DSP’s initial operating mode, and

• to allow an external device to request a DSP
interrupt after internal synchronization.

MODC is read and internally latched in the DSP
when the processor exits the Reset state. The logic
state present on the MODA, MODB, and MODC pins
selects the initial DSP operating mode. Several clock
cycles after leaving the Reset state, the MODC signal
changes to the Non-Maskable Interrupt request,
NMI. The DSP operating mode can be changed by
software after reset.

Non-Maskable Interrupt Request—The NMI input
is a negative-edge-triggered external interrupt
request. This is a level 3 interrupt that can not be
masked out. Triggering occurs at a voltage level and
is not directly related to the fall time of the interrupt
signal. However, as the fall time of the interrupt
signal increases, the probability that noise on NMI
will generate multiple interrupts also increases.
Hardware reset causes this input to function as
MODC.

2-12 DSP56009 User’s Manual MOTOROLA

Signal Descriptions

Interrupt and Mode Control

Table 2-7 Interrupt and Mode Control Signals (Continued)

Signal

Name

RESET input active RESET—This input causes a direct hardware reset of

Signal

Type

State during

Reset

Signal Description

the processor. When RESET is asserted, the DSP is
initialized and placed in the Reset state. A
Schmitt-trigger input is used for noise immunity. When
the reset signal is deasserted, the initial DSP operating
mode is latched from the MODA, MODB, and MODC
signals. The DSP also samples the PINIT signal and
writes its status into the PEN bit of the PLL Control
Register. When the DSP comes out of the Reset state,
deassertion occurs at a voltage level and is not
directly related to the rise time of the RESET signal.
However, the probability that noise on RESET will
generate multiple resets increases with increasing
rise time of the RESET signal.

For proper hardware reset to occur, the clock must be
active, since a number of clock ticks are required for
proper propagation of the hardware reset state.

MOTOROLA DSP56009 User’s Manual 2-13

Signal Descriptions
Serial Host Interface (SHI)

2.7 SERIAL HOST INTERFACE (SHI)

The Serial Host Interface (SHI) has five I/O signals, which may be configured to

operate in either SPI or I

2

C mode. Table 2-8 lists the SHI signals.

Table 2-8 Serial Host Interface (SHI) signals

State

during

Signal Description

Reset

Tri-stated SPI Serial Clock (SCK)—The SCK signal is an

output when the SPI is configured as a master, and
a Schmitt-trigger input when the SPI is configured
as a slave. When the SPI is configured as a master,
the SCK signal is derived from the internal SHI
clock generator. When the SPI is configured as a
slave, the SCK signal is an input, and the clock
signal from the external master synchronizes the
data transfer. The SCK signal is ignored by the SPI
if it is defined as a slave and the Slave Select (SS)
signal is not asserted. In both the master and slave
SPI devices, data is shifted on one edge of the SCK
signal and is sampled on the opposite edge where
data is stable. Edge polarity is determined by the
SPI transfer protocol.
I2C Serial Clock (SCL)—SCL carries the clock for
bus transactions in the I2C mode. SCL is a
Schmitt-trigger input when configured as a slave,
and an open-drain output when configured as a
master. SCL should be connected to VCC through a
pull-up resistor. The maximum allowed internally
generated bit clock frequency is
mode and

Fosc

/6 for the I2C mode where F

Fosc

/4 for the SPI

osc

is the
clock on EXTAL. The maximum allowed
externally generated bit clock frequency is
for the SPI mode and

Fosc

/5 for the I2C mode. This

Fosc

signal is tri-stated during hardware reset, software
reset, or individual reset (no need for external
pull-up in this state).

Signal Name

SCK

SCL

Signal

Type

Input or
Output

Input or
Output

/3

2-14 DSP56009 User’s Manual MOTOROLA

Signal Descriptions

Serial Host Interface (SHI)

Table 2-8 Serial Host Interface (SHI) signals (Continued)

Signal Name

MISO

SDA

Signal

Type

Input or
Output

Input or
Output

State

during

Signal Description

Reset

Tri-stated SPI Master-In-Slave-Out (MISO)— When the SPI

is configured as a master, MISO is the master data
input line. The MISO signal is used in conjunction
with the MOSI signal for transmitting and
receiving serial data. This signal is a
Schmitt-trigger input when configured for the SPI
Master mode, an output when configured for the
SPI Slave mode, and tri-stated if configured for the
SPI Slave mode when SS is deasserted.
I2C Serial Data and Acknowledge (SDA)—In I2C
mode, SDA is a Schmitt-trigger input when
receiving and an open-drain output when
transmitting. SDA should be connected to VCC
through a pull-up resistor. SDA carries the data for
I2C transactions. The data in SDA must be stable
during the high period of SCL. The data in SDA is
only allowed to change when SCL is low. When
the bus is free, SDA is high. The SDA line is only
allowed to change during the time SCL is high in
the case of Start and Stop events. A high-to-low
transition of the SDA line while SCL is high is an
unique situation, and is defined as the Start event.
A low-to-high transition of SDA while SCL is high
is an unique situation, and is defined as the Stop
event.

MOTOROLA DSP56009 User’s Manual 2-15

Note: This line is tri-stated during hardware reset,

software reset, or individual reset (no need for
external pull-up in this state).

Signal Descriptions
Serial Host Interface (SHI)

Table 2-8 Serial Host Interface (SHI) signals (Continued)

Signal Name

MOSI

HA0

Signal

Type

Input or
Output

Input

State

during

Signal Description

Reset

Tri-stated SPI Master-Out-Slave-In (MISO)—When the SPI

is configured as a master, MOSI is the master data
output line. The MOSI signal is used in
conjunction with the MISO signal for transmitting
and receiving serial data. MOSI is the slave data
input line when the SPI is configured as a slave.
This signal is a Schmitt-trigger input when
configured for the SPI Slave mode.
I2C Slave Address 0 (HA0)—This signal uses a
Schmitt-trigger input when configured for the I2C
mode. When configured for I2C Slave mode, the
HA0 signal is used to form the slave device
address. HA0 is ignored when the SHI is
configured for the I2C Master mode.

Note: This signal is tri-stated during hardware reset,

software reset, or individual reset (no need for
external pull-up in this state).

SS

HA2

Input

Input

Tri-stated SPI Slave Select (SS)—This signal is an active low

Schmitt-trigger input when configured for the SPI
mode. When configured for the SPI Slave mode,
this signal is used to enable the SPI slave for
transfer. When configured for the SPI Master
mode, this signal should be kept deasserted. If it is
asserted while configured as SPI master, a bus
error condition will be flagged.
I2C Slave Address 2 (HA2)—This signal uses a
Schmitt-trigger input when configured for the I2C
mode. When configured for the I2C Slave mode,
the HA2 signal is used to form the slave device
address. HA2 is ignored in the I2C Master mode. If
SS is deasserted, the SHI ignores SCK clocks and
keeps the MISO output signal in the
high-impedance state.

Note: This signal is tri-stated during hardware reset,

software reset, or individual reset (no need for
external pull-up in this state).

2-16 DSP56009 User’s Manual MOTOROLA

Signal Descriptions

Serial Host Interface (SHI)

Table 2-8 Serial Host Interface (SHI) signals (Continued)

Signal Name

Signal

Type

HREQ Input or

Output

State

during

Signal Description

Reset

Tri-stated Host Request—This signal is an active low

Schmitt-trigger input when configured for the
Master mode, but an active low output when
configured for the Slave mode. When configured
for the Slave mode, HREQ is asserted to indicate
that the SHI is ready for the next data word
transfer and deasserted at the first clock pulse of
the new data word transfer. When configured for
the Master mode, HREQ is an input and when
asserted by the external slave device, it will trigger
the start of the data word transfer by the master.
After finishing the data word transfer, the master
will await the next assertion of HREQ to proceed
to the next transfer.

Note: This signal is tri-stated during hardware,

software, individual reset, or when the
HREQ[1:0] bits (in the HCSR) are cleared (no
need for external pull-up in this state).

MOTOROLA DSP56009 User’s Manual 2-17

Signal Descriptions
Serial Audio Interface (SAI)

2.8 SERIAL AUDIO INTERFACE (SAI)

The SAI is composed of separate receiver and transmitter sections.

2.8.1 SAI Receiver Section

Table 2-9 Serial Audio Interface (SAI) Receiver signals

Signal

Name

Signal

Type

State

during

Reset

Signal Description

SDI0 Input Tri-stated Serial Data Input 0—While in the high

impedance state, the internal input buffer is
disconnected from the pin and no external
pull-up is necessary. SDI0 is the serial data
input for receiver 0.

Note: This signal is high impedance during

hardware or software reset, while receiver 0
is disabled (R0EN = 0), or while the DSP is
in the Stop state.

SDI1 Input Tri-stated Serial Data Input 1—While in the high

impedance state, the internal input buffer is
disconnected from the pin and no external
pull-up is necessary. SDI1 is the serial data
input for receiver 1.

Note: This signal is high impedance during

hardware or software reset, while receiver 1
is disabled (R1EN = 0), or while the DSP is
in the Stop state.

SCKR Input or

Tri-stated Receive Serial Clock—SCKR is an output if the

Output

2-18 DSP56009 User’s Manual MOTOROLA

receiver section is programmed as a master,
and a Schmitt-trigger input if programmed as a
slave. While in the high impedance state, the
internal input buffer is disconnected from the
pin and no external pull-up is necessary.

Note: SCKR is high impedance if all receivers are

disabled (individual reset) and during
hardware or software reset, or while the
DSP is in the Stop state.

Signal Descriptions

Serial Audio Interface (SAI)

Table 2-9 Serial Audio Interface (SAI) Receiver signals (Continued)

Signal

Name

Signal

Type

WSR Input or

Output

State

during

Signal Description

Reset

Tri-stated Word Select Receive (WSR)—WSR is an

output if the receiver section is configured as a
master, and a Schmitt-trigger input if
configured as a slave. WSR is used to
synchronize the data word and to select the
left/right portion of the data sample.

Note: WSR is high impedance if all receivers are

disabled (individual reset), during
hardware reset, during software reset, or
while the DSP is in the Stop state. While in
the high impedance state, the internal input
buffer is disconnected from the signal and
no external pull-up is necessary.

MOTOROLA DSP56009 User’s Manual 2-19

Signal Descriptions
Serial Audio Interface (SAI)

2.8.2 SAI Transmitter Section

Table 2-10 Serial Audio Interface (SAI) Transmitter signals

Signal

Name

Signal

Type

State

during

Reset

SDO0 Output Driven

High

SDO1 Output Driven

High

SDO2 Output Driven

High

SCKT Input or

Tri-stated Serial Clock Transmit (SCKT)—This signal

Output

Signal Description

Serial Data Output 0 (SDO0)—SDO0 is the serial

output for transmitter 0. SDO0 is driven high if
transmitter 0 is disabled, during individual reset,
hardware reset, and software reset, or when the DSP
is in the Stop state.

Serial Data Output 1 (SDO1)—SDO1 is the serial
output for transmitter 1. SDO1 is driven high if
transmitter 1 is disabled, during individual reset,
hardware reset and software reset, or when the DSP
is in the Stop state.

Serial Data Output 2 (SDO2)—SDO2 is the serial
output for transmitter 2. SDO2 is driven high if
transmitter 2 is disabled, during individual reset,
hardware reset and software reset, or when the DSP
is in the Stop state.

provides the clock for the SAI. SCKT can be an
output if the transmit section is configured as a
master, or a Schmitt-trigger input if the transmit
section is configured as a slave. When the SCKT is an
output, it provides an internally generated SAI
transmit clock to external circuitry. When the SCKT
is an input, it allows external circuitry to clock data
out of the SAI.

2-20 DSP56009 User’s Manual MOTOROLA

Note: SCKT is high impedance if all transmitters are

disabled (individual reset), during hardware reset,
software reset, or while the DSP is in the Stop
state. While in the high impedance state, the
internal input buffer is disconnected from the pin
and no external pull-up is necessary.

Signal Descriptions

General Purpose I/O

Table 2-10 Serial Audio Interface (SAI) Transmitter signals (Continued)

Signal

Name

Signal

Type

WST Input or

Output

State

during

Reset

Tri-stated Word Select Transmit (WST)—WST is an output if

the transmit section is programmed as a master, and
a Schmitt-trigger input if it is programmed as a slave.
WST is used to synchronize the data word and select
the left/right portion of the data sample.

Note: WST is high impedance if all transmitters are

2.9 GENERAL PURPOSE I/O

Table 2-11 General Purpose I/O (GPIO) Signals

Signal Description

disabled (individual reset), during hardware or
software reset, or while the DSP is in the Stop
state. While in the high impedance state, the
internal input buffer is disconnected from the pin
and no external pull-up is necessary.

Signal

Name

GPIO0–
GPIO3

Signal

Type

Standard

Output,

Open-drain

Output, or

Input

State during

Reset

Signal Description

Disconnected GPIO lines can be used for control and

handshake functions between the DSP and
external circuitry. Each GPIO line can be
configured individually as disconnected,
open-drain output, standard output, or an
input.

Note: Hardware reset or software reset

configures all the GPIO lines as
disconnected (external circuitry
connected to these pins may need
pull-ups until the pins are configured
for operation).

MOTOROLA DSP56009 User’s Manual 2-21

Signal Descriptions
On-Chip Emulation (OnCETM) Port

2.10 ON-CHIP EMULATION (OnCETM) PORT

There are four signals associated with the OnCE port controller and its serial
interface.

Table 2-12 On-Chip Emulation Port Signals

Signal

Name

DSI

OS0

Signal

Type

Input

Output

State

during

Reset

Output,
Driven
Low

Signal Description

Debug Serial Input (DSI)—The DSI signal is the

signal through which serial data or commands are
provided to the OnCE port controller. The data
received on the DSI signal will be recognized only
when the DSP has entered the Debug mode of
operation. Data must have valid TTL logic levels
before the serial clock falling edge. Data is always
shifted into the OnCE port Most Significant Bit (MSB)
first.

Operating Status 0 (OS0)—When the DSP is not in
the Debug mode, the OS0 signal provides
information about the DSP status if it is an output
and used in conjunction with the OS1 signal. When
switching from output to input, the signal is
tri-stated.

Note: If the OnCE port is in use, an external

pull-down resistor should be attached to the
DSI/OS0 signal. If the OnCE port is not in use,
the resistor is not required.

2-22 DSP56009 User’s Manual MOTOROLA

Signal Descriptions

On-Chip Emulation (OnCETM) Port

Table 2-12 On-Chip Emulation Port Signals (Continued)

Signal

Name

DSCK

OS1

Signal

Type

Input

Output

State

during

Reset

Output,
Driven
Low

Signal Description

Debug Serial Clock (DSCK)—The DSCK/OS1

signal, when an input, is the signal through which
the serial clock is supplied to the OnCE port. The
serial clock provides pulses required to shift data
into and out of the OnCE port. Data is clocked into
the OnCE port on the falling edge and is clocked
out of the OnCE port on the rising edge.

Operating Status 1 (OS1)—If the OS1 signal is an
output and used in conjunction with the OS0
signal, it provides information about the DSP
status when the DSP is not in the Debug mode. The
debug serial clock frequency must be no greater
than 1/8 of the processor clock frequency. The
signal is tri-stated when it is changing from input
to output.

Note: If the OnCE port is in use, an external

pull-down resistor should be attached to the
DSCK/OS1 pin. If the OnCE port is not in use,
the resistor is not required.

MOTOROLA DSP56009 User’s Manual 2-23

Signal Descriptions
On-Chip Emulation (OnCETM) Port

Table 2-12 On-Chip Emulation Port Signals (Continued)

Signal

Name

DSO Output Driven

Signal

Type

State

during

Reset

High

Signal Description

Debug Serial Output (DSO)—The DSO line

provides the data contained in one of the OnCE
port controller registers as specified by the last
command received from the command controller.
The Most Significant Bit (MSB) of the data word is
always shifted out of the OnCE port first. Data is
clocked out of the OnCE port on the rising edge of
DSCK.

The DSO line also provides acknowledge pulses to
the external command controller. When the DSP
enters the Debug mode, the DSO line will be
pulsed low to indicate that the OnCE port is
waiting for commands. After receiving a read
command, the DSO line will be pulsed low to
indicate that the requested data is available and the
OnCE port is ready to receive clock pulses in order
to deliver the data. After receiving a write
command, the DSO line will be pulsed low to
indicate that the OnCE port is ready to receive the
data to be written; after the data is written, another
acknowledge pulse will be provided.

Note: During hardware reset and when idle, the DSO

line is held high.

2-24 DSP56009 User’s Manual MOTOROLA

Signal Descriptions

On-Chip Emulation (OnCETM) Port

Table 2-12 On-Chip Emulation Port Signals (Continued)

Signal

Name

Signal

Type

State

during

Reset

Signal Description

DR Input Input Debug Request (DR)—The debug request input

provides a means of entering the Debug mode of
operation. This signal, when asserted (pulled low),
will cause the DSP to finish the current instruction
being executed, to save the instruction pipeline
information, to enter the Debug mode, and to wait
for commands to be entered from the debug serial
input line. While the DSP is in the Debug mode, the
user can reset the OnCE port controller by
asserting DR, waiting for an acknowledge pulse on
DSO, and then deasserting DR. It may be necessary
to reset the OnCE port controller in cases where
synchronization between the OnCE port controller
and external circuitry is lost. Asserting DR when
the DSP is in the Wait or the Stop mode, and
keeping it asserted until an acknowledge pulse in
the DSP is produced, puts the DSP into the Debug
mode. After receiving the acknowledge pulse, DR
must be deasserted before sending the first OnCE
port command. For more information, see Methods
Of Entering The Debug Mode in the DSP56000
Family Manual.

Note: If the OnCE port is not in use, an external

pull-up resistor should be attached to the DR
line.

MOTOROLA DSP56009 User’s Manual 2-25

Signal Descriptions
On-Chip Emulation (OnCETM) Port

2-26 DSP56009 User’s Manual MOTOROLA

SECTION 3

MEMORY, OPERATING MODES,

AND INTERRUPTS

Memory, Operating Modes, and Interrupts

3.1 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

3.2 DSP56009 DATA AND PROGRAM MEMORY . . . . . . . . . . . 3-3

3.3 DSP56009 DATA AND PROGRAM MEMORY MAPS . . . . . 3-5

3.4 OPERATING MODE REGISTER (OMR). . . . . . . . . . . . . . . 3-11

3.5 OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12

3.6 INTERRUPT PRIORITY REGISTER. . . . . . . . . . . . . . . . . . 3-14

3.7 PHASE LOCK LOOP (PLL) CONFIGURATION . . . . . . . . . 3-18

3.8 HARDWARE RESET OPERATION. . . . . . . . . . . . . . . . . . . 3-19

3-2 DSP56009 User’s Manual MOTOROLA

Memory, Operating Modes, and Interrupts

Introduction

3.1 INTRODUCTION

The DSP56009 program and data memories are independent, and the on-chip data
memory is divided into two separate memory spaces, X and Y. There are also two
on-chip data ROMs in the X and Y data memory spaces, and a bootstrap ROM that
can overlay part of the Program RAM. The data memories are divided into two
independent spaces to work with the two address ALUs to feed two operands
simultaneously to the Data ALU. Through the use of Program RAM Enable bits (PEA
and PEB) in the Operating Mode Register (OMR), four different memory
configurations are possible to provide appropriate memory sizes for a variety of
applications (see Table 3-1).

Table 3-1 Internal Memory Configurations

No Switch

Memory

Program RAM 0.5 K 1.25 K 2.0 K 2.75 K

X data RAM 4.5 K 3.75 K 3.75 K 3.0 K

Y data RAM 4.25 K 4.25 K 3.5 K 3.5 K

Program ROM 10.0 K 10.0 K 10.0 K 10.0 K

X data ROM 3.0 K 3.0 K 3.0 K 3.0 K

Y data ROM 1.75 K 1.75 K 1.75 K 1.75 K

(PEA = 0,

PEB = 0)

Switch A
(PEA = 1,

PEB = 0)

Switch B
(PEA = 0,

PEB = 1)

Switch A + B

(PEA = 1,

PEB = 1)

This section also includes details of the interrupt vectors and priorities and describes
the effect of a hardware reset on the PLL Multiplication Factor (MF).

3.2 DSP56009 DATA AND PROGRAM MEMORY

External memory cannot be accessed as a direct extension of the internal memory.
The internal data and program memory configurations are shown in Table 3-1.

MOTOROLA DSP56009 User’s Manual 3-3

Memory, Operating Modes, and Interrupts
DSP56009 Data And Program Memory

3.2.1 X Data ROM

The X data ROM occupies locations $2000–$2BFF in the X data memory space. The
functions contained in the X data ROM are listed in the DSP56009 Technical Data
sheet. For more detailed information, contact the Motorola DSP technical help line.

3.2.2 Y Data ROM

The Y data ROM occupies locations $2000–$26FF in the Y data memory space. The
functions contained in the Y data ROM are listed in the DSP56009 Technical Data
sheet. For more detailed information, contact the Motorola DSP technical help line.

3.2.3 Program ROM

The program ROM occupies locations $2000–$47FF in the program memory space.
The functions contained in the program ROM are listed in the DSP56009 Technical
Data sheet. For more detailed information, contact the Motorola DSP technical help
line.

3.2.4 Bootstrap ROM

The bootstrap ROM occupies locations 0–31 ($0–$1F) and 256–287 ($100–$11F) in two
areas in the bootstrap memory map. The bootstrap ROM is factory-programmed to
perform the bootstrap operation following hardware reset. It either jumps to the
user’s ROM starting address (P:$2000), or downloads up to 512 words of user
program from an external Erasable Programmable ROM (EPROM) attached to the
EMI port, or from the SHI port in SPI or I2C formats. The bootstrap ROM activity is
controlled by the Mode bits (MA, MB, and MC) in the OMR. When in the Bootstrap
mode, the first 512 words of Program RAM are disabled for read but accessible for
write.

Programs are loaded from external EPROM if MC:MB:MA = 001. The internal
Program RAM is loaded with 1,536 consecutive bytes from an EPROM connected to
the EMI. The EPROM is located at the EMI address $0, when operating the EMI in the
Absolute Addressing SRAM mode (EAM[2:0] = 000). It is assumed that the EPROM
is selected (enabled) through the GPIO3 pin, which is driven low in this Bootstrap
mode. The GPIO3 output is programmed to be of the active high/active low type.

3-4 DSP56009 User’s Manual MOTOROLA

Memory, Operating Modes, and Interrupts

DSP56009 Data And Program Memory Maps

The bytes will be packed into 512 24-bit words and stored in contiguous Program
RAM memory locations starting at P:$0000.

Note: The routine loads data starting with the least significant byte of P:$0000.

Programs can be loaded from the SHI in the SPI mode if MC:MB:MA = 101, or in the
I2C mode if MC:MB:MA = 111. The internal Program RAM is loaded with up to 512
words that are 24-bits long and are received through the SHI. The SHI operates in the
Slave mode, with the 10-word FIFO enabled, and with the HREQ pin enabled for
receive operation. The OnCE port is enabled by the bootstrap code.

The contents of the bootstrap ROM are provided in Appendix A.

3.2.5 Reserved Memory Spaces

The reserved memory spaces should not be accessed by the user. They are reserved
for future expansion. Write operations to the reserved range are ignored. Read
operations from addresses in the reserved range return the value $000005. If an
instruction fetch is attempted from an address in the reserved area, the value
returned is $000005, which is the opcode for the ILLEGAL instruction.

3.3 DSP56009 DATA AND PROGRAM MEMORY MAPS

The memory in the DSP56009 can be mapped into four different configurations
according to the PEA and PEB bits in the OMR. Memory maps for each of the four
configurations are shown in Figure 3-1, Figure 3-2, Figure 3-3, and Figure 3-4 on
the following pages.

MOTOROLA DSP56009 User’s Manual 3-5

Memory, Operating Modes, and Interrupts
DSP56009 Data And Program Memory Maps

X Data

$FFFF
$FFC0
$FFBF

$2C00
$2BFF

$2000
$1FFF

$1200
$11FF

$0000 $0000

Internal I/O

Reserved

Internal

ROM

Reserved

Internal

RAM

$FFFF

$2700
$26FF

$2000
$1FFF

$1100
$10FF

Figure 3-1 Memory Maps for PEA = 0, PEB = 0

X Data

$FFFF
$FFC0

$FFBF
$2C00

$2BFF

$2000
$1FFF

$1200
$11FF

$0F00
$0EFF

$0C00
$0BFF

$0000 $0000

Internal I/O

Reserved

Internal

ROM

Reserved

Internal

Ram

Reserved

Internal

RAM

$FFFF

$2700
$26FF

$2000

$1FFF

$1100
$10FF

Y Data

Reserved

Internal

ROM

Reserved

Internal

RAM

Y Data

Reserved

Internal

ROM

Reserved

Internal

RAM

$FFFF

$4800
$47FF

$2000
$1FFF

$0200
$01FF

$0000

$FFFF

$4800
$47FF

$2000

$1FFF

$0B00
$0AFF

$0800
$07FF

$0200
$01FF

$0000

Program

Reserved

Internal

ROM

Reserved

Internal RAM

AA0287

Program

Reserved

Internal

ROM

Reserved

Internal RAM

Reserved

Internal RAM

AA0288

Figure 3-2 Memory Maps for PEA = 1, PEB = 0

3-6 DSP56009 User’s Manual MOTOROLA

Memory, Operating Modes, and Interrupts

DSP56009 Data And Program Memory Maps

X Data

$FFFF
$FFC0
$FFBF

$2C00
$2BFF

$2000
$1FFF

$0F00
$0EFF

$0000 $0000

Internal I/O

Reserved

Internal

ROM

Reserved

Internal

RAM

$FFFF

$2700
$26FF

$2000

$1FFF

$0E00
$0DFF

Figure 3-3 Memory Maps for PEA = 0, PEB = 1

X Data

$FFFF
$FFC0
$FFBF

$2C00
$2BFF

$2000
$1FFF

Internal I/O

Reserved

Internal

ROM

$FFFF

$2700
$26FF

$2000

$1FFF

Y Data

Reserved

Internal

ROM

Reserved

Internal

RAM

Y Data

Reserved

Internal

ROM

Program

$FFFF

Reserved

$4800
$47FF

Internal

ROM

$2000

$1FFF

Reserved

$0800
$07FF

Internal

RAM

$0000

AA0289

Program

$FFFF

Reserved

$4800
$47FF

Internal

ROM

$2000

$1FFF

Reserved

$0C00
$0BFF

Internal

RAM

$0000 $0000

Figure 3-4 Memory Maps for PEA = 1, PEB = 1

MOTOROLA DSP56009 User’s Manual 3-7

$0E00
$0DFF

Reserved

Internal

RAM

Reserved

$0B00
$0AFF

Internal

RAM

$0000

AA0290

Memory, Operating Modes, and Interrupts
DSP56009 Data And Program Memory Maps

3.3.1 Dynamic Switching of Memory Configurations

The internal memory configuration is altered by re-mapping RAM modules from X
and Y data memories into program memory space and vise-versa. Data contents of
the switched RAM modules are preserved.

The memory can be dynamically switched from one configuration to another by
changing PEA and PEB bits in OMR. The address ranges that are directly affected by
the switch operation are P:$0200...$0AFF, X:$0C00...$11FF and Y:$0E00...$10FF (see

Figure 3-1 on page 3-6, Figure 3-2 on page 3-6, Figure 3-3 on page 3-7, and
Figure 3-4). The memory switch can be accomplished provided that the affected

address ranges are not being accessed during the instruction cycle in which the
switch operation takes place. Specifically, these two conditions must be observed for
troublefree dynamic switching:

• No accesses to or from X:$0C00...$11FF or Y:$0E00...$10FF are allowed during
the switch cycle.

• No accesses (including instruction fetches) to/from P:$0200...$0AFF are
allowed during the switch cycle.

Note: The switch actually occurs 3 instruction cycles after the instruction that

modifies PEA/PEB bits.

Any sequence that complies with the switch conditions is valid. For example, if the
program flow executes in the address range that is not affected by the switch (other
than P:$0200...$0AFF), the switch conditions can be met very easily. In this case a
switch can be accomplished by just changing PEA/PEB bits in OMR in the regular
program flow, assuming no accesses to X:$0C00...$11FF or Y:$0E00...$10FF occur up
to 3 instructions after the instruction that changes the OMR bits.

A more intricate case is that in which a switch memory operation takes place while
the program flow is being executed (or should proceed) in the affected program
address range (P:$0200...$0AFF). In this case, a particular switch sequence should be
performed. Interrupts must be disabled before executing the switch sequence, since
an interrupt could cause the DSP to fetch instructions out of sequence. The interrupts
must be disabled at least 4 instruction cycles before switching, due to pipeline latency
of the interrupt processing.

Special attention should be given when running a memory switch routine using the
OnCE port. Running the switch routine in Trace mode, for example, can cause the
switch to complete after the PEA/PEB bit changes while the DSP is in Debug mode.
As a result, subsequent instructions might be fetched according to the new memory
configuration (after the switch), and thus might execute improperly. A general

3-8 DSP56009 User’s Manual MOTOROLA

Memory, Operating Modes, and Interrupts

DSP56009 Data And Program Memory Maps

purpose routine in which the switch conditions are always met, independent of
where the program flow originates (before the switch) or where it proceeds (after the
switch) is shown below:

;Switch to Program RAM enabled:
ORI #03,MR ; Disable interrupts
INST1 ; Four instruction cycles guarantee no interrupts
INST2 ; after interrupts were disabled.
INST3 ; INST# denotes a one-word instruction, however,
INST4 ; two one-word instructions can be replaced by

; one two-word instruction.
ORI #$C,OMR ; Set PEA/PEB bits in OMR
ANDI #$FC,MR ; Allow a delay for remapping,

; meanwhile re-enable interrupts
JMP >Next_Address ; 2-word (long) jump instruction (uninterruptable)

;Switch to Program RAM disabled:
ORI #03,MR ; Disable interrupts
INST1 ; Four instruction cycles guarantee no interrupts
INST2 ; after interrupts were disabled.
INST3 ; INST# denotes any one-word instruction, however,
INST4 ; two one-word instructions can be replaced by

; one two-word instruction.
ANDI #$F3,OMR ; Clear PEA/PEB bit in OMR
ANDI #$FC,MR ; Allow a delay for remapping,

; meanwhile re-enable interrupts
JMP >Next_Address ; 2-word (long) jump instruction (uninterruptable)

Note: “Next_Address” is any valid program address in the new memory

configuration (after the switch). The 2-word instruction “JMP
>Next_Address” can be replaced by a sequence of an NOP followed by a
1-word “JMP <Next_Address” (jump short) instruction. In cases in which
interrupts are already disabled, the sequence would be a write to OMR with
PE modified (ORI/ANDI/MOVEC), followed by an NOP as a delay for
remapping, and then followed by a JMP >long (or another NOP and JMP
<short instead).

3.3.2 Internal I/O Memory Map

The DSP56009 on-chip peripheral modules have their register files programmed to
the addresses in the internal I/O memory range as shown in Table 3-2 on page 3-10.

Note: Location X:$FFFE is the Bus Control Register (BCR) for the DSP56000 core.

Although labelled reserved on the DSP56009, the BCR remains active. The
BCR is cleared by reset and should remain cleared (i.e., do not write to this
location) since the DSP56009 does not make use of the BCR function.

MOTOROLA DSP56009 User’s Manual 3-9

Memory, Operating Modes, and Interrupts
DSP56009 Data And Program Memory Maps

Table 3-2 Internal I/O Memory Map

Location Register

X: $FFFF Interrupt Priority Register (IPR)

X: $FFFE Reserved
X: $FFFD PLL Control Register (PCTL)
X: $FFFC Reserved

X: $FFFB Reserved
X: $FFFA Reserved

X: $FFF9 Reserved
X: $FFF8 Reserved
X: $FFF7 GPIO Control/Data Register (GPIOR)
X: $FFF6 EMI Write Offset Register (EWOR)
X: $FFF5 Reserved
X: $FFF4 Reserved
X: $FFF3 SHI Receive FIFO/Transmit Register (HRX/HTX)
X: $FFF2

X: $FFF1 SHI Host Control/Status Register (HCSR)
X: $FFF0 SHI Host Clock Control Register (HCKR)

X: $FFEF EMI Refresh Control Register (ERCR)
X: $FFEE EMI Data Register 1 (EDRR1/EDWR1)
X: $FFED EMI Offset Register 1 (EOR1)
X: $FFEC EMI Base Address Register 1 (EBAR1)
X: $FFEB EMI Control/Status Register (ECSR)
X: $FFEA EMI Data Register 0 (EDRR0/EDWR0)

X: $FFE9 EMI Offset Register 0 (EOR0)

X: $FFE8 EMI Base Address Register 0 (EBAR0)

X: $FFE7 SAI TX2 Data Register (TX2)

X: $FFE6 SAI TX1 Data Register (TX1)

X: $FFE5 SAI TX0 Data Register (TX0)

X: $FFE4 SAI TX Control/Status Register (TCS)

X: $FFE3 SAI RX1 Data Register (RX1)

X: $FFE2 SAI RX0 Data Register (RX0)

X: $FFE1 SAI RX Control/Status Register (RCS)

X: $FFE0 SAI Baud Rate Control Register (BRC)
X: $FFDF Reserved

SHI I2C Slave Address Register (HSAR)

3-10 DSP56009 User’s Manual MOTOROLA

Memory, Operating Modes, and Interrupts

Operating Mode Register (OMR)

Table 3-2 Internal I/O Memory Map (Continued)

Location Register

: :

X: $FFC0 Reserved

3.4 OPERATING MODE REGISTER (OMR)

The Operating Mode Register (OMR) is illustrated in Figure 3-5.

012345623 7

MAMBPEAPEBMCSD

Bits 5 and 7–23 are reserved, read as 0s, and should be written with 0s
for future compatibility.

Operating Mode A,B
Program RAM Enable A
Program RAM Enable B
Operating Mode C
Stop Delay

AA0291k

Figure 3-5 Operating Mode Register (OMR)

3.4.1 DSP Operating Mode (MC, MB, MA)—Bits 4, 1, and 0

The DSP operating mode bits, MC, MB, and MA, select the operating mode of the
DSP56009. These operating modes are described in Section 3.5 Operating Modes
on the following page. On hardware reset, MC, MB, and MA are loaded from the
external mode select pins MODC, MODB, and MODA, respectively. After the DSP
leaves the reset state, MC, MB, and MA can be changed under software control.

3.4.2 Program RAM Enable A (PEA)—Bit 2

The Program RAM Enable A (PEA) bit is used to map 768 words of the internal X
data memory into internal Program RAM. When PEA is set, 768 words of X data
RAM (locations $0C00–$0EFF) are mapped into the program memory space
(locations $0800–$0AFF). The internal memory maps, as controlled by the PEA bit,

MOTOROLA DSP56009 User’s Manual 3-11

Memory, Operating Modes, and Interrupts
Operating Modes

are shown in Figure 3-1 on page 3-6 and Figure 3-2 on page 3-6. PEA is cleared by
hardware reset.

3.4.3 Program RAM Enable B (PEB)—Bit 3

The Program RAM Enable B (PEB) bit is used to map 768 words of the internal X data
memory and 768 words of the internal Y data memory into internal Program RAM.
When PEB is set, 768 words of X data RAM (locations $0F00–$11FF) and 768 words of
Y data RAM (locations $0E00–$10FF) are mapped into the program space (locations
$0200–$07FF). The internal memory maps, as controlled by the PEB bit, are shown in

Figure 3-3 on page 3-7 and Figure 3-4 on page 3-7. PEB is cleared by hardware reset.

3.4.4 Stop Delay (SD)—Bit 6

When leaving the Stop state, the Stop Delay (SD) bit is interrogated. If cleared
(SD = 0), a 65,535 core clock cycle delay (131,072 T states) is implemented before
continuation of the STOP instruction cycle. If the SD bit is set (SD = 1), the delay
before continuation of the STOP instruction cycle is set as eight clock cycles (16 T
states). When the DSP is driven by a stable external clock source, setting the SD bit
before executing the STOP instruction will allow a faster start up of the DSP.

3.5 OPERATING MODES

The DSP56009 operating modes are defined as described below and summarized in
Table 3-3 on page 3-13. The operating modes are latched from pins MODA, MODB,
and MODC during reset and can be changed by writing to the OMR. The operating
modes defined are compatible with the DSP56004. One new mode was defined,
mode 2, which ends up in the first location of the Program ROM (address $2000).
Each operating mode is described below.

• Mode 0—In this mode, the internal Program RAM is enabled and the

bootstrap ROM is disabled. All bootstrap programs end by selecting this
operating mode. This is identical to the DSP56001/DSP56002 Mode 0. It is not
possible to reach this operating mode during hardware reset. If an attempt is
made, the chip will default to Mode 1. Mode 1 bootstrap terminates by setting
the operating mode to 0 and jumping to the reset vector at address $0000.

3-12 DSP56009 User’s Manual MOTOROLA

Memory, Operating Modes, and Interrupts

Operating Modes

• Mode 1—In this mode, the bootstrap ROM is enabled and the bootstrap

program is executed after hardware reset. The internal Program RAM is
loaded with up to 512 words from an external byte-wide static memory
connected to the External Memory Interface (EMI). The EMI operates in the
SRAM Absolute Addressing mode with the slowest SRAM timing. It is
assumed that the chip select control for the external memory is the GPIO3 pin.

• Mode 2—In this mode, the bootstrap ROM is enabled and the bootstrap

program is executed after hardware reset. The bootstrap program ends up in
the first location of the Program ROM (program address $2000).

• Mode 3—Reserved—It is not possible to reach this operating mode during

hardware reset. If an attempt is made, the chip will default to mode 1.

• Mode 4—Reserved

• Mode 5—In this mode, the bootstrap ROM is enabled and the bootstrap

program is executed after hardware reset. The internal Program RAM is
loaded with up to 512 words from the Serial Host Interface (SHI). The SHI
operates in the SPI Slave mode, with 24-bit word width. Mode 5 bootstrap
terminates by setting the operating mode to 0 and jumping to the reset vector
at address $0000.

• Mode 6—Reserved

• Mode 7—In this mode, the bootstrap ROM is enabled and the bootstrap

program is executed after hardware reset. The internal Program RAM is
loaded with up to 512 words from the Serial Host Interface (SHI). The SHI
operates in the I2C Slave mode, with 24-bit word width. Mode 7 bootstrap
terminates by setting the operating mode to 0 and jumping to the reset vector
at address $0000.

Table 3-3 Operating Modes

Mode

0 000 Normal operation, bootstrap disabled
1 001 Bootstrap from EMI
2 010 Wake up in Program ROM address $2000
3 011 Reserved
4 100 Reserved
5 101 Bootstrap from SHI (SPI mode)
6 110 Reserved
7 111

MMM

C B A

Operating Mode

Bootstrap from SHI (I2C mode)

MOTOROLA DSP56009 User’s Manual 3-13

Memory, Operating Modes, and Interrupts
Interrupt Priority Register

Note: The OnCE port operation is enabled at hardware reset. This means the device

can enter the Debug mode at any time after hardware reset.

3.6 INTERRUPT PRIORITY REGISTER

Interrupt priorities are determined in the 24-bit Interrupt Priority Register (IPR). The
Interrupt Priority Level (IPL) for each on-chip peripheral device and for two of the
external interrupt sources, can be programmed, under software control, to one of
three maskable priority levels (IPL 0,1, or 2). IPLs are set by writing to the IPR. The
IPR configuration is shown in Figure 3-6.

011 10 9 8 7 6 5 4 3 2 1

IAL1 IAL0IAL2IBL0IBL1IBL2SAL0SAL1

IRQA Mode
IRQB Mode
Reserved
SAI IPL

1223 22 21 20 19 18 17 16 15 14 13

SHL1 SHL0EML0EML1

SHI IPL
EMI IPL
Reserved

Reserved, read as 0, and should be written with 0s for future compatibility.

AA0292

Figure 3-6 Interrupt Priority Register (Address X:$FFFF)

• Bits 0–5 of the IPR are used by the DSP56000 core for two of the external
interrupt request inputs, IRQA (IAL[2:0]) and IRQB (IBL[2:0]). Assuming the
same IPL, IRQA has higher priority than IRQB.

• Bits 6–9 and 16–23 are reserved for future use.

• Bits 10–15 are available for determining IPLs for each peripheral (EMI, SHI,
SAI). Two IPL bits are required for each peripheral interrupt group.

The interrupt priorities are shown in Table 3-4 and the interrupt vectors are shown
in Table 3-5.

3-14 DSP56009 User’s Manual MOTOROLA

Memory, Operating Modes, and Interrupts

Table 3-4 Interrupt Priorities

Priority Interrupt

Level 3 (Nonmaskable)

Interrupt Priority Register

Highest

Lowest

Highest

Hardware RESET

Illegal Instruction

NMI

Stack Error

Trace

SWI

Levels 0, 1, 2 (Maskable)

IRQA

IRQB

SAI Receiver Exception

SAI Transmitter Exception

SAI Left Channel Receiver

SAI Left Channel Transmitter

SAI Right Channel Receiver

Lowest

SAI Right Channel Transmitter

SHI Bus Error

SHI Receive Overrun Error

SHI Transmit Underrun Error

SHI Receive FIFO Full

SHI Transmit Data

SHI Receive FIFO Not Empty

EMI EBAR0 Memory Wrap

EMI EBAR1 Memory Wrap

EMI Read Data

EMI Write Data

MOTOROLA DSP56009 User’s Manual 3-15

Memory, Operating Modes, and Interrupts
Interrupt Priority Register

Table 3-5 Interrupt Vectors

Address Interrupt Source

P: $0000 Hardware RESET
P: $0002 Stack Error
P: $0004 Trace
P: $0006 SWI
P: $0008 IRQA

P: $000A IRQB

P: $000C Reserved

P: $000E Reserved
P: $0010 SAI Left Channel Transmitter if TXIL = 0
P: $0012 SAI Right Channel Transmitter if TXIL = 0
P: $0014 SAI Transmitter Exception if TXIL = 0
P: $0016 SAI Left Channel Receiver if RXIL = 0
P: $0018 SAI Right Channel Receiver if RXIL = 0

P: $001A SAI Receiver Exception if RXIL = 0

P: $001C Reserved

P: $001E NMI
P: $0020 SHI Transmit Data
P: $0022 SHI Transmit Underrun Error
P: $0024 SHI Receive FIFO Not Empty
P: $0026 Reserved
P: $0028 SHI Receive FIFO Full

P: $002A SHI Receive Overrun Error

P: $002C SHI Bus Error

P: $002E Reserved
P: $0030 EMI Write Data
P: $0032 EMI Read Data
P: $0034 EMI EBAR0 Memory Wrap
P: $0036 EMI EBAR1 Memory Wrap
P: $0038 Reserved

: :

3-16 DSP56009 User’s Manual MOTOROLA

Memory, Operating Modes, and Interrupts

Interrupt Priority Register

Table 3-5 Interrupt Vectors (Continued)

Address Interrupt Source

P: $003C Reserved

P: $003E Illegal Instruction
P: $0040 SAI Left Channel Transmitter if TXIL = 1
P: $0042 SAI Right Channel Transmitter if TXIL = 1
P: $0044 SAI Transmitter Exception if TXIL = 1
P: $0046 SAI Left Channel Receiver if RXIL = 1

P: $0048 SAI Right Channel Receiver if RXIL = 1
P: $004A SAI Receiver Exception if RXIL = 1
P: $004C Reserved

: :

P: $007E Reserved

MOTOROLA DSP56009 User’s Manual 3-17

Memory, Operating Modes, and Interrupts
Phase Lock Loop (PLL) Configuration

3.7 PHASE LOCK LOOP (PLL) CONFIGURATION

Section 9 of the DSP56000 Family Manual provides detailed information about the
Phase Lock Loop (PLL). The PLL Multiplication Factor (MF) and the clock applied to
EXTAL determine the frequency at which the Voltage Controlled Oscillator (VCO)
will oscillate, that is, the output frequency of the PLL.

If the PLL is used as the DSP internal clock:

• the PLL VCO output is used directly as the internal DSP clock if the PLL
Control Register (PCTL) Chip Clock Source Bit (CSRC) is set, and

• the PLL VCO frequency is divided by the Low Power Divider (LPD) and then
used as the internal DSP clock if CSRC is cleared.

The DSP56009 PLL multiplication factor is set to 3 during hardware reset, which
means that the Multiplication Factor bits (MF[11:0]) in the PCTL are set to $002. The
PLL may be disabled (PEN = 0) upon reset by pulling the PINIT pin low. The DSP
will subsequently operate at the frequency of the clock applied to the EXTAL pin
until the PEN bit is set. This reset value cannot be modified by the user until the DSP
comes out of reset. The Low Power Divider (LPD) Division Factor bits (DF[3:0] in the
PCTL) are cleared during hardware reset. Once the PEN bit is set, it cannot be cleared
by software.

EXTAL

Phase

Detector

(PD)

Charge

Pump

Loop
Filter

Multiplication

Voltage

Controlled

Oscillator

(VCO)

Frequency

Multiplier

Factor

1 to 4096

MF[11:0]

Figure 3-7 PLL Configuration

Low

Power

Divider

20 to 2

DF[3:0]

Divider Out

15

VCO Out

AA0293k

3-18 DSP56009 User’s Manual MOTOROLA

Memory, Operating Modes, and Interrupts

Hardware Reset Operation

3.8 HARDWARE RESET OPERATION

The processor enters the Reset processing state after the external RESET pin is
asserted (hardware reset occurs) for the specified minimum time (See DSP56009
Technical Data sheet). The Reset state:

• resets internal peripheral devices by initializing their control registers as
described in the individual peripheral sections,

• sets the modifier registers to $FFFF,

• clears the Interrupt Priority Register (IPR),

• clears the Stack Pointer (SP),

• clears the Scaling mode (S[1:0]), Trace mode (T), Loop Flag (LF), Double
precision Multiply mode (DM), and Condition Code Register (CCR) bits in the
Status Register (SR) and sets the Interrupt mask (I[1:0]) bits, and

• clears the Stop Delay (SD) bit and the Program RAM Enable (PEA and PEB)
bits in the OMR.

The DSP remains in the Reset state until the RESET pin is deasserted. When the
processor leaves the Reset state it:

• loads the chip operating mode (MC, MB, and MA) bits of the OMR from the
external mode select pins (MODC, MODB, MODA), and

• begins program execution of the bootstrap ROM starting at address $0000.

Note: Refer to the DSP56000 Family Manual for detailed information about the IPR,

SR, and OMR.

MOTOROLA DSP56009 User’s Manual 3-19

Memory, Operating Modes, and Interrupts
Hardware Reset Operation

3-20 DSP56009 User’s Manual MOTOROLA

SECTION 4

EXTERNAL MEMORY INTERFACE

MOTOROLA DSP56009 User’s Manual 4-1

External Memory Interface

4.1 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

4.2 EMI PROGRAMMING MODEL . . . . . . . . . . . . . . . . . . . . . . . 4-5

4.3 EMI ADDRESS GENERATION. . . . . . . . . . . . . . . . . . . . . . 4-23

4.4 DRAM REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31

4.5 EMI OPERATING CONSIDERATIONS. . . . . . . . . . . . . . . . 4-38

4.6 DATA-DELAY STRUCTURE. . . . . . . . . . . . . . . . . . . . . . . . 4-46

4.7 EMI-TO-MEMORY CONNECTION . . . . . . . . . . . . . . . . . . . 4-48

4.8 EMI TIMING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-50

4-2 DSP56009 User’s Manual MOTOROLA

External Memory Interface

Introduction

4.1 INTRODUCTION

The External Memory Interface (EMI) enables the DSP to access external dynamic
and/or static memory with no (or minimal) additional logic. The EMI permits simple
implementation of data-delay buffers in external memory and is often used for audio
sample storage, as required by digital reverberation algorithms. The EMI is designed
to connect directly to one or two page-mode DRAM devices of the following sizes: 64
K

×

4, 256 K
access up to 256 K
8-, 12-, 16-, 20- or 24-bits can be stored and retrieved via the EMI with automatic
packing and unpacking. In addition, the EMI can be configured to operate in the
Absolute Addressing mode. This allows connection to external memory devices for
program bootstrap and data storage, as well as general parallel access to external
memory-mapped peripheral devices.

×

4, 1 M

×

4, and 4 M

×

8 bits. The data bus width can be 4- or 8-bits wide. Data words of

×

4 bits. When using SRAMs, the EMI can directly

4.1.1 Theory of Operation

The DSP views the EMI as a memory-mapped peripheral. The EMI functions as a
memory-mapped peripheral in which data transfers are performed by moving data
to/from data registers, and control is exercised by polling status flags in the
control/status register or by servicing interrupts. An external memory write is
executed by writing the data into the EMI Data Write Register (EDWR). This will
trigger the EMI operation in which the EDWR contents are transferred to the external
memory device. The EDWR is free for the next write operation when signalled by a
status bit or by an interrupt request. An external memory read is triggered by either
writing to the EMI Offset Register (EOR) or reading the EMI Data Read Register
(EDRR). This will trigger an EMI read operation in which the data is read from the
external memory device and is stored in the EDRR. The end of operation is signaled
by a status bit or by an interrupt request.

MOTOROLA DSP56009 User’s Manual 4-3

External Memory Interface
Introduction

4.1.2 EMI Features

The main features of the EMI are:

• Direct connection to several possible memory device configurations:
– One or two DRAM devices of 64 K
– SRAM addressing with one device select and 256 K address range
– SRAM addressing with two device selects and 128 K address range
– SRAM addressing with four device selects and 32 K address range
– Additional SRAM or peripheral addressing with address range of 32 K
– Data bus can be 4 or 8 bits wide
– Data words can be 8, 12, 16, 20 or 24 bits long
– Automatic data pack/unpack to fit and orient external bus width and

external word length to internal 24-bit word format

• Programmable timing features:
– Independently selectable timing for SRAM or DRAM
– Automatic DRAM refresh by internal refresh timer
– Two timing modes for DRAM, sixteen timing modes for SRAM

• Address Features:
– Relative Addressing for data-delay buffers

×

4, 256 K

×

4, 1 M

×

4 or 4 M

×

4 bits

– DRAM Absolute Addressing for efficient data storage
– Absolute Addressing for program bootstrap and overlays (SRAM or

EPROM), and to access external peripherals
– Two base registers to handle two delay buffers in parallel
– Base-offset address calculation for data-delay buffers
– Optional base address post update (increment)

4-4 DSP56009 User’s Manual MOTOROLA

4.2 EMI PROGRAMMING MODEL

External Memory Interface

EMI Programming Model

The EMI registers available to the programmer are shown in

Figure 4-1

on page 4-6.
All accessible registers are mapped into the internal I/O memory space. These
registers can be accessed through regular MOVE instructions or by peripheral move
(MOVEP) instructions. The registers are described in the following sections. The
interrupt vector table for the EMI is shown in Table 4-1 . The interrupts generated by
the EMI are prioritized, as shown in Table 4-2 . Since either a read condition or a
write condition (but not both) can trigger an interrupt, the read data and write data
interrupts share the same level of priority.

Table 4-1 EMI Interrupt Vector

Address Interrupt Source

P: $0030 EMI Write Data

P: $0032 EMI Read Data

P: $0034 EMI EBAR0 Memory Wrap

P: $0036 EMI EBAR1 Memory Wrap

Table 4-2 EMI Internal Interrupt Priorities

Priority Interrupt Source

highest EMI EBAR0 Memory Wrap

EMI EBAR1 Memory Wrap

lowest EMI Read or Write Data

MOTOROLA DSP56009 User’s Manual 4-5

External Memory Interface
EMI Programming Model

023

X: $FFEF

X: $FFEB

X: $FFE8

X: $FFEC

(EOR0) X: $FFE9

(EOR1) X: $FFED

(EDRR0) X: $FFEA
(EDRR1) X: $FFEE

Refresh Control Register (ERCR)

Control/Status Register (ECSR)

Base Address Register 0 (EBAR0)

Base Address Register 1 (EBAR1)

Write Offset Register (EWOR)

Offset Register (EOR)

Data Read Register (EDRR)

023

023

023

023X: $FFF6

023

023

Global Data Bus (GDB)

(EDWR0) X: $FFEA
(EDWR1) X: $FFEE

023

Data Write Register (EDWR)

023

Data Register Buffer (EDRB)

To EMI Data Bus

Figure 4-1 EMI Registers

4-6 DSP56009 User’s Manual MOTOROLA

External Memory Interface

EMI Programming Model

4.2.1 EMI Base Address Registers (EBAR0 and EBAR1)

The read/write 24-bit EMI Base Address Registers (EBAR0 and EBAR1) contain the
base address used by the EMI to calculate the address (in external memory) of the
word to be accessed. During a read access, the word address is formed by subtracting
the value in the EOR from the value in either EBAR0 or EBAR1 (EBARx). During a
write access, the word address is formed by subtracting the contents of the Write
Offset Register (EWOR) from the contents of EBARx. The EBARx contents can be
incremented after the memory access. The increment operates on all 24 bits of
EBARx. The base address is stored in 24-bit unsigned integer format.

4.2.2 EMI Write Offset Register (EWOR)

The read/write 24-bit EMI Write Offset Register (EWOR) is used by the EMI to
calculate the address (in external memory) of the word to be accessed during write
operations. The address is formed by subtracting the contents of the EWOR from the
contents of EBARx. The offset is stored in 24-bit unsigned integer format. The EWOR
contains a displacement value (from the start of the data-delay buffer) and is used to
access a delayed data sample location. For example, assuming that EBARx points to
the sample at time 0, then in order to write the data sample delayed by N, the value
of N should be written into the EWOR.

Note: The EWOR is cleared by hardware reset and software reset.

MOTOROLA DSP56009 User’s Manual 4-7

External Memory Interface
EMI Programming Model

4.2.3 EMI Offset Register (EOR)

The EMI uses the read/write 24-bit EMI Offset Register (EOR) to calculate the
address (in external memory) of the word to be accessed during read operations. The
EOR is a single 24-bit register that is mapped to two different memory locations
(EOR0 and EOR1). The address is formed by subtracting the contents of the EOR
from the contents of EBARx. The offset is stored in 24-bit unsigned integer format.
The EOR contains a displacement value (from the start of the data-delay buffer) and
is used to access delayed data samples. For example, assuming that EBARx points to
the sample at time 0, then to read the data sample delayed by N, the value of N is
written into the EOR. The EOR has two addresses: $XFFE9 (EOR0) and $XFFED
(EOR1). When the ECSR EMI Read Trigger Select (ERTS) bit (see Figure 4-2 ) is
cleared, writing to EOR0 triggers an EMI memory read operation that will use the
value in the EOR and the value in the EBAR0 for address calculation. Writing to
EOR1 when the ERTS bit is cleared triggers an EMI memory read operation that will
use the values in the EOR and the EBAR1 for address calculation. The EOR is cleared
by hardware reset and software reset. See

(EDRR)

on page 4-9

for a description of operation when the ERTS bit is set.

Section 4.2.5 EMI Data Read Register

3

4567891011

EAM1

EIS0 EINREINWEIS1

ESTM1

EAM2

EAM3EMWIE

1617181920212223

EWL2

EWL1

EAM0

15

EBSY EBDFEME ERTSESTM0 EDTMESTM2ESTM3 EDRF

EWL0

012

EBW

EMI Data Bus Width
EMI Data Word Length

EMI Addressing Mode

Increment EBAR (Read)
Increment EBAR (Write)
Read/Write Interrupt Select
Memory-Wrap Interrupt Enable

121314

EDWE

EDWR Empty
EDRR Full
EDRB & EDRR Full
EMI Busy Status
EMI Data Word Length
EMI Read Trigger Select
EMI DRAM Timing
EMI SRAM Timing
EMI Enable

AA0402

Figure 4-2 EMI Control/Status Register (ECSR)

4-8 DSP56009 User’s Manual MOTOROLA

External Memory Interface

EMI Programming Model

4.2.4 EMI Data Write Registers (EDWR)

The EMI Data Write Register (EDWR) is a single 24-bit write-only register that is
mapped to two memory addresses and is used when writing data to memory. Data
to be transferred to external memory is written into either EDWR0 or EDWR1. The
contents of the written register are transferred to the Data Register Buffer for
memory writes. All transfers to/from EDWR0 or EDWR1 are 24-bit transfers.
Writing to EDWR0 ($FFEA) triggers an EMI memory write operation that will use
EBAR0 and EWOR to generate the word address. Writing to EDWR1 ($FFEA)
triggers an EMI memory write operation that will use EBAR1 and EWOR to generate
the word address.

4.2.5 EMI Data Read Register (EDRR)

The EMI Data Read Register (EDRR) is a single 24-bit read-only register that is
mapped to two memory addresses and is used when reading data from memory.
Data to be received from external memory arrives in the EDRR, and can be read from
either the $FFEA (EDRR0) or the $FFEE (EDRR1) memory location. The contents of
the Data Register Buffer are transferred to the EDRR at the end of a memory read if
the EDRR is empty. All transfers to/from the EDRR are 24-bit transfers. Reading
EDRR0 ($FFEA) when the ERTS bit (in the ECSR) is set triggers an EMI memory read
operation that will use EBAR0 and EOR to generate the word address. Reading
EDRR1 when the ERTS bit (in the ECSR) is set triggers an EMI memory read
operation that will use EBAR1 and EOR to generate the word address. See

4.2.3 EMI Offset Register (EOR)

ERTS is cleared.

on page 4-8 for a description of the operation when

Section

4.2.6 EMI Data Register Buffer (EDRB)

Data pack and unpack procedures during memory accesses are performed in the
24-bit EMI Data Register Buffer (EDRB). Since the EMI data bus is either 4- or 8-bits
wide and the words for transfer are 8-, 12-, 16-, 20-, or 24-bits wide, the data word
must be sliced (unpacked) into data-bus-width segments for storage in memory, or
must be packed when reading memory. When writing 8-bit or 16-bit words to
external memory, only the most significant 8 or 16 bits of the EDRB contents are
transferred. When reading 8-bit or 16-bit words from external memory, the words are
left-aligned and zero-extended (to the right) before being transferred to the EDRR.
When writing 12-bit or 20-bit words to external memory via a 4-bit data bus, only the
most significant 12 or 20 bits of the EDRB contents are transferred. Similarly, when

MOTOROLA DSP56009 User’s Manual 4-9

External Memory Interface
EMI Programming Model

reading 12-bit or 20-bit words from external memory via a 4-bit data bus, the words
are left-aligned and zero-extended to the right before being transferred to the EDRR.
When 12-bit or 20-bit words are transferred via 8-bit data bus, 16 or 24 bits, are
transferred in both read and write directions. While packing or unpacking, the data
word is held in the EDRB. During memory writes, the data to be written is
transferred from the EDWR to the EDRB for unpacking. The EDRB cannot be
accessed by the DSP directly.

4.2.7 EMI Control/Status Register (ECSR)

The EMI Control/Status Register (ECSR) is a 24-bit read/write register used by the
DSP to control and interrogate the EMI operation. The ECSR bits are shown in

Figure 4-2 and described in the following paragraphs.

Note: If ECSR control bits are changed while the EMI is busy (with the exception of

the ECSR interrupt controls EMWIE, EIS[1:0], and the read trigger select
ERTS), improper operation can result.

4.2.7.1 EMI Data Bus Width (EBW)—Bit 0

The read/write control bit EMI Data Bus Width (EBW) defines the width of the EMI
data bus. When EBW is cleared (EBW = 0), the data bus is 4 bits wide. When EBW is
set (EBW = 1), the data bus is 8 bits wide. The bus width affects the number of
memory accesses and address generation required for a data word transfer. The
number of memory accesses performed by the EMI during a word transfer and the
number of memory locations required for a word storage (for words of different
lengths), in both Relative and Absolute Addressing modes, is shown in Table 4-3 .

Note: EBW is cleared by hardware reset and software reset.

Table 4-3 EMI Memory Accesses and Locations Per Word

Memory

Addressing Bus Width Word Length

Relative 4 8 2 2

locations/

word

Memory

accesses/

word

Relative 4 12 4 3
Relative 4 16 4 4
Relative 4 20 8 5
Relative 4 24 8 6
Relative 4 16 Data/24 Address 8 4

4-10 DSP56009 User’s Manual MOTOROLA

External Memory Interface

EMI Programming Model

Table 4-3 EMI Memory Accesses and Locations Per Word (Continued)

Memory

Addressing Bus Width Word Length

Relative 8 8 1 1
Relative 8 12 2 2
Relative 8 16 2 2
Relative 8 20 4 3
Relative 8 24 4 3

Relative 8 16 Data/24 Address 4 2
Absolute 4 8 2 2
Absolute 4 12 3 3
Absolute 4 16 4 4
Absolute 4 20 5 5
Absolute 4 24 6 6
Absolute 4 16 Data/24 Address 4 4
Absolute 8 8 1 1

locations/

word

Memory

accesses/

word

Absolute 8 12 2 2
Absolute 8 16 2 2
Absolute 8 20 3 3
Absolute 8 24 3 3
Absolute 8 16 Data/24 Address 2 2

4.2.7.2 EMI Word Length (EWL[2:0])—Bits 16,2, and 1

The read/write control bits EMI Word Length (EWL[2:0]) select the length of the data
word to be transferred. The encoding of EWL[2:0] is shown in Table 4-4 .

Note: EWL[2:0] are cleared by hardware reset and software reset.

Table 4-4 EMI Word Length

EWL2 EWL1 EWL0 Word Length

0 0 0 8-bit data word

0 0 1 16-bit data word

MOTOROLA DSP56009 User’s Manual 4-11

External Memory Interface
EMI Programming Model

Table 4-4 EMI Word Length (Continued)

EWL2 EWL1 EWL0 Word Length

0 1 0 24-bit data word

0 1 1 16-bit data word/24-bit data addressing

1 0 0 Reserved

1 0 1 12-bit data word

1 1 0 20-bit data word

1 1 1 Reserved

4.2.7.3 EMI Addressing Mode (EAM[3:0])—Bits 6–3

The read/write EMI Addressing Mode (EAM[3:0]) control bits select the addressing
mode of the EMI. The addressing modes are shown in Table 4-5 . The values in
EAM[3:0] select which functions will be performed by the EMI pins and if the device
being accessed is an SRAM or DRAM.

Note: EAM[3:0] are cleared by hardware reset and software reset.

Table 4-5 EMI Addressing Modes

EAM

[3:0]

1,2

0000

0001 SRAM Relative MA[17:0] MCS0 n.a. 256 K

0010 SRAM Relative MA[16:0] MCS

0011 SRAM Relative MA[14:0] MCS

0100 DRAM Relative MA[7:0] na yes 64 K

0101 DRAM Relative MA[8:0] na yes 256 K

0110 DRAM Relative MA[9:0] na yes 1 M

0111 DRAM Relative MA[10:0] na yes 4 M

10xx Reserved

Type Addressing

SRAM Absolute MA[14:0] None Refresh

Address

Lines

Chip

Select

[1:0] n.a. 256 K

[3:0] n.a. 128 K

RAS/

CAS

only

Address

Range

32 K

1100

2

DRAM Absolute MA[7:0] na yes 64 K

4-12 DSP56009 User’s Manual MOTOROLA

External Memory Interface

EMI Programming Model

Table 4-5 EMI Addressing Modes (Continued)

EAM

[3:0]

2

1101

2

1110

2

1111

Note: 1. In this mode, MCS0

2. In the Absolute Addressing modes, if post-increment of EBAR is enabled and

Type Addressing

DRAM Absolute MA[8:0] na yes 256 K

DRAM Absolute MA[9:0] na yes 1 M

DRAM Absolute MA[10:0] na yes 4 M

active only during DRAM refresh cycles. Devices to be addressed using this mode
should be enabled with some hardware external to the EMI, such as a GPIO pin.

multiple memory accesses are required for a word transfer, EBAR will be
incremented after each memory access.

and MA15 are held high. MRAS and MCAS, if enabled, are

Address

Lines

Chip

Select

RAS/

CAS

Address

Range

The maximum number of word locations that can be stored in the external memory
when using the SRAM addressing modes is shown in Table 4-6 . The maximum
number of word locations that can be stored in the external memory when using the
DRAM, in both Relative and Absolute Addressing modes, is shown in
on page 4-14 and

Table 4-8

on page 4-15. When using the 16-bit word length with

Table 4-7

24-bit addressing (EWL[2:0] = 011), the number of available word locations is the
same as those for 16-bit word length in the Absolute Addressing modes and the same
as those for 24-bit length in the Relative Addressing modes.

Table 4-6 EMI Maximum SRAM Size

EAM[3:0] Bus Width Word Length Number of Words

0000 4 8 16 K

0000 4 12 10,922

0000 4 16 8 K

0000 4 20 6,553

0000 4 24 5,461

0000 8 8 32 K

0000 8 12 or 16 16 K

0000 8 20 or 24 10,922

0001 and 0010 4 8 128 K

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External Memory Interface
EMI Programming Model

Table 4-6 EMI Maximum SRAM Size (Continued)

EAM[3:0] Bus Width Word Length Number of Words

0001 and 0010 4 12 or 16 64 K

0001 and 0010 4 20 or 24 32 K

0001 and 0010 8 8 256 K

0001 and 0010 8 12 or 16 128 K

0001 and 0010 8 20 or 24 64 K

0011 4 8 64 K

0011 4 12 or 16 32 K

0011 4 20 or 24 16 K

0011 8 8 128 K

0011 8 12 or 16 64 K

0011 8 20 or 24 32 K

Table 4-7 EMI Maximum DRAM Size (Relative Addressing)

EAM[3:0] Bus Width Word Length DRAM devices

0100 4 8

0100 4 12 or 16

0100 4 20 or 24

0100 8 8

0100 8 12 or 16

0100 8 20 or 24

0101 4 8

64 K

64 K

64 K

2

×

2 ×
2 ×

256 K ×

4

×
×

4

×

4

64 K

×

64 K × 4
64 K × 4

4

4

Number of

Words

32 K

16 K

8 K

64 K

32 K

16 K

128 K

0101 4 12 or 16

0101 4 20 or 24

0101 8 8

0101 8 12 or 16

4-14 DSP56009 User’s Manual MOTOROLA

256 K ×
256 K ×

2 ×

256 K × 4

2 ×

256 K × 4

4
4

64 K

32 K

256 K

128 K

External Memory Interface

EMI Programming Model

Table 4-7 EMI Maximum DRAM Size (Relative Addressing) (Continued)

EAM[3:0] Bus Width Word Length DRAM devices

0101 8 20 or 24

0110 4 8

0110 4 12 or 16

0110 4 20 or 24

0110 8 8

0110 8 12 or 16

0110 8 20 or 24
0111 4 8 4 M × 4 2 M

0111 4 12 or 16 4 M × 41 M
0111 4 20 or 24 4 M × 4 512 K
0111 8 8 2 × 4 M × 44 M
0111 8 12 or 16 2 × 4 M × 42 M
0111 8 20 or 24 2 × 4 M × 41 M

256 K × 4

2 ×

1 M ×
1 M ×
1 M ×

2 ×

1 M × 4

2 ×

1 M × 4

2 ×

1 M × 4

4
4
4

Number of

Words

64 K

512 K

256 K

128 K

1 M

512 K

256 K

Table 4-8 EMI Maximum DRAM Size (Absolute Addressing)

EAM[3:0] Bus Width Word Length DRAM devices

1100 4 8 64 K × 4 32 K
1100 4 12 64 K × 4 21,845
1100 4 16 64 K × 4 16 K
1100 4 20 64 K × 4 13,107
1100 4 24 64 K × 4 10,922
1100 8 8 2 × 64 K × 4 64 K
1100 8 12 or 16 2 × 64 K × 4 32 K
1100 8 20 or 24 2 × 64 K × 4 21,845
1101 4 8 256 K × 4 128 K
1101 4 12 256 K × 4 87,381
1101 4 16 256 K × 4 64 K
1101 4 20 256 K × 4 52,428

Number of

Words

MOTOROLA DSP56009 User’s Manual 4-15

External Memory Interface
EMI Programming Model

Table 4-8 EMI Maximum DRAM Size (Absolute Addressing) (Continued)

EAM[3:0] Bus Width Word Length DRAM devices

1101 4 24 256 K × 4 43,690
1101 8 8 2 × 256 K × 4 256 K
1101 8 12 or 16 2 × 256 K × 4 128 K
1101 8 20 or 24 2 × 256 K × 4 87,381
1110 4 8 1 M × 4 512 K
1110 4 12 1 M × 4 349,525
1110 4 16 1 M × 4 256 K
1110 4 20 1 M × 4 209,715
1110 4 24 1 M × 4 174,762
1110 8 8 2 × 1 M × 41 M
1110 8 12 or 16 2 × 1 M × 4 512 K
1110 8 20 or 24 2 × 1 M × 4 349,525
1111 4 8 4 M × 42 M
1111 4 12 4 M × 4 1,398,101

Number of

Words

1111 4 16 4 M × 41 M
1111 4 20 4 M × 4 838,860
1111 4 24 4 M × 4 699,050
1111 8 8 2 × 4 M × 44 M
1111 8 12 or 16 2 × 4 M × 42 M
1111 8 20 or 24 2 × 4 M × 4 1,398,101

4.2.7.4 EMI Increment EBAR After Read (EINR)—Bit 7

The read/write control bit EMI Increment EBAR after Read (EINR) enables the
function of incrementing the contents of the relevant EBARx after a read operation. If
EINR is cleared, EBARx will not be modified after read operations. If EINR is set, the
contents of EBARx will be incremented by one after generating the address for the
read operation. This bit affects all operating modes.

Note: EINR is cleared by hardware reset and software reset.

4.2.7.5 EMI Increment EBAR After Write (EINW)—Bit 8

The read/write control bit EMI Increment EBAR after Write (EINW) enables the
function of incrementing the contents of the relevant EBARx after a write operation.

4-16 DSP56009 User’s Manual MOTOROLA