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CDM

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and PRO SERIES

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Mobile Radios

Detailed Service Manual

Professional Radio

contact

control

PRO7100

As Dedicated As You Are

Computer Software Copyrights

The Motorola products described in this manual may include copyrighted Motorola computer programs stored in semiconductor memories or other media. Laws in the United States and other countries preserve for Motorola certain exclusive rights for copyrighted computer programs, including the exclusive right to copy or reproduce in any form, the copyrighted computer program. Accordingly, any copyrighted Motorola computer programs contained in the Motorola products described in this manual may not be copied or reproduced in any manner without the express written permission of Motorola. Furthermore, the purchase of Motorola products shall not be deemed to grant, either directly or by implication, estoppel or otherwise, any license under the copyrights, patents or patent applications of Motorola, except for the normal non-exclusive royalty-free license to use that arises by operation of law in the sale of a product.

SAFETY INFORMATION

Important information on safe and efficient operation is included in this manual. Read this information before using your ra dio.

SAFE AND EFFICIENT OPERATION OF MOTOROLA TWO-WAY RADIOS

This document provid es information and instruction s f or the sa fe and efficient ope ratio n of Motoro la Portable and Mobile Two-Way Radios.

The information provided in this document supercedes the general safety information contained in user guides published prior to 1st. January 1998.

For inf ormation re garding r adio use in haz ardou s areas , p lease ref e r to t he Factory Mutual (FM) appro v a l man ual supplement or Instruction Card which is included with radio models that offer this capability.

EXPOSURE TO RADIO FREQUENCY ENERGY

Your Motorola Two-Way Radio, which generates and radiates radio frequency (RF) electromagnetic energy (EME) is designed to comply with the following National and International Standards and Guidelines regarding exposure of human beings to radio frequency electromagnetic energy:

l Federal Communications Commission Report and Order No. FCC 96-326 (August 1996) l American National Standards Institute (C95.1 - 1992) l National Council on Radiation Protection and Measurements (NCRP-1986) l International Commission on Non-Ionizing Radiation Protection (ICNRP- 1986) l European Committee for Electrotechnical Standardisation (CENELEC):

Safety-1

ENV 50166-1 1995 E Human exposure to electromagnetic fields Low

frequency (0 Hz to 10 kHz)

ENV 50166-2 1995 E Human exposure to electromagnetic fields High

frequency (10 kHz to 300 GHz)

Proceedings of SC211/B 1996 “Safety Conside r ations for Human Exposure to EMFs fro m

Mobile Telecommunication Equipment (MTE) in the Frequency Range 30MHz - 6 GHz.” (EMF - Electro-Magnetic Fields)

To assure optimal radio per fo rmance and to en sure that you r e xposure to ra dio freque ncy electro magnetic energ y is within the guidelines in the above standards, always adhere to the following procedures:

PORTABLE RADIO OPERATION AND EME EXPOSURE

l When transmitting with a portable radio, hold radio in a vertical position with the

microphone 2.5 to 5 centimeters (one or two inches) away from the mouth. Keep antenna at least 2.5 centimeters (one inch) from your head or body when transmitting.

l If you wear a portable Two-Way radio on your body, ensure that the antenna is at

least 2.5 centimeters (one inch) from the body when transmitting.

ELECTROMAGNETIC INTERFERENCE/COMPATIBILITY

NOTE

Nearly every electronic device is susceptible to electromagnetic interference (EMI) if inadequately shielded, designed or otherwise configured for electromagnetic compatibility

MAN WITH RADIO

l To avoid electromagnetic interference and/or compatibility conflicts, turn off your radio in any fa cility where

posted notices instruct you to do so. Hospital or health facilities may be using equipment that is sensitive to external RF energy.

l When instructed to do so, turn off your radio when on board an aircraft. Any use of a radio must be in accor-

dance with airline regulations or crew instructions.

Safety-2

OPERATIONAL WARNINGS

Vehicles with an air bag

l Do not place a portable ra dio in t he area o ver an air bag or in the a ir bag de ployment area. Air b ags inf late w ith

great force. If a portable radio is placed in the air bag deployment area and the air bag inflates, the radio may be propelled with great force and cause serious injury to occupants of vehicle.

W A R N I N G

Potentially explosive atmospheres

l Turn off your Two-Way radio when you are in any area with a potentially explosive atmosphere, unless it is a

radio type especially qualified for use in such areas (e.g. FM or Cenelec approved). Sparks in a potentially explosive atmosphere can cause an explosion or fire resulting in bodily injury or even death.

Batteries

l Do not replace or recharge batteries in a potentially explosive atmosphere. Contact sparking may occur while

installing or removing batteries and cause an explosion.

Blasting caps and areas

l To avoid possible interf ere nc e wi th blasting oper ati on s , tu rn off your radio whe n you are near electrical blas tin g

caps. In a “

NOTE

blasting area

The areas with potentially explosive atmospheres referred to above include fuelling areas such as: below decks on boats; fuel or chemical transfer or storage facilities; areas where the air contains chemicals or particles, such as grain, dust or metal powders; and any other area where you would normally be advised to turn off your vehicle engine. Areas with potentially explosive atmospheres are often but not always posted.

” or in areas posted “

turn off two-way radio

”, obey all signs and instructions.

OPERATIONAL CAUTIONS

Damaged antennas

l Do not use any portable Two-Way radio that has a damaged antenna. If a damaged antenna comes into con-

tact with your skin, a minor burn can result.

C a u t i o n

Batteries

l All batteries can cause property damage and/or bodily injury such as burns if a conductive material such as

jewelery, keys or beaded chains touch exposed terminals. The conductive material may complete an electrical circuit (short circuit) and become quite hot. Exercise care in handling any charged battery, particularly when placing it inside a pocket, purse or other container with metal objects.

INTRINSICALLY SAFE RADIO INFORMATION

FMRC Approved Equipm en t

Anyone intending to use a radio in a location where hazardous concentrations of flammable material exist (hazardous atmosphere) is advised to become familiar with the subject of intrinsic safety and with the National Electric Code NFPA 70 (National Fire Protection Association) Article 500 (hazardous [classified] locations).

An Approval Guide, issued by Factory Mutual Research Corporation (FMRC), lists manufacturers and the products approved by FMRC for use in such locations. FMRC has also issued a voluntary approval standard for repair service (“Class Number 3605”).

FMRC Approval labels are attached to the radio to identify the unit as being FM Approved for specified hazardous atmospheres. This label specifies the hazardous Class/Division/Group along with the part number of the battery that must be used. Depending on the design of the portable unit,

this FM label can be found on the back of the radio housing or the bottom of the radio housing.Their Approval mark is shown below.

WARNING: Do not operate radio communications equipment in a hazardous atmosphere unless it is a type especially qualified (e.g. FMRC Approved) for such use. An explosion or

W A R N I N G

fire may result. WARNING: Do not operate the FMRC Appr oved Product in a hazardous atmosphere if it has

been physically damaged (e.g. cracked housing). An explosion or fire may result. WARNING: Do not replace or charge batteries in a hazardous at mosphere. Contact sparking

may occur while installing or removing batteries and cause an ex plosion or fire. WARNING: Do not replace or change accessories in a hazardous atmosphere. Contact

sparking may occur while installing or removing accessories and cause an explosion or fire. WARNING: Do not operate the FMRC Approved Product unit in a hazardous location with the

accessory contacts exposed. Keep the connector cover in place when accessories are not used.

WARNING: Turn radio off before removing or installing a battery or accessory.

Safety-3

APPROVED

WARNING: Do not disassemble the FMRC Approved Product unit in any way that exposes the internal electrical circuits of the unit.

Radios must ship from the Motorola manufacturing facility with the hazardous atmosphere capability and FM Approval labeling. Radios will not be “upgraded” to this capability and labeled in the field.

A modification changes the unit’s hardware from its original design configuration. Modifications can only be done by the original product manufacturer at one of its FMRC audited manufacturing facilities.

WARNING: Failure to use an FMRC Approved Product unit with an FMRC Approved battery or FMRC Approved accessories specifically approved for that product may result in the dan-

W A R N I N G

gerously unsafe condition of an unapproved radio combination being used in a hazardous location.

Unauthorized or incorrect modification of an FMRC Approved Product unit will negate the Approval rating of the product.

Repair of FMRC Approved Products

REPAIRS FOR MO T OROLA FMRC APPR O VED PR ODUCTS ARE THE RESPONSIBILITY OF THE USER.

You should not repair or relabel any Motorola manufactured communication equipment bearing the FMRC Approval label (“FMRC Approved Product”) unless you are familiar with the current FMRC Approval standard for repairs and service (“Class Number 3605).

You may want to consider using a repair facility that operates under 3605 repair service approval.

WARNING: Incorrect repair or relabeling of any FMRC Approved Product unit could adversely affect the Approval rating of the unit.

W A R N I N G

WARNING: Use of a radio that is not intrinsically safe in a hazardous atmosphere could result in serious injury or death.

Safety-4

FMRC’s Approval Standard Class Number 3605 is subject to change at any time without notice to you, so you may want to obtain a current copy of 3605 from FMRC. Per the December, 1994 publication of 3605, some key definitions and service requirements are as follows:

Repair

A repair constitutes something done internally to the unit that would bring it back to its original condition Approved by FMRC. A repair should be done in an FMRC Approved facility.

Items not considered as repairs are those in which an action is performed on a unit which does not require the outer casing of the unit to be opened in a manner which exposes the internal electrical circuits of the unit. You do not have to be an FMRC Approved Repair Facility to perform these actions.

Relabeling

The repair facility shall have a method by which the replacement of FMRC Approval labels are controlled to ensure that any relabeling is limited to units that were originally shipped from the Manufacturer with an FM Approval label in place. FMRC Approval labels shall not be stocked by the repair facility. An FMRC Approval label shall be ordered from the original manufacturer as needed to repair a specific unit. Replacement labels may be obtained and applied by the repair facility providing satisfactory evidence that the unit being relabeled was originally an FMRC Approved unit. V erification may include, but is not limited to: a unit with a damaged Approval label, a unit with a defective housing displaying an Approval label, or a customer invoice indicating the serial number of the unit and purchase of an FMRC Approved model.

Do Not Substitute Options or Accessories

The Motorola communications equipment certified by Factory Mutual is tested as a system and consists of the FM Approved portable, FM Approved battery, and FM Approved accessories or options, or both. This Approved portable and battery combination must be strictly observed. There must be no substitution of items, even if the substitute has been previously Approved with a different Motorola communications equipment unit. Approved configurations are listed in the FM Approval guide published by FMRC, or in the product FM Supplement. This FM Supplement is shipped with FM Approved radio and battery combination from the manufacturer. The Approval guide, or the Approval standard Class Number 3605 document for repairs and service, can be ordered directly through Factory Mutual Research Corporation located in Norwood, Massachusetts.

Chapter 1

1.1 Scope of Manual ................... ....... ...... ....... ...... ....... ...... ...... ....... ...... ....... ...... ................................. 1-1

1.2 Warranty and Service Support ......................................................................................................1-1

1.2.1 Warranty Period .....................................................................................................................1-1

1.2.2 Return Instructions .................................................................................................................1-1

1.2.3 After Warranty Period ............................................................................................................ 1-1

1.3 Related Documents ........................... ....... ...... ....... ...... ...... ....... ...... ....... ...... ................................. 1-2

1.4 Technical Support .........................................................................................................................1-2

1.5 Warranty and Repairs.................................................................................................................... 1-2

1.6 Radio Model Chart and Specifications ..........................................................................................1-4

1.7 Radio Model Information ...............................................................................................................1-4

Chapter 2

2.1 Overview....................................................................................................................................... 2-1

2.2 Controller Section .........................................................................................................................2-1

2.2.1 Radio Power Distribution ....... ...... ....... ...... ....... ...... ...... ....... ...... ............................................. 2-2

2.2.2 Automatic On/Off ................................................................................................................... 2-3

2.2.3 Emergency............................................................................................................................. 2-4

2.2.4 Mechanical On/Off ................................................................................................................. 2-4

2.2.5 Ignition ................................................................................................................................... 2-4

2.2.6 Microprocessor Clock Synthesizer......................................................................................... 2-5

2.2.7 Serial Peripheral Interface (SPI)............................................................................................ 2-5

2.2.8 SBEP Serial Interface ............................................................................................................ 2-6

2.2.9 General Purpose Input/Output............................................................................................... 2-6

2.2.10 Normal Microprocessor Operation......................................................................................... 2-7

2.2.11 Static Random Access Memory (SRAM)............................................................................... 2-8

2.3 Controller Board Audio and Signalling Circuits ............................................................................. 2-8

2.3.1 Audio Signalling Filter IC with Compander (ASFIC CMP) ..................................................... 2-8

2.3.2 Transmit Audio Circuits.......................................................................................................... 2-9

2.3.3 Microphone Input Path ...........................................................................................................2-9

2.3.3.1 PTT Sensing and TX Audio Processing ........................................................................ 2-10

2.3.3.2 TX Secure Audio (optional) ........................................................................................... 2-10

2.3.3.3 Option Board Transmit Audio ........................................................................................2-10

2.3.4 Transmit Signalling Circuits ................................................................................................. 2-11

2.3.4.1 Sub-Audible Data (PL/DPL) ................................. ....... ...... ....... ..................................... 2-11

2.3.4.2 High Speed Data ...........................................................................................................2-12

2.3.4.3 Dual Tone Multiple Frequency (DTMF) Data ................................................................ 2-12

2.3.5 Receive Audio Circuits......................................................................................................... 2-13

2.3.5.1 Squelch Detect ..............................................................................................................2-13

2.3.5.2 Audio Processing and Digital Volume Control ............................................................... 2-14

2.3.5.3 Audio Amplification Speaker (+) Speaker (-) .................................................................2-14

2.3.5.4 Handset Audio ............................................................................................................... 2-15

2.3.5.5 Filtered Audio and Flat Audio ........................................................................................ 2-15

2.3.5.6 RX Secure Audio (Optional) .......................................................................................... 2-15

Introduction

Theory of Operation

2.3.5.7 Option Board Receive Audio 2-15

2.3.6 Receive Signalling Circuits................................................................................................... 2-16

2.3.6.1 Sub-audible Data (PL/DPL) and High Speed Data Decoder ........................................2-16

2.3.6.2 Alert Tone Circuits.........................................................................................................2-16

2.3.6.3 Voice Storage (Optional) ..............................................................................................2-17

2.4 UHF (403-470 MHz) Receiver Front-End ...................................................................................2-17

2.4.1 Front-End Band-Pass Filters & Pre-Amplifier....................................................................... 2-19

2.4.2 First Mixer and 1st Intermediate Frequency (IF)...................................................................2-19

2.4.3 2nd Intermediate Frequency (IF) and Receiver Back-End................................................... 2-19

2.5 Transmitter Power Amplifier (PA) 40 W ......................................................................................2-20

2.5.1 Power Controlled Stage ....................................................................................................... 2-20

2.5.2 Pre-Driver Stage .................................................................................................................. 2-20

2.5.3 Driver Stage......................................................................................................................... 2-21

2.5.4 Final Stage.............................................. ...... ....... ...... ...... ....... ............................................. 2-21

2.5.5 Bi-Directional Coupler .......................................................................................................... 2-21

2.5.6 Antenna Switch.................................................................................................................... 2-21

2.5.7 Harmonic Filter......................................................................................................................2-21

2.5.8 Power Control .......................................................................................................................2-21

2.6 Frequency Synthesis ..................................................................................................................2-22

2.6.1 Reference Oscillator............................................................................................................. 2-22

2.6.2 Fractional-N Synthesizer.................. ....... ............................................. ...... ....... ...... ....... ...... 2-22

2.6.3 Voltage Controlled Oscillator (VCO) .................................................................................... 2-23

2.6.4 Synthesizer Operation.......................................................................................................... 2-25

2.7 VHF (136-174MHz) Receiver Front-End .....................................................................................2-26

2.7.1 Front-End Band-Pass Filters and Pre-Amplifier................................................................... 2-27

2.7.2 First Mixer and 1st Intermediate Frequency (IF).................................................................. 2-27

2.7.3 2nd Intermediate Frequency (IF) and Receiver Back-End................................................... 2-27

2.8 Transmitter Power Amplifier (PA) 45 W ......................................................................................2-28

2.8.1 Power Controlled Stage ....................................................................................................... 2-28

2.8.2 Pre-Driver Stage .................................................................................................................. 2-28

2.8.3 Driver Stage......................................................................................................................... 2-29

2.8.4 Final Stage.............................................. ...... ....... ...... ...... ....... ............................................. 2-29

2.8.5 Directional Coupler............................................................................................................... 2-29

2.8.6 Antenna Switch.................................................................................................................... 2-29

2.8.7 Harmonic Filter..................................................................................................................... 2-29

2.8.8 Power Control ...................................................................................................................... 2-30

2.9 Frequency Synthesis ..................................................................................................................2-30

2.9.1 Reference Oscillator............................................................................................................. 2-30

2.9.2 Fractional-N Synthesizer.................. ....... ............................................. ...... ....... ...... ....... ...... 2-30

2.9.3 Voltage Controlled Oscillator (VCO) .................................................................................... 2-32

2.9.4 Synthesizer Operation.......................................................................................................... 2-33

2.10 Control Head (PRO3100, CDM750) ...........................................................................................2-34

2.10.1 Power Supplies .................................................................................................................... 2-34

2.10.2 Power On/Off ....................................................................................................................... 2-34

2.10.3 Microprocessor Circuit ......................................................................................................... 2-34

2.10.4 SBEP Serial Interface .......................................................................................................... 2-35

2.10.5 Keypad Keys.... ...... ....... ...... ....... ...... ....... ............................................. ...... ....... ...... ............. 2-35

2.10.6 Status LED and Back Light Circuit....................................................................................... 2-35

2.10.7 Microphone Connector Signals............................................................................................ 2-36

2.10.8 Speaker.................................................................................................................................2-36

2.10.9 Electrostatic Transient Protection ........................................................................................ 2-36

2.11 Control Head (PRO5100, PRO7100, CDM1250, CDM1550) .....................................................2-37

2.11.1 Power Supplies .................................................................................................................... 2-37

2.11.2 Power On / Off ..................................................................................................................... 2-37

2.11.3 Microprocessor Circuit ......................................................................................................... 2-37

2.11.4 SBEP Serial Interface .......................................................................................................... 2-38

2.11.5 Keypad Keys........................................................................................................................ 2-38

2.11.6 Status LED and Back Light Circuit....................................................................................... 2-38

2.11.7 Liquid Crystal Display (LCD)................................................................................................ 2-39

2.11.8 Microphone Connector Signals............................................................................................ 2-39

2.11.9 Speaker................................................................................................................................ 2-40

2.11.10 Elec tros tati c Transien t Prot ectio n .......................... ...... ....... ...... ....... ...... ....... ...... ....... ...... .. .. 2-40

Chapter 3 Maintenance

3.1 Introduction .............. ....................................................................... ..............................................3-1

3.2 Preventive Maintenance ...............................................................................................................3-1

3.2.1 Inspection............................................................................................................................... 3-1

3.2.2 Cleaning................................................................................................................................. 3-1

3.3 Safe Handling of CMOS and LDMOS ........................................................................................... 3-2

3.4 General Repair Procedures and Techniques ............................................................................... 3-2

3.5 Recommended Test Tools ............................................................................................................ 3-5

3.6 Transmitter Troubleshootin g Chart............ ............................................. ...... ....... ...... ....... ...... ....... 3-6

3.7 Receiver Troubleshooting Charts .................................................................................................3-7

3.8 Synthesizer Troubleshooting Chart s .. ............................................. ....... ...... ....... ...... ....... ...... ....... 3-9

3.9 VCO Troubleshooting Charts....................................................................................................... 3-11

iii

Chapter 4

4.1 Introduction .............. ....................................................................... ..............................................4-1

4.1.1 Notes For All Schematics and Circuit Boards........................................................................ 4-1

Schematic Diagrams, Overlays, and Parts Lists

List of Figures

2-1 Controller Block Diagram...............................................................................................................2-1

2-2 DC Power Distribution Block Diagram........................................................................................... 2-3

2-3 Transmit Audio Paths ....................................................................................................................2-9

2-4 Transmit Signalling Paths............................................................................................................2-11

2-5 Receive Audio Paths ...................................................................................................................2-13

2-6 Receive Signalling Paths.............................................................................................................2-16

2-7 UHF Receiver Block Diagram...................................................................................................... 2-18

2-8 UHF Transmitter Block Diagram..................................................................................................2-20

2-9 UHF Synthesizer Block Diagram ................................................................................................. 2-23

2-10 UHF VCO Block Diagram ............................................................................................................2-24

2-11 VHF Receiver Block Diagram...................................................................................................... 2-26

2-12 VHF Transmitter Block Diagram.................................................................................................. 2-28

2-13 VHF Synthesizer Block Diagram .................................................................................................2-31

2-14 VHF VCO Block Diagram ............................................................................................................2-32

4-1 PRO3100/CDM750 Control Head Top Overlay ............................................................................ 4-3

4-2 PRO3100/CDM750 Control Head Bottom Overlay ....................................................................... 4-4

4-3 PRO3100CDM750 Control Head Schem atic Dia gram, She et 1 ...................................... ...... ....... 4-5

4-4 PRO3100CDM750 Control Head Schem atic Dia gram, She et 2 ...................................... ...... ....... 4-6

4-5 PRO5100/PRO7100/CDM1250/CDM1550 Control Head Top

Overlay ......................... ............. ............. ............. ............. ...... ............. ............. ............. ....... .........4-9

4-6 PRO5100/PRO7100/CDM1250/CDM1550 Control Head Bottom

Overlay ......................... ............. ............. ............. ............. ...... ............. ............. ............. ....... .......4-10

4-7 PRO5100/PRO7100/CDM1250/CDM1550 Control Head

Schematic Diagram .....................................................................................................................4-11

4-8 PRO5100/PRO7100/CDM1250/CDM1550 Control Head Keypad

Schematic Diagram..................................................................................................................... 4-12

4-9 PRO5100/PRO7100/CDM1250/CDM1550 Control Head LCD

Schematic ................................................................................................................................... 4-13

4-10 PRO5100/PRO7100/CDM1250/CDM1550 Control Head Display

Schematic ................................................................................................................................... 4-14

4-11 Complete Controller Schematic Diagram ....................................................................................4-17

4-12 Controller Control Schematic Diagram ......................................................................................4-18

4-13 Controller I/O Schematic Diagram ..............................................................................................4-19

4-14 Controller Audio Schematic Diagram ..........................................................................................4-20

4-15 Controller Supply Voltage Schematic Diagram ...........................................................................4-21

4-16 UHF (403-470MHz) Voltage Controlled Oscillator Schematic Diagram ......................................4-25

4-17 UHF (403-470MHz) Fractal-N Schematic Diagram ....................................................................4-26

4-18 UHF (403-470MHz) Power Amplifier Schematic Diagram ..........................................................4-27

4-19 VHF (136-174MHz) Main Board Top Side PCB ..........................................................................4-33

4-20 VHF (136-174MHz) Receiver Front End Schematic Diagram ....................................................4-34

4-21 VHF (136-174MHz) Receiver IF Schematic Diag ram ............ ....... ...... ....... ...... ....... ...... ....... ...... .4-35

4-22 VHF (136-174MHz) Fractal-N Schematic Diagram .....................................................................4-36

4-23 VHF (136-174MHz) Voltage Controlled Oscillator Schematic Diagram ......................................4-37

4-24 VHF (136-174MHz) Power Amplifier Schematic Diagram ..........................................................4-38

List of Tables

1-1 Radio Model Number.....................................................................................................................1-3

3-1 Recommended Test tools..............................................................................................................3-5

4-1 PRO3100/CDM750 Control Head Parts List..................................................................................4-7

4-2 PRO5100/PRO7100/CDM1250/CDM1550 Control Head Parts List............................................4-15

4-3 Controller Parts List ....................................... ...... ....... ...... ...... .............................................. ...... .4-22

4-4 UHF B1 Radio Parts List..............................................................................................................4-28

4-5 VHF (136-174MHz) Radio Parts List ...........................................................................................4-39

Chapter 1 Introduction

1.1 Scope of Manual

This manual is intended for use by service technicians familiar with similar types of equipment. It contains service information required for the equipment described and is current as of the printing date. Changes that occur after the printing date are incorporated by a complete manual revision or alternatively , as additions.

1-1

NOTE

Before operating or testing these units, please read the Safety Information Section in the front of this manual.

1.2 Warranty and Service Support

Motorola offers long term support for its products. This support includes full exchange and/or repair of the product during the warranty period, and service/repair or spare parts support out of warranty . Any “return for exchange” or “return for repair” by an authorized Motorola dealer must be accompanied by a warranty claim form. Warranty claim forms are obtained by contacting customer service.

1.2.1 Warranty Period

The terms and conditions of warranty are defined fully in the Motorola dealer or distributor or reseller contract. These conditions may change from time to time and the following notes are for guidance purposes only.

1.2.2 Return In structions

In instances where the product is covered under a “return for replacement” or “return for repair” warranty, a check of the product should be performed prior to shipping the unit back to Motorola. This is to ensure that the product has been correctly programmed or has not been subjected to damage outside the terms of the warranty.

Prior to shipping any radio back to a Motorola warranty depot, please contact the appropriate customer service for instructions. All returns must be accompanied by a warranty claim form, available from your customer services representative. Products should be shipped back in the original packaging, or correctly packaged to ensure no damage occurs in transit.

1.2.3 After Warranty Period

After the Warranty period, Motorola continues to support its products in two ways: Firstly, Motorola's Accessories and Aftermarket Division (ADD) offers a repair service to both end

users and dealers at competitive prices. Secondly, Motorola’s service department supplies individual parts and modules that can be

purchased by dealers who are technically capable of performing fault analysis and repair.

1-2 Related Documents

1.3 Related Documents

The following documents are directly related to the use and maintainability of this product.

Title Part Number

Service Manual, Basic, Engl 68P81091C62 Service Manual, Basic, Engl 68P81092C71 Service Manual, Basic, Port 68P81092C73 Service Manual, Basic,Span 68P81092C72 Service Manual, Detailed, Engl 68P81091C63 Service Manual, Detailed, Port 68P81092C76 Service Manual, Detailed, Span 68P81092C75

1.4 Technical Support

Technical support is available to assist the dealer/distributor and self-maintained customers in resolving any malfunction which may be encountered. Initial contact should be by telephone to customer resources wherever possible. When contacting Motorola technical support, be prepared to provide the product model number and the unit’s serial number. The contact locations and telephone numbers are listed below.

United States and Puerto Rico: 1-800-694-2161, Options 1, 3 Brasil: 000-811-682-0550 Colombia: 980-12-0451 Mexico: 001-800-694-2161 From other countries: (954)723-3008

1.5 W arranty and Repairs

For warranty and repairs, contact Motorola Technical Support as listed below. Be prepared to provide the product

Some replacement parts, spare parts, and/or product information can be ordered directly. If a complete Motorola part number is assigned to the part, and it is not identified as “Depot ONLY”, the part is available from Motorola Accessories and Aftermarket Division (AAD). If no part number is assigned, the part is not normally available from Motorola. If the part number is appended with an asterisk, the part is serviceable by a Motorola depot only. If a parts list is not included, this generally means that no user-serviceable parts are available for that kit or assembly.Technical Support the product

model number

and the unit’s

serial number

Warranty and Repairs 1-3

Parts Order Entry

7:00 A. M. to 7:00 P. M. (Central Standard Time) Monday through Friday (Chicago, U. S. A.)

To Order Parts in the United States of America:

1-800-422-4210, or 847-538-8023 1-800-826-1913, or 410-712-6200 (U. S. Federal Government) TELEX: 280127 FAX: 1-847-538-8198 FAX: 1-410-712-4991 (U. S. Federal Government) (U. S. A.) after hours or weekends: 1-800-925-4357

Colombia

Motorola de Colombia Diagonal 127A 17-64 Santa Fe de Bogota Columbia Telefono: 1-615-5759

Puerto Rico

Motorola de Puerto Rico A BE. Chardon, Edificio Telemundo 2 Hato Rey, PR 00918 Telefono: (787)641-4100 Fax: (787)782-3685

To Order Parts in Latin America and the Caribbean:

1-847-538-8023 Motorola P arts Accessories and Aftermarket Division (United States and Canada) Attention: Order Processing 1313 E. Algonquin Road Schaumburg, IL 60196 Accessories and Aftermarket Division Attention: Latin America and Caribbean

Order Processing

1313 E. Algonquin Road Schaumburg, IL 60196

Parts Identification

1-847-538-0021 (Voice) 1-847-538-8194 (FAX)

Brazil

Motorola Do Brasil Rua Bandeira Paulista, 580 Phone: (11)821-9991 Fax: (11)8 28- 0157

Mexico

Motorola De Mexico Blvd. Manuel Avila Camacho #32, Primer Piso COL. Lomas de Chapultepec Mexico D.F. 06700 CP 11000 Mexico Phone: (5)387-0501 Fax: (5)387-0 554

1-4 Radio Model Chart and Specifications

1.6 Radio Model Chart and Specifications

The radio model charts and specifications are located in the Basic Service Manual listed under the Related Documents paragraph of this chapter.

1.7 Radio Model Information

The model number and serial number are located on a label attached to the back of your radio. You can determine the RF output power, frequency band, protocols, and physical packages from these numbers. The example below shows one portable radio model number and its specific characteristics.

Table 1-1. Radio Model Number

Example:

AAM25RHC9AA1AN

Ty pe of

Unit

Model Series

M25 K

= Mobile

Motorola Internal Use

Freq. Band

VHF

(136-

174MHz)

UHF1

(403-

470MHz)

UHF2

(450-

512MHz)

Low

Band, R1

(29.7-

36.0MHz)

Power

Level

1-25WANo Display ,

25-40WCNo Display

Physical

Packages

No Keypad

Basic Key-

pad

1-Line Dis -

play, Lim-

ited Keypad

1-Line Dis -

play, Stan-

dard

Keypad

Channel Spacing

Program-

mable

Protocol

Conventional

LTR

Feature

Level

64F

128F

160F

Model

Revisi on

Model

Package

Low

Band, R2

(36.0-

42.0MHz)

Low

Band, R3

(42.0-

50.0MHz)

4-Line Dis -

play,

Enhanced

Keypad

Chapter 2 Theory of Operation

2.1 Overview

This chapter provides a detailed theory of operation for the radio and its components. The radio is designed as a single board unit consisting of a transmitter, receiver , and controller circuits. The board also accepts one additional option board that can provide functions such as secure voice/data, voice storage, or a signalling decoder.

A control head mounted directly on the front of the radio or remotely connected by an extension cable provides a user interface for controlling the various features of the radio.The control head contains, LED indicators, microphone connector, and buttons depending on the radio type, display, and speaker.

If a control head is not mounted directly on the front of the radio, an expansion board containing circuits for special applications can be mounted in its place on the front of the radio. An additional control head may be connected using an extension cable.

The rear of the radio provides connections for a power, antenna, and accessory cable. The accessory cable provides connections for items such as an external speaker, emergency switch, foot operated PTT, and ignition sensing, etc.

2-1

2.2 Controller

The radio controller, shown in Figure 2-1, is divided into three main functions:

Digital control

Audio processing

Voltage regulation.

The digital control section of the radio consists of a microprocessor (µP), support memory, support logic, signal MUX ICs, on/off circuit, and general purpose input/output circuits.

To Synthesizer

16.8 MHz Reference Clock from Synthesizer

Recovered Audio

5V from Synthesizer Section (5V_RF)

To RF Se ction

Digital

Mod

5V Regulator (5VD)

Out

ASFIC_CMP

SPI

RAM

EEPROM

FLASH

Audio/Signalling

Audio PA

µP Clock

HC11FL0

External Microphone

External Speaker

Internal

Speaker

SCI to Accessory & Control Head Connector

Figure 2-1. Controller Block Diagram

2-2 Theory of Operation

2.2.1 Radio Power Distribution

The dc power distribution throughout the radio board is shown in Figure 2-2. Voltage regulation for the controller is provided by four separate devices:

U0651 (MC78M05) +5 volts

U0641 (LM2941) +9.3 volts

U0611 (LM2941) +12 volts

VSTBY 5V (a combination of R0621 and VR0621)

Additional 5 volt regulator located in the RF section.

The dc voltage applied to connector J0601 supplies power directly to the following:

Electronic on/off control

RF power amplifier

12 volt regulator

9.3 volt regulator

Audio PA

5.6 volt stabilization circuit

9.3 volt regulator (U0641) supplies power to the 5 volt regulator (U0651) and 6 volt voltage divider Q0681

Regulator U0641 generates the 9.3 volts required by some audio circuits, the RF and power control circuits. Input and output capacitors C0641 and C0644 / C0645 are used to reduce high frequency noise. Resistors R0642 / R0643 set the output voltage of the regulator. If the voltage at pin 1 is greater than 1.3 volts the regulator output decreases and if the voltage is less than 1.3 volts the regulator output increases. This regulator output is enabled by a 0 volt signal on pin 2. Transistors Q0661, Q0641, and R0641 are used to disable the regulator when the radio is turned off.

Voltage regulator U0651 provides 5 volts operating voltage for the digital circuits. Operating voltage is from the regulated 9.3volts supply. Input and output capacitors (C0651 / C0652 and C0654 / C0655) reduce high frequency noise and provide proper operation during battery transients. Voltage sense device U0652 or alternatively U0653 provides a reset output that goes to 0 volts if the regulator output goes below 4.5 volts. This resets the controller to prevent improper operation. Diode D0651 prevents discharge of C0652 by negative spikes on the 9.3 volt supply.

Transistor Q0681 and resistors R0681 / R0682 divide the regulated 9.3 volts down to about 6 volts. This voltage supplies the 5 volt regulator, located on the RF section. By reducing the supply voltage of the regulator, the power dissipation is divided between the RF section and the controller section.

The VSTBY signal, derived directly from the supply voltage by components R0621 and VR0621, buffers the internal RAM. Capacitor C0622 allows the battery voltage to be disconnected for several seconds without losing RAM information. Dual diode D0621 prevents radio circuits from discharging this capacitor. When the supply voltage is applied to the radio, C0622 is charged via R0621 and D0621. When the radio is switched on, the µP enters the wrong mode if the voltage across C0622 is still too low. The regulated 5 volts charges C0622 via diode D0621.

Theory of Operation 2-3

J0601

13.2V

PASUPVLT G

FLT_A+

PA, Driver

Antenna Switch

12V

Regulator

ON / OFF

Control

9.3V

Regulator

Audio PA

5.6V

20 Pin Connector

SWB+

Ignition Emergency ON/OFF

TX Amp

Te mp S e n se

RX RF Amp

IF Amp

Accessories

9V3

PCIC,

VSTBY

Control Head

12 Pin Connector

FLT_A+

5VD

Regulator

5VD

MCU

µP, R A M ,

FLASH & EEPROM

Option Board

40 Pin Connector

Regulator

ASFIC_CMP

5V_RF

FRACTN VCOBIC

5V/ VDDA

Figure 2-2. DC Power Distribution Block Diagram

The INT SW B+ voltage from switching transistor Q0661 provides power to the circuit controlling the audio PA output. The voltage is monitored by the µP through voltage divider R0671/R0672 and the line battery voltage. Diode VR0671 limits the divided voltage to 5.6 volts to protect the µP.

Regulator U0611 generates the voltage for the switched supply voltage output (SWB+) at accessory connector J0501, pin 13. U0611 operates as a switch with voltage and current limit. Resistors R0611/R0612 set the maximum output voltage to 16.5 volts. This limitation is only active at high supply voltage levels. The regulator output is enabled by a 0 volt signal at Q0661, pin 2. Q0641 and R0641 disable the regulator when the radio is turned off. Input and output capacitors C0603 and C0611/C0612 reduce high frequency noise.

Diode VR0601 protects against transients and reverse polarity of the supply voltage.

2.2.2 Automatic On/Off

The radio software and/or external triggers turn the radio on or off without direct user action. For example, automatic turn on when ignition is sensed and off when ignition is off.

Q0661 provides the INT SW B+ voltage to the various radio circuits and to enable the voltage regulators via transistor Q0641 which contains a pnp and an npn transistor that provide an electronic on/off switch. The switch is on when the collector of the npn transistor within Q0661 is low . When the radio is off the collector is at supply voltage level. This effectively prevents current flow from emitter to collector of the pnp transistor. When the radio is turned on the voltage at the base of the npn transistor is pulled high and the pnp transistor switches on (saturation). With the INT SWB+ voltage now at supply voltage level, transistor Q0641 pulls pin 2 of the voltage regulators U0611 and U 0641 to ground level, enabling their outputs.

The electronic on/off circuits are enabled by the µP through ASFIC CMP port GCB2, line DC POWER ON, emergency switch (line EMERGENCY CONTROL), the mechanical On/Off/Volume knob on the control head (line ON OFF CONTROL), or the ignition sense circuits (line IGNITION CONTROL). If any of the four paths cause a low at the collector of the npn transistor within Q0661, the electronic "ON" is engaged.

2-4 Theory of Operation

2.2.3 Emergency

The emergency switch (J0501, pin 9), when engaged, grounds the base of Q0662 via the EMERGENCY CONTROL line. This switches Q0662 off and resistor R0662 pulls the collector of Q0662 and the base of Q0663 to levels above two volts. Transistor Q0663 then switches on and pulls the collector of the npn transistor within Q0661 to ground level This enables the voltage regulators via Q0641. When the emergency switch is released, R0541 pulls the base of Q0662 up to 0.6 volts causing the collector of transistor Q0662 to go low (0.2 volts), switching Q0663 off.

While the radio is on, the µP monitors the voltage at the emergency input on the accessory connector via pin 60 and the GP5 IN ACC9 line. Three different conditions can exit: no emergency, emergency, and open connection to the emergency switch. If no emergency switch is connected or the connection to the emergency switch is broken, the resistive divider R0541/R0512 sets the voltage to about 4.7 volts. If an emergency switch is connected, a resistor to ground within the emergency switch reduces the voltage on line GP5 IN ACC9 to inform the µP that the emergency switch is operational. An engaged emergency switch pulls line GP5 IN ACC9 to ground level. Diode D0179 limits the voltage to protect the µP input.

While the EMERGENCY CONTROL signal is low and INT SW B+ is on, the µP starts execution, reads that the emergency input is active through the voltage lev el of line GP5 IN ACC9, and sets the DC POWER ON output of the ASFIC CMP, pin 13 to a logic high. This keeps Q0661 and Q0641 switched to allow a momentary press of the emergency switch to power up the radio. When the µP has finished processing the emergency press, it sets the DC POWER ON line to a logic 0. This turns off Q0661 and the radio turns off. Notice that the µP is alerted to the emergency condition via line GP5 IN ACC9. If the radio is already on when the emergency is triggered, the DC POWER ON signal is already high.

2.2.4 Mechanical On/Off

This refers to the on/off/volume knob located on the control head which is used to turn the radio on and off and control the volume.

If the radio is turned off and the on/off/volume knob is pressed, line ON OFF CONTROL (J0401, pin

11) goes high and switches the radio’ s voltage regulators on as long as the button is pressed. The µP is alerted through line ON OFF SENSE (U0101, pin 6) which is pulled to low by Q0110 while the on/ off/volume knob is pressed. In addition, an interrupt is generated at µP, pin 96. The µP asserts line DC POWER ON via ASFIC CMP, pin 13 high which keeps the radio switched on. The µP switches the radio off by setting DC POWER ON to low via ASFIC CMP pin 13.

2.2.5 Ignition

Ignition sense prevents the radio from draining the vehicle’s battery because the engine is not running.

When the IGNITION input (J0501, pin 10) goes above 5 volts, Q0661 is turned on via line IGNITION CONTROL. Q0661 turns on INT SW B+ and the voltage regulators by turning on Q0641 and the µP starts ex ecution. The µP is alerted through line GP6 IN ACC10. While the on/off button is pressed, a high signal turns Q0181 on, which pulls µP, pin 74 to low. If the software detects a low state it asserts DC POWER ON via ASFIC, pin 13 high which keeps Q0661 and Q0641 and the radio switched on.

When the IGNITION input goes below 3 volts, Q0181 switches off and R0181 pulls µP, pin 74 to high. This alerts the software to switch off the radio by setting DC POWER ON to low. The next time the IGNITION input goes above 5 volts the above process is repeated.

Theory of Operation 2-5

2.2.6 Microprocessor Clock Synthesizer

The clock source for the µP system is generated by the ASFIC CMP (U0221). Upon power-up the synthesizer IC (FRAC-N) generates a 16.8 MHz waveform that is routed from the RF section to the ASFIC CMP, pin 34. For the main board controller the ASFIC CMP uses 16.8 MHz as a reference input clock signal for its internal synthesizer. The ASFIC CMP, in addition to the audio circuit, has a programmable synthesizer which can generate a synthesized signal ranging from 1200Hz to

32.769MHz in 1200Hz steps. When power is first applied, the ASFIC CMP generates its default 3.6864MHz CMOS square wave

UP CLK (on U0221, pin 28) and this is routed to the µP (U0101, pin 90). After the µP starts operation, it reprograms the ASFIC CMP clock synthesizer to a higher UP CLK frequency (usually

7.3728 or 14.7456 MHz) and continues operation. The ASFIC CMP may be reprogrammed to change the clock synthesizer frequencies at various

times depending on the software features that are executing. In addition, the clock frequency of the synthesizer is changed in small amounts if there is a possibility of harmonics of this clock source interfering with the desired radio receive frequency.

The ASFIC CMP synthesizer loop uses C0245, C0246 and R0241 to set the switching time and jitter of the clock output. If the synthesizer cannot generate the required clock frequency it switches back to its default 3.6864MHz output.

Because the ASFIC CMP synthesizer and the µP do not operate without the 16.8 MHz reference clock, the synthesizer and the voltage regulators should be checked first in debugging the system.

The µP uses crystal oscillator Y0131 and associated components to form a real time clock used to display the time on control heads (with display) or as time stamp for incoming calls or messages. The real time clock is powered from the voltage VSTBY to keep running while the radio is switched off. If the radio is disconnected from the supply voltage, the time must be reset.

2.2.7 Serial Peripheral Interface (SPI)

The µP communicates to many of the IC’s through its SPI port. This port consists of SPI TRANSMIT DATA (MOSI) (U0101, pin 100), SPI RECEIVE DATA (MISO) (U0101, pin 99), SPI CLK (U0101, pin

1) and chip select lines going to the various ICs. The BUS is a synchronous bus, in that the timing clock signal CLK is sent while SPI data (SPI TRANSMIT or RECEIVE) is sent. Therefore, whenever there is activity on either SPI TRANSMIT DATA or SPI RECEIVE DATA there should be a uniform signal on CLK.

The SPI TRANSMIT DATA sends serial data from the µP to a device, and SPI RECEIVE DATA is sends data from a device to the µP. On the controller there are two ICs on the SPI BUS: ASFIC CMP (U0221, pin 22), and EEPROM (U0111, pin 5). In the RF section there are two ICs on the SPI BUS: FRAC-N Synthesizer, and the Power Control IC (PCIC). The SPI TRANSMIT DATA and CLK lines going to the RF section are filtered by L0481/R0481 and L0482/R0482 to minimize noise. The chip select line CSX from U0101, pin 2 is shared by the ASFIC CMP, FRAC-N Synthesizer, and PCIC. Each of these IC‘s check the SPI data and when the sent address information matches the IC’s address, the data that follows is processed. The chip select lines for the EEPROM (EE CS), voice storage (VS CS), expansion board (EXP1 CS, EXP2 CS) and option board (OPT CS) are decoded by the address decoder U0141.

When the µP needs to program any of these IC’s it brings the chip select line CSX to a logic 0 and then sends the proper data and clock signals. The amount of data sent varies, for example the ASFIC CMP can receive up to 19 bytes (152 bits) while the PCIC can receive up to 6 bytes (48 bits). After the data is sent, the chip select line is returned to logic 1.

2-6 Theory of Operation

The option board interfaces are different in that the µP can also read data back from devices connected.The timing and operation of this interface is specific to the option connected, but the general pattern is as follows:

Option board generates a service request via J0551, pin 29, line RDY, and µP, pin 79

The main board asserts a chip select for that option board via U0141,pin 14, line OPT CS, J0551,pin 30

The main board µP generates the CLK (J0551, pin 3)

The main board µP writes serial data via J0551, pin 15 and reads serial data via J0551, pin 16

When data transfer is complete the main board terminates the chip select and CLK activity

2.2.8 SBEP Serial Interface

The SBEP serial interface allows the radio to communicate with the Customer Programming Software (CPS), or the universal tuner via the Radio Interface Box (RIB). This interface connects to the microphone connector via control head connector (J0401, pin 8) or to the accessory connector J0401, pin 17 and comprises BUS+. The line is bi-directional, meaning that either the radio or the RIB can drive the line. The µP sends serial data via pin 98 and D0101 and it reads serial data via pin

97. Whenever the µP detects activity on the BUS+ line, it starts communication. In addition, the SBEP serial interface is used to communicate with a connected control head. When a

control head key is pressed or the volume knob is rotated, the line ON OFF CONTROL goes high. This turns on transistor Q0110 which pulls line ON OFF SENSE and µP, pin 6 to ground level. In addition, an interrupt is generated via R0109 (for SELECT 5 / MDC models) or R0128, U0125, pins 17/26 (for MPT models) and µP, pin 96. This indicates that the control head wants to start SBEP communication. The µP then reads the registers of the Universal Asynchronous Receiver T r ansmitter (UART) U0125 to determine whether the interrupt source was the control head or the UART (MPT models only). If the interrupt source was from the control head, the µP requests the data from the control head. The control head starts sending and after all data has been sent, the ON OFF CONTROL line goes low. The control head ignores any data on BUS+ during SBEP communication with the CPS or universal tuner.

2.2.9 General Purpose Input/Output

The controller provides eight general purpose lines (DIG1 through DIG8) available on the accessory connector J0501 to interface the external options. Lines DIG IN 1,3,5,6, are inputs, DIG OUT 2 is an output and DIG IN OUT 4,7,8 are bidirectional. The software and the hardware of the radio model define the function of each port.

DIG IN 1 can be used as external PTT input or others, set by the CPS. The µP reads this port via pin 77 and Q0171.

DIG OUT 2 can be used as normal output or external alarm output, set by the CPS. Transistor Q0173 is controlled by the µP via ASFIC CMP, pin 14.

DIG IN 3 is read by µP, pin 63 via resistor R0176 DIG IN 5 can be used as normal input or emergency input, set by the CPS. The µP reads this port via

R0179 and µP, pin 60. Diode D0179 limits the voltage to protect the µP input. DIG IN 6 can be used as normal input, set by the CPS. The µP reads this port via, pin 74 and Q0181. DIG IN OUT 4,7,8 are bidirectional and use the same circuit configuration. Each port uses an output

transistor Q0177, Q0183, Q0185 controlled by µP, pins 46, 47, 53. The ports are read by µP, pins 75, 54, 76. To use one of the ports as input the µP must turn off the corresponding output transistor.

In addition the signals from DIG IN 1, DIG IN OUT 4 are fed to the option board connector J0551 and the expansion board connector J0451.

Theory of Operation 2-7

2.2.10 Normal Microprocessor Operation

The µP is configured to operate in one of two modes: expanded or bootstrap. In expanded mode, the µP uses external memory devices to operate. In bootstrap mode, the µP uses only its internal memory.

During normal operation of the radio, the µP is operating in expanded mode and the µP (U0101) has access to three external memory devices: U0121 (EEPROM), U0122 (SRAM), and U0111 (EEPROM). Also, within the µP there are three KBs of internal RAM, as well as logic to select external memory devices.

The external EEPROM (U0111) space contains the information in the radio which is customer specific, referred to as the codeplug. This information consists of items such as:

Band in which the radio operates

What frequencies are assigned to what channel

Tuning information.

The external SRAM (U0122) as well as the µP’s own internal RAM space are used for temporary calculations required by the software during execution. All of the data stored in both of these locations is lost when the radio powers off (See the particular device subsection for more details).

The µP provides an address bus of 16 address lines (ADDR 0 - ADDR 15), and a data bus of eight data lines (DATA 0 - DATA 7). There are also three control lines: CSPROG (U0101, pin 38) to chip select U0121, pin 30 (EEPROM), CSGP2 (U0101, pin 41) to chip select U0122, pin 20 (SRAM) and PG7 R W (U0101, pin 4) to select whether to read or to write. The external EEPROM (U0111,pin 1), the OPTION BOARD and EXPANSION BOARD are selected by three lines of the µP using address decoder U0141. The chips ASFIC CMP / FRAC-N / PCIC are selected by line CSX (U0101, pin 2).

When the µP is functioning normally, the address and data lines are toggling at CMOS logic levels. Specifically, the logic high levels should be between 4.8 to 5.0 volts, and the logic low levels should be between 0 to 0.2 volts. No other intermediate levels should be observed, and the rise and fall times should be <30ns.

The low-order address lines (ADDR 0 - ADDR 7) and the data lines (DATA 0-DATA 7) should be toggling at a high rate, e. g., you should set your oscilloscope sweep to 1µs/div. or faster to observe individual pulses. High speed CMOS transitions should also be observed on the µP control lines.On the µP the lines XIRQ (U0101, pin 48), MODA LIR (U0101, pin 58), MODB VSTPY (U0101, pin 57) and RESET (U0101, pin 94) should be high at all times during normal operation. Whenever a data or address line becomes open or shorted to an adjacent line, a common symptom is that the RESET line goes low periodically, with the period being in the order of 20msecs. In the case of shorted lines you may also detect the line periodically at an intermediate level, i.e. around 2.5 volts when two shorted lines attempt to drive to opposite rails.

The MODA LIR (U0101, pin 58) and MODB VSTPY (U0101, pin 57) inputs to the µP must be at a logic 1 for it to start executing correctly . After the µP starts execution it periodically pulses these lines to determine the desired operating mode. While the central processing unit (CPU) is running, MODA LIR is an open-drain CMOS output which goes low whenever the µP begins a new instruction. One instruction typically requires 2-4 external bus cycles, or memory fetches.

There are eight analog-to-digital converter ports (A/D) on U0101 labelled within the device block as PE0-PE7. These lines sense the voltage level ranging from 0 to 5V of the input line and convert that level to a number ranging from 0 to 255 which is read by the software to take appropriate action.

For example U0101, pin 67 is the battery voltage detect line. R0671 and R0672 form a resistor divider on INT SWB+. With 30K and 10K and a voltage range of 11V to 17V, that A/D port is 2.74V to

4.24V which is then be converted to ~140 to 217 respectively.

2-8 Theory of Operation

U0101-69 is the high reference voltage for the A/D ports on the µP. Capacitor C0101 filters the +5 volt reference. If this voltage is lower than +5 volt, the A/D reading is incorrect. Likewise U0101, pin 68 is the low reference for the A/D ports. This line is normally tied to ground. If this line is not connected to ground, the A/D readings could be incorrect.

2.2.11 Static Random Access Memory (SRAM)

The SRAM (U0121) contains temporary radio calculations or parameters that can change very frequently, and which are generated and stored by the software during its normal operation. The information is lost when the radio is turned off.

The device allows an unlimited number of write cycles. SRAM accesses are indicated by the CS signal U0122, pin 20 which is the result of U0101-CSGP2 going low. U0122 is commonly referred to as the external RAM as opposed to the internal RAM which is the 3 KBs of RAM (part of the 68HC11FL0). Both RAM spaces serve the purpose. However, the internal RAM is used for the calculated values which are accessed most often.

Capacitor C0122 filters out any ac noise which may ride on +5V at U0122.

2.3 Controller Board Audio and Signalling Circuits

2.3.1 Audio Signalling Filter IC with Compander (ASFIC CMP)

The ASFIC CMP (U0221) used in the controller has the four following functions:

RX/TX audio shaping, i.e. filtering, amplification, attenuation

RX/TX signalling, PL/DPL/HST/MDC/MPT

Squelch detection

µP clock signal generation

The ASFIC CMP is programmable through the SPI BUS (U0221-20/21/22), normally receiving 19 bytes. This programming sets up various paths within the ASFIC CMP to route audio and/or signalling signals through the appropriate filtering, gain, and attenuator blocks. The ASFIC CMP also has six general control bits (GCB0-5) which are CMOS level outputs and used for NOISE BLANKER (GCB0) in low band radios, EXTERNAL ALARM (GCB1), and DC POWER ON (GCB2) to switch the voltage regulators (and the radio) on and off. GCB3 controls U0251, pin 11 to output either RX FLAT AUDIO or RX FILTERED AUDIO on the accessory connector, pin 11. GCB4 controls U0251, pin 10 to use either the external microphone input or the voice storage playback signal. GCB5 switches the audio PA on and off.

Theory of Operation 2-9

2.3.2 Transmit Audio Cir cuits

Refer to Figure 2-3 for the descriptions that follow.

J0451

TX RTN

MIC

EXT MIC

FLAT TX

AUDIO

FLAT

EXPANSION BOARD

CONTROL HEAD

CONNECTOR

ACCESSORY CONNECTOR

J0401

J0501

TP0221

TP0222

2.3.3 Microphone Input Path

The radio supports two microphone input paths. One from the control head external microphone accessory connector J0501, pin 2, and one from the microphone auxiliary path (FLAT TX AUDIO) via accessory connector J0501, pin 5. The microphones require a DC biasing voltage provided by a resistive network.

J0551

OPTION

OUT

BOARD

OUT

44 TX SND

MIC INT

MIC

ASFIC_CMP

U0221

MIC EXT

48 42

AUX TX

LIMITER

HS SUMMER

SPLATTER

FILTER

LS SUMMER

36 TX RTN

FILTERS AND

PREEMPHASIS

ATTENUATOR

Figure 2-3. Transmit Audio Paths

VCO

ATN

MOD IN

TO RF

SECTION

(SYNTHESIZER)

The two microphone audio input paths enter the ASFIC CMP at U0221, pin 48 (external microphone) and U0221, pin 46 (auxiliary microphone).

The microphone is plugged into the radio control head which is connected to the controller board via J0401, pin 9. The signal is then routed via R0409 and line INT MIC to R0205. Resistors R0201 and R0202 provide 9.3Vdc bias. Resistive divider R0205/R0207 divide the input signal by 5.5 and provide input protection for the CMOS amplifier input. R0202 and C0201 provide a 560 ohm AC path to ground that sets the input impedance for the microphone and determines the gain based on the emitter resistor in the microphone’s amplifier circuit.

Capacitor C0204 provides dc blocking. The audio signal at U0221, pin 46 (TP0221) is approximately 14mV for 1.5kHz or 3kHz of deviation with 12.5kHz or 25kHz channel spacing.

The external microphone signal enters the radio on accessory connector J0501, pin 5, then it is routed via line EXT MIC to resistor R0206. Resistors R0201 and R0204 provide a 9.3Vdc bias. Resistive divider R0206 / R0208 divide the input signal by 5.5 and provide input protection for the CMOS amplifier input. R0204 and C0201 provide a 560 ohm AC path to ground that sets the input impedance for the microphone and determines the gain based on the emitter resistor in the microphone’s amplifier circuit. Capacitor C0254 provides dc blocking.

2-10 Theory of Operation

Multi switch U0251 controlled by ASFIC CMP port GCB4 selects either the external microphone input signal or the voice storage playback signal for entering the ASFIC CMP at pin 48. The audio signal at U0221-48 (TP0222) is approximately 14mVrms for 1.5kHz or 3kHz of deviation with

12.5kHz or 25kHz channel spacing. The FLAT TX AUDIO signal from accessory connector J0501-5 is fed to the ASFIC CMP (U0221, pin

42) through C0541 and line FLAT TX RTN. The ASFIC has an internal AGC that controls the gain in the microphone audio path. The AGC can

be disabled/enabled by the µP. Another feature that can be enabled/disabled in the ASFIC is the VOX. This circuit, along with the capacitor at U0221, pin 7, provides a dc voltage allows the µP to detect microphone audio. The ASFIC can also be programmed to route the microphone audio to a speaker for public address operation.

2.3.3.1 PTT Sensing and TX Audio Processing

The microphone PTT signal coming from the control head is sent via the SBEP bus to the µP. An external PTT can be generated by grounding pin 3 on the accessory connector if this input is programmed for PTT by the CPS. When microphone PTT is sensed, the µP always configures the ASFIC CMP for the "internal" microphone audio path, and external PTT results in the external microphone audio path being selected.

Inside the ASFIC CMP, the microphone audio is filtered to eliminate frequency components outside the 300-3000Hz voice band, and pre-emphasized if pre-emphasis is enabled. The signal is then limited to prevent the transmitter from over deviating. The limited microphone audio is then routed through a summer, which is used to add in signalling data, and then to a splatter filter to eliminate high frequency spectral components that could be generated by the limiter. The audio is then routed to an attenuator, which is tuned in the factory or the field to set the proper amount of FM deviation. The TX audio emerges from the ASFIC CMP at U0221-40 MOD IN, at which point it is routed to the RF section.

2.3.3.2 TX Secure Audio (optional)

The audio follows the normal transmit audio processing until it emerges from the ASFIC CMP TX SND pin (U0221-44), which is fed to the Secure board residing at option connector J0551-33. The Secure board contains circuits to amplify, encrypt, and filter the audio. The encrypted signal is then fed back from J0551-32 to the ASFIC CMP TX RTN input (U0221-36). The signal level at this pin should be about 65mVrms. The signal is then routed through the TX path in the ASFIC CMP and emerges at MOD IN pin 40.

2.3.3.3 Option Board Transmit Audio

The audio follows the normal transmit audio processing until it emerges from the ASFIC CMP TX SND pin (U0221-44), which is fed to the option board residing at option connector J0551-33. The option board contains circuits to process the audio. The processed signal is then fed back from J0551-32 to the ASFIC CMP TX RTN input (U0221-36). The signal level at this pin is approximately 65mVrms. The signal is then routed through the TX path in the ASFIC CMP and out at MOD IN, pin

40.

Theory of Operation 2-11

2.3.4 Transmit Signalling Circuits

Refer to Figure 2-4 for the descriptions that follow.

Figure 2-4. Transmit Signalling Paths

The three types of transmit signalling paths are as follows:

• Sub-audible data (PL/DPL/connect tone) summed with transmit voice or signalling

• DTMF data for telephone communication between trunked and conventional systems

• Audible signalling

NOTE

All three types are supported by the hardware while the radio software determines which signalling type is available.

2.3.4.1 Sub-Audible Data (PL/DPL)

Sub-audible data implies signalling whose frequency/data rate is below 300Hz. PL and DPL waveforms are used for conventional operation and connect tones for trunked voice channel operation. The trunking connect tone is simply a PL tone at a higher deviation level than PL in a conventional system. Although it is referred to as "sub-audible data," the actual frequency spectrum of these waveforms may be as high as 250 Hz, which is audible to the human ear. Howe v er , the radio receiver filters out any audio below 300Hz, so these tones are never heard in the actual system.

Only one type of sub-audible data can be generated by U0221 (ASFIC CMP) at any one time. The process is as follows, using the SPI BUS, the µP programs the ASFIC CMP to set up the proper lowspeed data deviation and select the PL or DPL filters. The µP then generates a square wave which strobes the ASFIC PL / DPL encode input LSIO U0221-18 at twelve times the desired data rate. For example, for a PL frequency of 103Hz, the frequency of the square wave is 1236Hz.

This drives a tone generator inside U0221 which generates a staircase approximation to a PL sine wave or DPL data pattern. This internal wavef orm is then low-pass filtered and summed with voice or data. The resulting summed waveform then appears on U0221-40 (MOD IN), where it is sent to the RF board as previously described for transmit audio. A trunking connect tone would be generated in the same manner as a PL tone.

2-12 Theory of Operation

2.3.4.2 High Speed Data

High speed data refers to the 3600 baud data waveforms, known as inbound signalling words (ISWs) used in a trunking system for high speed communication between the central controller and the radio. To generate an ISW, the µP first programs the ASFIC CMP (U0221) to the proper filter and gain settings. It then begins strobing U0221-19 (HSIO) with a pulse when the data is supposed to change states. U0221’s 5-3-2 state encoder, which is in a 2-state mode, is then fed to the post-limiter summer block and then the splatter filter. From that point, it is routed through the modulation attenuators and then out of the ASFIC CMP to the RF board. MPT 1327 and MDC are generated in much the same way as trunking ISW. However, in some cases these signals may also pass through a data pre-emphasis block in the ASFIC CMP. Also these signalling schemes are based on sending a combination of 1200 Hz and 1800 Hz tones only. Microphone audio is muted during high speed data signalling.

2.3.4.3 Dual Tone Multiple Frequency (DTMF) Data

DTMF data is a dual tone waveform used during phone interconnect operation. It is the same type of tones which are heard when using a "Touch Tone" telephone.

There are seven frequencies, with four in the low group (697, 770, 852, 941Hz) and three in the high group (1209, 1336, 1477Hz).

The high-group tone is generated by the µP (U0101-44) strobing U0221-19 at six times the tone frequency for tones less than 1440Hz or twice the frequency for tones greater than 1440Hz. The low group tone is generated by the ASFIC CMP, controlled by the µP via SPI bus. Inside U0221 the lowgroup and high-group tones are summed (with the amplitude of the high group tone being approximately 2 dB greater than that of the low group tone) and then pre-emphasized before being routed to the summer and splatter filter. The DTMF waveform then follows the same path as described for high-speed data

Theory of Operation 2-13

2.3.5 Receive Audio Circuits

Refer to Figure 2-5 for the descriptions that follow.

ACCESSORY CONNECTOR

3 2

HANDSET

AUDIO

FLT RX AUDIO

EXTERNAL

INTERNAL

SPEAKER

OPTION

BOARD

J0551

FROM

SECTION

(IF IC)

J0451

EXPANSION

BOARD

DISC

AUDIO

OUT

U0101

SPKR +

SPKR -

INT

SPKR-

CONTROLHEAD

CONNECTOR

LS IO

SQ DET

J0501

J0401

AUDIO

U0271

INT

SPKR+

U IO

AUX RX

DISC

4110

AUDIO

URX OUT

VOLUME

ATTEN.

FILTER AND

DEEMPHASIS

LIMITER, RECTIFIER

FILTER, COMPARATOR

CH ACT

ASFIC_CMP U0221

PL FILTER

LIMITER

SQUELCH

CIRCUIT

MICRO

CONTROLLER

2.3.5.1 Squelch Detect

The squelch detect circuits are all contained within the ASFIC CMP as shown in Figure 2-5. The radio’s RF circuits are constantly producing an output (DISC AUDIO) at the discriminator IF IC. The output signal is applied to the ASFIC CMP’s squelch detect circuits DISC input (U0221, pin 2). The squelch signal entering the ASFIC CMP is amplified, filtered, attenuated, and rectified. It is then sent to a comparator to produce an active high signal (CH ACT). The squelch circuit produces the SQ DET signal at U0221, pin 17 from the CH ACT input signal. The state of CH ACT and SQ DET go from a low (logic 0) to a high (logic 1) when an RF carrier is detected. The CH ACT and SQ DET signals from the squelch circuit are applied to the µP pins 84 and 83 respectively.

SQ DET is used to determine all audio mute/unmute decisions except for conventional scan. In this case CH ACT is a pre-indicator as it occurs slightly faster than SQ DET.

Figure 2-5. Receive Audio Paths

2-14 Theory of Operation

2.3.5.2 Audio Processing and Digital Volume Control

The receiver audio signal (DISC AUDIO) enters the controller section from the IF IC where it is AC coupled by C0227 before entering the ASFIC CMP via the DISC input at U0221, pin 2. The signal is then applied to both the audio and the PL/DPL paths.

The signal on the audio path is applied to a programmable amplifier, whose setting is based on the channel bandwidth being received, an LPF filter to remove any frequency components above 3000Hz, and HPF filter to strip off any sub-audible data below 300Hz. The recovered audio passes through a de-emphasis filter, if it is enabled, to compensate for pre-emphasis which is used to reduce the effects of FM noise. The audio then goes through the 8-bit programmable attenuator whose level is set depending on the value of the volume control. The resulting filtered audio signal is passed through an output buffer within the ASFIC CMP and exits the ASFIC CMP at the AUDIO output (U0221, pin 41).

The µP programs the attenuator, using the SPI BUS, based on the volume setting. The minimum/ maximum settings of the attenuator are set by codeplug parameters.

Since sub-audible signalling is summed with voice information on transmit, it must be separated from the voice information before processing. Any sub-audible signal enters the ASFIC CMP from the IF IC at DISC U0221, pin 2, then through the PL/DPL path. The signal first passes through one of two low pass filters, either PL low pass filter, or DPL/LST low pass filter. Either signal is then filtered, goes through a limiter, and exits the ASFIC CMP at LSIO (U0221, pin 18). At this point the signal appears as a square wave version of the sub-audible signal the radio received. The µP (U0101, pin 80) decodes the signal directly to determine if it is the tone/code currently active on that mode.

2.3.5.3 Audio Amplification Speaker (+) Speaker (-)

The output of the ASFIC CMP’s digital volume pot (U0221, pin 41) is routed through dc blocking capacitor C0256 to a buffer formed by U0211, pin 1. Resistors R0256 and R0268 set the correct input level to the audio PA (U0271). This is necessary because the gain of the audio PA is 46 dB and the ASFIC CMP output is capable of overdriving the PA unless the maximum volume is limited. Resistor R0267 and capacitor C0267 increase frequency components below 350 Hz.

The audio then passes through R0269 and C0272 which provides AC coupling and low frequency roll-off. C0273 provides high frequency roll-off as the audio signal is routed to audio power amplifier U0271, pins 1 and 9 which are both tied to the received audio. The audio power amplifier has one inverted and one non-inverted output that produces the differential audio output SPK+/SPK- (U0271, pins 4 and 6).

The audio PA’s dc biases are not activated until the audio PA is enabled at pin 8. The audio PA is enabled via the ASFIC CMP (U0221, pin 38). When the base of Q0271 is low, the transistor is off and U0271-8 is high via pull-up resistor R0273, and the audio PA is ON. The voltage at U0273-8 must be above 8.5Vdc to properly enable the device. If the voltage is between 3.3 and 6.4V, the device is active, but has its input (U0273, pins 1 and 9) off. This is a mute condition used to prevent an audio pop when the PA is enabled.

The SPK+ and SPK- outputs of the audio PA are dc biased and vary proportionately with FLT A+ (U0271, pin 7). FLT A+ of 11V yields a dc offset of 5V, and FLT A+ of 17V yields a dc offset of 8.5V. If either of these lines is shorted to ground, it is possible that the audio PA could be damaged. SPK+ and SPK- are routed to the accessory connector (J0501, pins 1 and 16) and to the control head connector (J0401, pins 2 and 3).

Theory of Operation 2-15

2.3.5.4 Handset Audio

Certain accessories have a self contained speaker which requires a different voltage level than that provided by U0271. For those devices, HANDSET AUDIO is available at control head connector J0401, pin 7.

The received audio from the output of the ASFIC CMP’s digital volume attenuator and buffered by U0211, pin 1, is also routed to U0211, pin 9 where it is amplified by 20 dB. This is set by the 10k/ 100k combination of R0261 and R0262. This signal is routed from the output of the op amp U0211 to J0401-7. The control head sends this signal directly out to the microphone jack. The maximum value of this output is 6.6Vp-p.

2.3.5.5 Filtered Audio and Flat Audio

The ASFIC CMP audio output at U0221, pin 39 is filtered and de-emphasized, but has not yet gone through the digital volume attenuator. From ASFIC CMP U0221, pin 39 the signal is routed via R0251 through gate U0251, pin 12 and AC coupled to U0211, pin 2. The gate controlled by ASFIC CMP port GCB3 (U0221, pin 35) selects between the filtered audio signal from the ASFIC CMP at pin 39 (URXOUT) or the unfiltered flat audio signal from the ASFIC CMP, U10, pin 10. Resistors R0251 and R0253 determine the gain of op amp U0211, pin 2 for the filtered audio while R0252 and R0253 determine the gain for the flat audio.The output of U0253, pin 7 is then routed to J0501, pin 11 via dc blocking capacitor C0542. Note that any volume adjustment of the signal on this path must be done by the accessory.

2.3.5.6 RX Secure Audio Option

Discriminator audio, which is now encrypted audio, follows the normal receive audio processing until it is output from the ASFIC CMP UIO (U0221, pin 10), which is fed to the secure audio board at option connector J0551, pin 35. On the secure board, the encrypted signal is converted back to normal audio format, then fed back through J0551, pin 34 to AUX RX of the ASFIC CMP (U0221, pin

43). The signal then follows a path identical to the conventional receive audio, where it is filtered (0.3

- 3kHz) and deemphasized. The signal URX SND from the ASFIC CMP (U0221-39) also routed to option connector J0551, pin 28, is not used for the secure board, but for other option boards.

2.3.5.7 Option Board Receive Audio

Unfiltered audio from the ASFIC CMP (U0221, pin 10) enters the option board at connector J0551, pin 35. Filtered audio from the ASFIC CMP URXOUT (U0221, pin 39) enters the option board at connector J0551, pin 28. On the option board, the signal is processed, then fed back through (J0551, pin 34) to AUX RX of the ASFIC CMP (U0221, pin 43). The signal then follows a path identical to conventional receive audio, where it is filtered (0.3 - 3kHz) and de-emphasized.

2-16 Theory of Operation

2.3.6 Receive Signalling Circuits

Refer to Figure 2-6 for the descriptions that follow.

DET AUDIO

DISCRIMINATOR AUDIO

FROM RF SECTION

(IF IC)

DATA FILTER

AND DEEMPHASIS

DISC

PLEAP

ASFIC_CMP

FILTER

LIMITER

U0221

PLCAP2

LIMITER

HSIO

LSIO

Figure 2-6. Receive Signalling Paths

2.3.6.1 Sub-Audible Data (PL/DPL) and High Speed Data Decoder

The ASFIC CMP (U0221) filters and limits all received data. The data enters the ASFIC CMP at input DISC (U0221, pin 2). Inside U0221 the data is filtered according to data type (HS or LS), then it is limited to a 0-5V digital level. The MDC and trunking high speed data appear at U0221, pin 19, where it connects to the µP U0101, pin 82

The low speed limited data output (PL, DPL, and trunking LS) appears at U0221, pin 18, where it connects to the µP U0101, pin 80.

The low speed data is read by the µP at twice the frequency of the sampling waveform; a latch configuration in the ASFIC CMP stores one bit every clock cycle. The external capacitors C0236, and C0244 set the low frequency pole for a zero crossings detector in the limiters for PL and HS data. The hysteresis of these limiters is programmed based on the type of received data.

MICRO

CONTROLLER

U0101

2.3.6.2 Alert Tone Circuits

When the software determines that it needs to give the operator an audible feedback for a good key press, or for a bad key press, or radio status (trunked system busy, phone call, circuit failures), it sends an alert tone to the speaker. It does so by sending SPI BUS data to U0221 which sets up the audio path to the speaker for alert tones. The alert tone itself can be generated in one of two ways: internally by the ASFIC CMP, or externally using the µP and the ASFIC CMP.

The allowable internal alert tones are 304, 608, 911, and 1823Hz. In this case a code contained within the SPI BUS load to the ASFIC CMP sets up the path and determines the tone frequency, and at what volume level to generate the tone. (It does not have to be related to the voice volume setting).

For external alert tones, the µP can generate any tone within the 100-3000Hz audio band. This is accomplished by the µP generating a square wave which enters the ASFIC CMP at U0221-19. Inside the ASFIC CMP this signal is routed to the alert tone generator

The output of the generator is summed into the audio chain just after the RX audio de-emphasis block. Inside U0221 the tone is amplified and filtered, then passed through the 8-bit digital volume attenuator, which is typically loaded with a special value for alert tone audio. The tone exits at U022141 and is routed to the audio PA like receive audio.

+ 79 hidden pages

Motorola de servcio PRO movil Diagram

Specifications and Main Features

Frequently Asked Questions

User Manual

SAFETY INFORMATION

SAFE AND EFFICIENT OPERATION OF MOTOROLA TWO-WAY RADIOS

EXPOSURE TO RADIO FREQUENCY ENERGY

PORTABLE RADIO OPERATION AND EME EXPOSURE

ELECTROMAGNETIC INTERFERENCE/COMPATIBILITY

OPERATIONAL WARNINGS

OPERATIONAL CAUTIONS

INTRINSICALLY SAFE RADIO INFORMATION

FMRC Approved Equipm en t

Repair of FMRC Approved Products

Repair

Do Not Substitute Options or Accessories

TABLE OF CONTENTS

1.1 Scope of Manual

1.2 Warranty and Service Support

1.2.1 Warranty Period

1.2.2 Return In structions

1.2.3 After Warranty Period

1.3 Related Documents

1.4 Technical Support

Warranty and Repairs 1-3

1.7 Radio Model Information

2.1 Overview

2.2 Controller

Figure 2-1. Controller Block Diagram

2.2.1 Radio Power Distribution

Figure 2-2. DC Power Distribution Block Diagram

2.2.2 Automatic On/Off

2.2.3 Emergency

2.2.4 Mechanical On/Off

2.2.5 Ignition

2.2.6 Microprocessor Clock Synthesizer

2.2.7 Serial Peripheral Interface (SPI)

2.2.8 SBEP Serial Interface

2.2.9 General Purpose Input/Output

2.2.10 Normal Microprocessor Operation

2.2.11 Static Random Access Memory (SRAM)

2.3 Controller Board Audio and Signalling Circuits

2.3.1 Audio Signalling Filter IC with Compander (ASFIC CMP)

2.3.2 Transmit Audio Cir cuits

2.3.3 Microphone Input Path

Figure 2-3. Transmit Audio Paths

2.3.3.1 PTT Sensing and TX Audio Processing

2.3.3.2 TX Secure Audio (optional)

2.3.3.3 Option Board Transmit Audio

2.3.4 Transmit Signalling Circuits

Figure 2-4. Transmit Signalling Paths

2.3.4.1 Sub-Audible Data (PL/DPL)

2.3.4.2 High Speed Data

2.3.4.3 Dual Tone Multiple Frequency (DTMF) Data

2.3.5 Receive Audio Circuits

2.3.5.1 Squelch Detect

Figure 2-5. Receive Audio Paths

2.3.5.2 Audio Processing and Digital Volume Control

2.3.5.3 Audio Amplification Speaker (+) Speaker (-)

2.3.5.4 Handset Audio

2.3.5.5 Filtered Audio and Flat Audio

2.3.5.6 RX Secure Audio Option

2.3.5.7 Option Board Receive Audio

2.3.6 Receive Signalling Circuits

Figure 2-6. Receive Signalling Paths

2.3.6.1 Sub-Audible Data (PL/DPL) and High Speed Data Decoder

2.3.6.2 Alert Tone Circuits